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1/*
2 * linux/drivers/video/pxafb.c
3 *
4 * Copyright (C) 1999 Eric A. Thomas.
5 * Copyright (C) 2004 Jean-Frederic Clere.
6 * Copyright (C) 2004 Ian Campbell.
7 * Copyright (C) 2004 Jeff Lackey.
8 * Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas
9 * which in turn is
10 * Based on acornfb.c Copyright (C) Russell King.
11 *
12 * This file is subject to the terms and conditions of the GNU General Public
13 * License. See the file COPYING in the main directory of this archive for
14 * more details.
15 *
16 * Intel PXA250/210 LCD Controller Frame Buffer Driver
17 *
18 * Please direct your questions and comments on this driver to the following
19 * email address:
20 *
21 * [email protected]
22 *
23 * Add support for overlay1 and overlay2 based on pxafb_overlay.c:
24 *
25 * Copyright (C) 2004, Intel Corporation
26 *
27 * 2003/08/27: <[email protected]>
28 * 2004/03/10: <[email protected]>
29 * 2004/10/28: <[email protected]>
30 *
31 * Copyright (C) 2006-2008 Marvell International Ltd.
32 * All Rights Reserved
33 */
34
35#include <linux/module.h>
36#include <linux/moduleparam.h>
37#include <linux/kernel.h>
38#include <linux/sched.h>
39#include <linux/errno.h>
40#include <linux/string.h>
41#include <linux/interrupt.h>
42#include <linux/slab.h>
43#include <linux/mm.h>
44#include <linux/fb.h>
45#include <linux/delay.h>
46#include <linux/init.h>
47#include <linux/ioport.h>
48#include <linux/cpufreq.h>
49#include <linux/platform_device.h>
50#include <linux/dma-mapping.h>
51#include <linux/clk.h>
52#include <linux/err.h>
53#include <linux/completion.h>
54#include <linux/mutex.h>
55#include <linux/kthread.h>
56#include <linux/freezer.h>
57#include <linux/console.h>
58#include <linux/of_graph.h>
59#include <linux/regulator/consumer.h>
60#include <linux/soc/pxa/cpu.h>
61#include <video/of_display_timing.h>
62#include <video/videomode.h>
63#include <linux/string_choices.h>
64
65#include <asm/io.h>
66#include <asm/irq.h>
67#include <asm/div64.h>
68#include <linux/platform_data/video-pxafb.h>
69
70/*
71 * Complain if VAR is out of range.
72 */
73#define DEBUG_VAR 1
74
75#include "pxafb.h"
76#include "pxa3xx-regs.h"
77
78/* Bits which should not be set in machine configuration structures */
79#define LCCR0_INVALID_CONFIG_MASK (LCCR0_OUM | LCCR0_BM | LCCR0_QDM |\
80 LCCR0_DIS | LCCR0_EFM | LCCR0_IUM |\
81 LCCR0_SFM | LCCR0_LDM | LCCR0_ENB)
82
83#define LCCR3_INVALID_CONFIG_MASK (LCCR3_HSP | LCCR3_VSP |\
84 LCCR3_PCD | LCCR3_BPP(0xf))
85
86static int pxafb_activate_var(struct fb_var_screeninfo *var,
87 struct pxafb_info *);
88static void set_ctrlr_state(struct pxafb_info *fbi, u_int state);
89static void setup_base_frame(struct pxafb_info *fbi,
90 struct fb_var_screeninfo *var, int branch);
91static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal,
92 unsigned long offset, size_t size);
93
94static unsigned long video_mem_size = 0;
95
96static inline unsigned long
97lcd_readl(struct pxafb_info *fbi, unsigned int off)
98{
99 return __raw_readl(fbi->mmio_base + off);
100}
101
102static inline void
103lcd_writel(struct pxafb_info *fbi, unsigned int off, unsigned long val)
104{
105 __raw_writel(val, fbi->mmio_base + off);
106}
107
108static inline void pxafb_schedule_work(struct pxafb_info *fbi, u_int state)
109{
110 unsigned long flags;
111
112 local_irq_save(flags);
113 /*
114 * We need to handle two requests being made at the same time.
115 * There are two important cases:
116 * 1. When we are changing VT (C_REENABLE) while unblanking
117 * (C_ENABLE) We must perform the unblanking, which will
118 * do our REENABLE for us.
119 * 2. When we are blanking, but immediately unblank before
120 * we have blanked. We do the "REENABLE" thing here as
121 * well, just to be sure.
122 */
123 if (fbi->task_state == C_ENABLE && state == C_REENABLE)
124 state = (u_int) -1;
125 if (fbi->task_state == C_DISABLE && state == C_ENABLE)
126 state = C_REENABLE;
127
128 if (state != (u_int)-1) {
129 fbi->task_state = state;
130 schedule_work(&fbi->task);
131 }
132 local_irq_restore(flags);
133}
134
135static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
136{
137 chan &= 0xffff;
138 chan >>= 16 - bf->length;
139 return chan << bf->offset;
140}
141
142static int
143pxafb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
144 u_int trans, struct fb_info *info)
145{
146 struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
147 u_int val;
148
149 if (regno >= fbi->palette_size)
150 return 1;
151
152 if (fbi->fb.var.grayscale) {
153 fbi->palette_cpu[regno] = ((blue >> 8) & 0x00ff);
154 return 0;
155 }
156
157 switch (fbi->lccr4 & LCCR4_PAL_FOR_MASK) {
158 case LCCR4_PAL_FOR_0:
159 val = ((red >> 0) & 0xf800);
160 val |= ((green >> 5) & 0x07e0);
161 val |= ((blue >> 11) & 0x001f);
162 fbi->palette_cpu[regno] = val;
163 break;
164 case LCCR4_PAL_FOR_1:
165 val = ((red << 8) & 0x00f80000);
166 val |= ((green >> 0) & 0x0000fc00);
167 val |= ((blue >> 8) & 0x000000f8);
168 ((u32 *)(fbi->palette_cpu))[regno] = val;
169 break;
170 case LCCR4_PAL_FOR_2:
171 val = ((red << 8) & 0x00fc0000);
172 val |= ((green >> 0) & 0x0000fc00);
173 val |= ((blue >> 8) & 0x000000fc);
174 ((u32 *)(fbi->palette_cpu))[regno] = val;
175 break;
176 case LCCR4_PAL_FOR_3:
177 val = ((red << 8) & 0x00ff0000);
178 val |= ((green >> 0) & 0x0000ff00);
179 val |= ((blue >> 8) & 0x000000ff);
180 ((u32 *)(fbi->palette_cpu))[regno] = val;
181 break;
182 }
183
184 return 0;
185}
186
187static int
188pxafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
189 u_int trans, struct fb_info *info)
190{
191 struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
192 unsigned int val;
193 int ret = 1;
194
195 /*
196 * If inverse mode was selected, invert all the colours
197 * rather than the register number. The register number
198 * is what you poke into the framebuffer to produce the
199 * colour you requested.
200 */
201 if (fbi->cmap_inverse) {
202 red = 0xffff - red;
203 green = 0xffff - green;
204 blue = 0xffff - blue;
205 }
206
207 /*
208 * If greyscale is true, then we convert the RGB value
209 * to greyscale no matter what visual we are using.
210 */
211 if (fbi->fb.var.grayscale)
212 red = green = blue = (19595 * red + 38470 * green +
213 7471 * blue) >> 16;
214
215 switch (fbi->fb.fix.visual) {
216 case FB_VISUAL_TRUECOLOR:
217 /*
218 * 16-bit True Colour. We encode the RGB value
219 * according to the RGB bitfield information.
220 */
221 if (regno < 16) {
222 u32 *pal = fbi->fb.pseudo_palette;
223
224 val = chan_to_field(red, &fbi->fb.var.red);
225 val |= chan_to_field(green, &fbi->fb.var.green);
226 val |= chan_to_field(blue, &fbi->fb.var.blue);
227
228 pal[regno] = val;
229 ret = 0;
230 }
231 break;
232
233 case FB_VISUAL_STATIC_PSEUDOCOLOR:
234 case FB_VISUAL_PSEUDOCOLOR:
235 ret = pxafb_setpalettereg(regno, red, green, blue, trans, info);
236 break;
237 }
238
239 return ret;
240}
241
242/* calculate pixel depth, transparency bit included, >=16bpp formats _only_ */
243static inline int var_to_depth(struct fb_var_screeninfo *var)
244{
245 return var->red.length + var->green.length +
246 var->blue.length + var->transp.length;
247}
248
249/* calculate 4-bit BPP value for LCCR3 and OVLxC1 */
250static int pxafb_var_to_bpp(struct fb_var_screeninfo *var)
251{
252 int bpp = -EINVAL;
253
254 switch (var->bits_per_pixel) {
255 case 1: bpp = 0; break;
256 case 2: bpp = 1; break;
257 case 4: bpp = 2; break;
258 case 8: bpp = 3; break;
259 case 16: bpp = 4; break;
260 case 24:
261 switch (var_to_depth(var)) {
262 case 18: bpp = 6; break; /* 18-bits/pixel packed */
263 case 19: bpp = 8; break; /* 19-bits/pixel packed */
264 case 24: bpp = 9; break;
265 }
266 break;
267 case 32:
268 switch (var_to_depth(var)) {
269 case 18: bpp = 5; break; /* 18-bits/pixel unpacked */
270 case 19: bpp = 7; break; /* 19-bits/pixel unpacked */
271 case 25: bpp = 10; break;
272 }
273 break;
274 }
275 return bpp;
276}
277
278/*
279 * pxafb_var_to_lccr3():
280 * Convert a bits per pixel value to the correct bit pattern for LCCR3
281 *
282 * NOTE: for PXA27x with overlays support, the LCCR3_PDFOR_x bits have an
283 * implication of the acutal use of transparency bit, which we handle it
284 * here separatedly. See PXA27x Developer's Manual, Section <<7.4.6 Pixel
285 * Formats>> for the valid combination of PDFOR, PAL_FOR for various BPP.
286 *
287 * Transparency for palette pixel formats is not supported at the moment.
288 */
289static uint32_t pxafb_var_to_lccr3(struct fb_var_screeninfo *var)
290{
291 int bpp = pxafb_var_to_bpp(var);
292 uint32_t lccr3;
293
294 if (bpp < 0)
295 return 0;
296
297 lccr3 = LCCR3_BPP(bpp);
298
299 switch (var_to_depth(var)) {
300 case 16: lccr3 |= var->transp.length ? LCCR3_PDFOR_3 : 0; break;
301 case 18: lccr3 |= LCCR3_PDFOR_3; break;
302 case 24: lccr3 |= var->transp.length ? LCCR3_PDFOR_2 : LCCR3_PDFOR_3;
303 break;
304 case 19:
305 case 25: lccr3 |= LCCR3_PDFOR_0; break;
306 }
307 return lccr3;
308}
309
310#define SET_PIXFMT(v, r, g, b, t) \
311({ \
312 (v)->transp.offset = (t) ? (r) + (g) + (b) : 0; \
313 (v)->transp.length = (t) ? (t) : 0; \
314 (v)->blue.length = (b); (v)->blue.offset = 0; \
315 (v)->green.length = (g); (v)->green.offset = (b); \
316 (v)->red.length = (r); (v)->red.offset = (b) + (g); \
317})
318
319/* set the RGBT bitfields of fb_var_screeninf according to
320 * var->bits_per_pixel and given depth
321 */
322static void pxafb_set_pixfmt(struct fb_var_screeninfo *var, int depth)
323{
324 if (depth == 0)
325 depth = var->bits_per_pixel;
326
327 if (var->bits_per_pixel < 16) {
328 /* indexed pixel formats */
329 var->red.offset = 0; var->red.length = 8;
330 var->green.offset = 0; var->green.length = 8;
331 var->blue.offset = 0; var->blue.length = 8;
332 var->transp.offset = 0; var->transp.length = 8;
333 }
334
335 switch (depth) {
336 case 16: var->transp.length ?
337 SET_PIXFMT(var, 5, 5, 5, 1) : /* RGBT555 */
338 SET_PIXFMT(var, 5, 6, 5, 0); break; /* RGB565 */
339 case 18: SET_PIXFMT(var, 6, 6, 6, 0); break; /* RGB666 */
340 case 19: SET_PIXFMT(var, 6, 6, 6, 1); break; /* RGBT666 */
341 case 24: var->transp.length ?
342 SET_PIXFMT(var, 8, 8, 7, 1) : /* RGBT887 */
343 SET_PIXFMT(var, 8, 8, 8, 0); break; /* RGB888 */
344 case 25: SET_PIXFMT(var, 8, 8, 8, 1); break; /* RGBT888 */
345 }
346}
347
348#ifdef CONFIG_CPU_FREQ
349/*
350 * pxafb_display_dma_period()
351 * Calculate the minimum period (in picoseconds) between two DMA
352 * requests for the LCD controller. If we hit this, it means we're
353 * doing nothing but LCD DMA.
354 */
355static unsigned int pxafb_display_dma_period(struct fb_var_screeninfo *var)
356{
357 /*
358 * Period = pixclock * bits_per_byte * bytes_per_transfer
359 * / memory_bits_per_pixel;
360 */
361 return var->pixclock * 8 * 16 / var->bits_per_pixel;
362}
363#endif
364
365/*
366 * Select the smallest mode that allows the desired resolution to be
367 * displayed. If desired parameters can be rounded up.
368 */
369static struct pxafb_mode_info *pxafb_getmode(struct pxafb_mach_info *mach,
370 struct fb_var_screeninfo *var)
371{
372 struct pxafb_mode_info *mode = NULL;
373 struct pxafb_mode_info *modelist = mach->modes;
374 unsigned int best_x = 0xffffffff, best_y = 0xffffffff;
375 unsigned int i;
376
377 for (i = 0; i < mach->num_modes; i++) {
378 if (modelist[i].xres >= var->xres &&
379 modelist[i].yres >= var->yres &&
380 modelist[i].xres < best_x &&
381 modelist[i].yres < best_y &&
382 modelist[i].bpp >= var->bits_per_pixel) {
383 best_x = modelist[i].xres;
384 best_y = modelist[i].yres;
385 mode = &modelist[i];
386 }
387 }
388
389 return mode;
390}
391
392static void pxafb_setmode(struct fb_var_screeninfo *var,
393 struct pxafb_mode_info *mode)
394{
395 var->xres = mode->xres;
396 var->yres = mode->yres;
397 var->bits_per_pixel = mode->bpp;
398 var->pixclock = mode->pixclock;
399 var->hsync_len = mode->hsync_len;
400 var->left_margin = mode->left_margin;
401 var->right_margin = mode->right_margin;
402 var->vsync_len = mode->vsync_len;
403 var->upper_margin = mode->upper_margin;
404 var->lower_margin = mode->lower_margin;
405 var->sync = mode->sync;
406 var->grayscale = mode->cmap_greyscale;
407 var->transp.length = mode->transparency;
408
409 /* set the initial RGBA bitfields */
410 pxafb_set_pixfmt(var, mode->depth);
411}
412
413static int pxafb_adjust_timing(struct pxafb_info *fbi,
414 struct fb_var_screeninfo *var)
415{
416 int line_length;
417
418 var->xres = max_t(int, var->xres, MIN_XRES);
419 var->yres = max_t(int, var->yres, MIN_YRES);
420
421 if (!(fbi->lccr0 & LCCR0_LCDT)) {
422 var->hsync_len = clamp(var->hsync_len, 1, 64);
423 var->vsync_len = clamp(var->vsync_len, 1, 64);
424 var->left_margin = clamp(var->left_margin, 1, 255);
425 var->right_margin = clamp(var->right_margin, 1, 255);
426 var->upper_margin = clamp(var->upper_margin, 1, 255);
427 var->lower_margin = clamp(var->lower_margin, 1, 255);
428 }
429
430 /* make sure each line is aligned on word boundary */
431 line_length = var->xres * var->bits_per_pixel / 8;
432 line_length = ALIGN(line_length, 4);
433 var->xres = line_length * 8 / var->bits_per_pixel;
434
435 /* we don't support xpan, force xres_virtual to be equal to xres */
436 var->xres_virtual = var->xres;
437
438 if (var->accel_flags & FB_ACCELF_TEXT)
439 var->yres_virtual = fbi->fb.fix.smem_len / line_length;
440 else
441 var->yres_virtual = max(var->yres_virtual, var->yres);
442
443 /* check for limits */
444 if (var->xres > MAX_XRES || var->yres > MAX_YRES)
445 return -EINVAL;
446
447 if (var->yres > var->yres_virtual)
448 return -EINVAL;
449
450 return 0;
451}
452
453/*
454 * pxafb_check_var():
455 * Get the video params out of 'var'. If a value doesn't fit, round it up,
456 * if it's too big, return -EINVAL.
457 *
458 * Round up in the following order: bits_per_pixel, xres,
459 * yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale,
460 * bitfields, horizontal timing, vertical timing.
461 */
462static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
463{
464 struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
465 struct pxafb_mach_info *inf = fbi->inf;
466 int err;
467
468 if (inf->fixed_modes) {
469 struct pxafb_mode_info *mode;
470
471 mode = pxafb_getmode(inf, var);
472 if (!mode)
473 return -EINVAL;
474 pxafb_setmode(var, mode);
475 }
476
477 /* do a test conversion to BPP fields to check the color formats */
478 err = pxafb_var_to_bpp(var);
479 if (err < 0)
480 return err;
481
482 pxafb_set_pixfmt(var, var_to_depth(var));
483
484 err = pxafb_adjust_timing(fbi, var);
485 if (err)
486 return err;
487
488#ifdef CONFIG_CPU_FREQ
489 pr_debug("pxafb: dma period = %d ps\n",
490 pxafb_display_dma_period(var));
491#endif
492
493 return 0;
494}
495
496/*
497 * pxafb_set_par():
498 * Set the user defined part of the display for the specified console
499 */
500static int pxafb_set_par(struct fb_info *info)
501{
502 struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
503 struct fb_var_screeninfo *var = &info->var;
504
505 if (var->bits_per_pixel >= 16)
506 fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR;
507 else if (!fbi->cmap_static)
508 fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
509 else {
510 /*
511 * Some people have weird ideas about wanting static
512 * pseudocolor maps. I suspect their user space
513 * applications are broken.
514 */
515 fbi->fb.fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
516 }
517
518 fbi->fb.fix.line_length = var->xres_virtual *
519 var->bits_per_pixel / 8;
520 if (var->bits_per_pixel >= 16)
521 fbi->palette_size = 0;
522 else
523 fbi->palette_size = var->bits_per_pixel == 1 ?
524 4 : 1 << var->bits_per_pixel;
525
526 fbi->palette_cpu = (u16 *)&fbi->dma_buff->palette[0];
527
528 if (fbi->fb.var.bits_per_pixel >= 16)
529 fb_dealloc_cmap(&fbi->fb.cmap);
530 else
531 fb_alloc_cmap(&fbi->fb.cmap, 1<<fbi->fb.var.bits_per_pixel, 0);
532
533 pxafb_activate_var(var, fbi);
534
535 return 0;
536}
537
538static int pxafb_pan_display(struct fb_var_screeninfo *var,
539 struct fb_info *info)
540{
541 struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
542 struct fb_var_screeninfo newvar;
543 int dma = DMA_MAX + DMA_BASE;
544
545 if (fbi->state != C_ENABLE)
546 return 0;
547
548 /* Only take .xoffset, .yoffset and .vmode & FB_VMODE_YWRAP from what
549 * was passed in and copy the rest from the old screeninfo.
550 */
551 memcpy(&newvar, &fbi->fb.var, sizeof(newvar));
552 newvar.xoffset = var->xoffset;
553 newvar.yoffset = var->yoffset;
554 newvar.vmode &= ~FB_VMODE_YWRAP;
555 newvar.vmode |= var->vmode & FB_VMODE_YWRAP;
556
557 setup_base_frame(fbi, &newvar, 1);
558
559 if (fbi->lccr0 & LCCR0_SDS)
560 lcd_writel(fbi, FBR1, fbi->fdadr[dma + 1] | 0x1);
561
562 lcd_writel(fbi, FBR0, fbi->fdadr[dma] | 0x1);
563 return 0;
564}
565
566/*
567 * pxafb_blank():
568 * Blank the display by setting all palette values to zero. Note, the
569 * 16 bpp mode does not really use the palette, so this will not
570 * blank the display in all modes.
571 */
572static int pxafb_blank(int blank, struct fb_info *info)
573{
574 struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
575 int i;
576
577 switch (blank) {
578 case FB_BLANK_POWERDOWN:
579 case FB_BLANK_VSYNC_SUSPEND:
580 case FB_BLANK_HSYNC_SUSPEND:
581 case FB_BLANK_NORMAL:
582 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
583 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
584 for (i = 0; i < fbi->palette_size; i++)
585 pxafb_setpalettereg(i, 0, 0, 0, 0, info);
586
587 pxafb_schedule_work(fbi, C_DISABLE);
588 /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */
589 break;
590
591 case FB_BLANK_UNBLANK:
592 /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */
593 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
594 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
595 fb_set_cmap(&fbi->fb.cmap, info);
596 pxafb_schedule_work(fbi, C_ENABLE);
597 }
598 return 0;
599}
600
601static const struct fb_ops pxafb_ops = {
602 .owner = THIS_MODULE,
603 FB_DEFAULT_IOMEM_OPS,
604 .fb_check_var = pxafb_check_var,
605 .fb_set_par = pxafb_set_par,
606 .fb_pan_display = pxafb_pan_display,
607 .fb_setcolreg = pxafb_setcolreg,
608 .fb_blank = pxafb_blank,
609};
610
611#ifdef CONFIG_FB_PXA_OVERLAY
612static void overlay1fb_setup(struct pxafb_layer *ofb)
613{
614 int size = ofb->fb.fix.line_length * ofb->fb.var.yres_virtual;
615 unsigned long start = ofb->video_mem_phys;
616 setup_frame_dma(ofb->fbi, DMA_OV1, PAL_NONE, start, size);
617}
618
619/* Depending on the enable status of overlay1/2, the DMA should be
620 * updated from FDADRx (when disabled) or FBRx (when enabled).
621 */
622static void overlay1fb_enable(struct pxafb_layer *ofb)
623{
624 int enabled = lcd_readl(ofb->fbi, OVL1C1) & OVLxC1_OEN;
625 uint32_t fdadr1 = ofb->fbi->fdadr[DMA_OV1] | (enabled ? 0x1 : 0);
626
627 lcd_writel(ofb->fbi, enabled ? FBR1 : FDADR1, fdadr1);
628 lcd_writel(ofb->fbi, OVL1C2, ofb->control[1]);
629 lcd_writel(ofb->fbi, OVL1C1, ofb->control[0] | OVLxC1_OEN);
630}
631
632static void overlay1fb_disable(struct pxafb_layer *ofb)
633{
634 uint32_t lccr5;
635
636 if (!(lcd_readl(ofb->fbi, OVL1C1) & OVLxC1_OEN))
637 return;
638
639 lccr5 = lcd_readl(ofb->fbi, LCCR5);
640
641 lcd_writel(ofb->fbi, OVL1C1, ofb->control[0] & ~OVLxC1_OEN);
642
643 lcd_writel(ofb->fbi, LCSR1, LCSR1_BS(1));
644 lcd_writel(ofb->fbi, LCCR5, lccr5 & ~LCSR1_BS(1));
645 lcd_writel(ofb->fbi, FBR1, ofb->fbi->fdadr[DMA_OV1] | 0x3);
646
647 if (wait_for_completion_timeout(&ofb->branch_done, 1 * HZ) == 0)
648 pr_warn("%s: timeout disabling overlay1\n", __func__);
649
650 lcd_writel(ofb->fbi, LCCR5, lccr5);
651}
652
653static void overlay2fb_setup(struct pxafb_layer *ofb)
654{
655 int size, div = 1, pfor = NONSTD_TO_PFOR(ofb->fb.var.nonstd);
656 unsigned long start[3] = { ofb->video_mem_phys, 0, 0 };
657
658 if (pfor == OVERLAY_FORMAT_RGB || pfor == OVERLAY_FORMAT_YUV444_PACKED) {
659 size = ofb->fb.fix.line_length * ofb->fb.var.yres_virtual;
660 setup_frame_dma(ofb->fbi, DMA_OV2_Y, -1, start[0], size);
661 } else {
662 size = ofb->fb.var.xres_virtual * ofb->fb.var.yres_virtual;
663 switch (pfor) {
664 case OVERLAY_FORMAT_YUV444_PLANAR: div = 1; break;
665 case OVERLAY_FORMAT_YUV422_PLANAR: div = 2; break;
666 case OVERLAY_FORMAT_YUV420_PLANAR: div = 4; break;
667 }
668 start[1] = start[0] + size;
669 start[2] = start[1] + size / div;
670 setup_frame_dma(ofb->fbi, DMA_OV2_Y, -1, start[0], size);
671 setup_frame_dma(ofb->fbi, DMA_OV2_Cb, -1, start[1], size / div);
672 setup_frame_dma(ofb->fbi, DMA_OV2_Cr, -1, start[2], size / div);
673 }
674}
675
676static void overlay2fb_enable(struct pxafb_layer *ofb)
677{
678 int pfor = NONSTD_TO_PFOR(ofb->fb.var.nonstd);
679 int enabled = lcd_readl(ofb->fbi, OVL2C1) & OVLxC1_OEN;
680 uint32_t fdadr2 = ofb->fbi->fdadr[DMA_OV2_Y] | (enabled ? 0x1 : 0);
681 uint32_t fdadr3 = ofb->fbi->fdadr[DMA_OV2_Cb] | (enabled ? 0x1 : 0);
682 uint32_t fdadr4 = ofb->fbi->fdadr[DMA_OV2_Cr] | (enabled ? 0x1 : 0);
683
684 if (pfor == OVERLAY_FORMAT_RGB || pfor == OVERLAY_FORMAT_YUV444_PACKED)
685 lcd_writel(ofb->fbi, enabled ? FBR2 : FDADR2, fdadr2);
686 else {
687 lcd_writel(ofb->fbi, enabled ? FBR2 : FDADR2, fdadr2);
688 lcd_writel(ofb->fbi, enabled ? FBR3 : FDADR3, fdadr3);
689 lcd_writel(ofb->fbi, enabled ? FBR4 : FDADR4, fdadr4);
690 }
691 lcd_writel(ofb->fbi, OVL2C2, ofb->control[1]);
692 lcd_writel(ofb->fbi, OVL2C1, ofb->control[0] | OVLxC1_OEN);
693}
694
695static void overlay2fb_disable(struct pxafb_layer *ofb)
696{
697 uint32_t lccr5;
698
699 if (!(lcd_readl(ofb->fbi, OVL2C1) & OVLxC1_OEN))
700 return;
701
702 lccr5 = lcd_readl(ofb->fbi, LCCR5);
703
704 lcd_writel(ofb->fbi, OVL2C1, ofb->control[0] & ~OVLxC1_OEN);
705
706 lcd_writel(ofb->fbi, LCSR1, LCSR1_BS(2));
707 lcd_writel(ofb->fbi, LCCR5, lccr5 & ~LCSR1_BS(2));
708 lcd_writel(ofb->fbi, FBR2, ofb->fbi->fdadr[DMA_OV2_Y] | 0x3);
709 lcd_writel(ofb->fbi, FBR3, ofb->fbi->fdadr[DMA_OV2_Cb] | 0x3);
710 lcd_writel(ofb->fbi, FBR4, ofb->fbi->fdadr[DMA_OV2_Cr] | 0x3);
711
712 if (wait_for_completion_timeout(&ofb->branch_done, 1 * HZ) == 0)
713 pr_warn("%s: timeout disabling overlay2\n", __func__);
714}
715
716static struct pxafb_layer_ops ofb_ops[] = {
717 [0] = {
718 .enable = overlay1fb_enable,
719 .disable = overlay1fb_disable,
720 .setup = overlay1fb_setup,
721 },
722 [1] = {
723 .enable = overlay2fb_enable,
724 .disable = overlay2fb_disable,
725 .setup = overlay2fb_setup,
726 },
727};
728
729static int overlayfb_open(struct fb_info *info, int user)
730{
731 struct pxafb_layer *ofb = container_of(info, struct pxafb_layer, fb);
732
733 /* no support for framebuffer console on overlay */
734 if (user == 0)
735 return -ENODEV;
736
737 if (ofb->usage++ == 0) {
738 /* unblank the base framebuffer */
739 console_lock();
740 fb_blank(&ofb->fbi->fb, FB_BLANK_UNBLANK);
741 console_unlock();
742 }
743
744 return 0;
745}
746
747static int overlayfb_release(struct fb_info *info, int user)
748{
749 struct pxafb_layer *ofb = container_of(info, struct pxafb_layer, fb);
750
751 if (ofb->usage == 1) {
752 ofb->ops->disable(ofb);
753 ofb->fb.var.height = -1;
754 ofb->fb.var.width = -1;
755 ofb->fb.var.xres = ofb->fb.var.xres_virtual = 0;
756 ofb->fb.var.yres = ofb->fb.var.yres_virtual = 0;
757
758 ofb->usage--;
759 }
760 return 0;
761}
762
763static int overlayfb_check_var(struct fb_var_screeninfo *var,
764 struct fb_info *info)
765{
766 struct pxafb_layer *ofb = container_of(info, struct pxafb_layer, fb);
767 struct fb_var_screeninfo *base_var = &ofb->fbi->fb.var;
768 int xpos, ypos, pfor, bpp;
769
770 xpos = NONSTD_TO_XPOS(var->nonstd);
771 ypos = NONSTD_TO_YPOS(var->nonstd);
772 pfor = NONSTD_TO_PFOR(var->nonstd);
773
774 bpp = pxafb_var_to_bpp(var);
775 if (bpp < 0)
776 return -EINVAL;
777
778 /* no support for YUV format on overlay1 */
779 if (ofb->id == OVERLAY1 && pfor != 0)
780 return -EINVAL;
781
782 /* for YUV packed formats, bpp = 'minimum bpp of YUV components' */
783 switch (pfor) {
784 case OVERLAY_FORMAT_RGB:
785 bpp = pxafb_var_to_bpp(var);
786 if (bpp < 0)
787 return -EINVAL;
788
789 pxafb_set_pixfmt(var, var_to_depth(var));
790 break;
791 case OVERLAY_FORMAT_YUV444_PACKED: bpp = 24; break;
792 case OVERLAY_FORMAT_YUV444_PLANAR: bpp = 8; break;
793 case OVERLAY_FORMAT_YUV422_PLANAR: bpp = 4; break;
794 case OVERLAY_FORMAT_YUV420_PLANAR: bpp = 2; break;
795 default:
796 return -EINVAL;
797 }
798
799 /* each line must start at a 32-bit word boundary */
800 if ((xpos * bpp) % 32)
801 return -EINVAL;
802
803 /* xres must align on 32-bit word boundary */
804 var->xres = roundup(var->xres * bpp, 32) / bpp;
805
806 if ((xpos + var->xres > base_var->xres) ||
807 (ypos + var->yres > base_var->yres))
808 return -EINVAL;
809
810 var->xres_virtual = var->xres;
811 var->yres_virtual = max(var->yres, var->yres_virtual);
812 return 0;
813}
814
815static int overlayfb_check_video_memory(struct pxafb_layer *ofb)
816{
817 struct fb_var_screeninfo *var = &ofb->fb.var;
818 int pfor = NONSTD_TO_PFOR(var->nonstd);
819 int size, bpp = 0;
820
821 switch (pfor) {
822 case OVERLAY_FORMAT_RGB: bpp = var->bits_per_pixel; break;
823 case OVERLAY_FORMAT_YUV444_PACKED: bpp = 24; break;
824 case OVERLAY_FORMAT_YUV444_PLANAR: bpp = 24; break;
825 case OVERLAY_FORMAT_YUV422_PLANAR: bpp = 16; break;
826 case OVERLAY_FORMAT_YUV420_PLANAR: bpp = 12; break;
827 }
828
829 ofb->fb.fix.line_length = var->xres_virtual * bpp / 8;
830
831 size = PAGE_ALIGN(ofb->fb.fix.line_length * var->yres_virtual);
832
833 if (ofb->video_mem) {
834 if (ofb->video_mem_size >= size)
835 return 0;
836 }
837 return -EINVAL;
838}
839
840static int overlayfb_set_par(struct fb_info *info)
841{
842 struct pxafb_layer *ofb = container_of(info, struct pxafb_layer, fb);
843 struct fb_var_screeninfo *var = &info->var;
844 int xpos, ypos, pfor, bpp, ret;
845
846 ret = overlayfb_check_video_memory(ofb);
847 if (ret)
848 return ret;
849
850 bpp = pxafb_var_to_bpp(var);
851 xpos = NONSTD_TO_XPOS(var->nonstd);
852 ypos = NONSTD_TO_YPOS(var->nonstd);
853 pfor = NONSTD_TO_PFOR(var->nonstd);
854
855 ofb->control[0] = OVLxC1_PPL(var->xres) | OVLxC1_LPO(var->yres) |
856 OVLxC1_BPP(bpp);
857 ofb->control[1] = OVLxC2_XPOS(xpos) | OVLxC2_YPOS(ypos);
858
859 if (ofb->id == OVERLAY2)
860 ofb->control[1] |= OVL2C2_PFOR(pfor);
861
862 ofb->ops->setup(ofb);
863 ofb->ops->enable(ofb);
864 return 0;
865}
866
867static const struct fb_ops overlay_fb_ops = {
868 .owner = THIS_MODULE,
869 .fb_open = overlayfb_open,
870 .fb_release = overlayfb_release,
871 .fb_check_var = overlayfb_check_var,
872 .fb_set_par = overlayfb_set_par,
873};
874
875static void init_pxafb_overlay(struct pxafb_info *fbi, struct pxafb_layer *ofb,
876 int id)
877{
878 sprintf(ofb->fb.fix.id, "overlay%d", id + 1);
879
880 ofb->fb.fix.type = FB_TYPE_PACKED_PIXELS;
881 ofb->fb.fix.xpanstep = 0;
882 ofb->fb.fix.ypanstep = 1;
883
884 ofb->fb.var.activate = FB_ACTIVATE_NOW;
885 ofb->fb.var.height = -1;
886 ofb->fb.var.width = -1;
887 ofb->fb.var.vmode = FB_VMODE_NONINTERLACED;
888
889 ofb->fb.fbops = &overlay_fb_ops;
890 ofb->fb.node = -1;
891 ofb->fb.pseudo_palette = NULL;
892
893 ofb->id = id;
894 ofb->ops = &ofb_ops[id];
895 ofb->usage = 0;
896 ofb->fbi = fbi;
897 init_completion(&ofb->branch_done);
898}
899
900static inline int pxafb_overlay_supported(void)
901{
902 if (cpu_is_pxa27x() || cpu_is_pxa3xx())
903 return 1;
904
905 return 0;
906}
907
908static int pxafb_overlay_map_video_memory(struct pxafb_info *pxafb,
909 struct pxafb_layer *ofb)
910{
911 /* We assume that user will use at most video_mem_size for overlay fb,
912 * anyway, it's useless to use 16bpp main plane and 24bpp overlay
913 */
914 ofb->video_mem = alloc_pages_exact(PAGE_ALIGN(pxafb->video_mem_size),
915 GFP_KERNEL | __GFP_ZERO);
916 if (ofb->video_mem == NULL)
917 return -ENOMEM;
918
919 ofb->video_mem_phys = virt_to_phys(ofb->video_mem);
920 ofb->video_mem_size = PAGE_ALIGN(pxafb->video_mem_size);
921
922 mutex_lock(&ofb->fb.mm_lock);
923 ofb->fb.fix.smem_start = ofb->video_mem_phys;
924 ofb->fb.fix.smem_len = pxafb->video_mem_size;
925 mutex_unlock(&ofb->fb.mm_lock);
926
927 ofb->fb.screen_base = ofb->video_mem;
928
929 return 0;
930}
931
932static void pxafb_overlay_init(struct pxafb_info *fbi)
933{
934 int i, ret;
935
936 if (!pxafb_overlay_supported())
937 return;
938
939 for (i = 0; i < 2; i++) {
940 struct pxafb_layer *ofb = &fbi->overlay[i];
941 init_pxafb_overlay(fbi, ofb, i);
942 ret = register_framebuffer(&ofb->fb);
943 if (ret) {
944 dev_err(fbi->dev, "failed to register overlay %d\n", i);
945 continue;
946 }
947 ret = pxafb_overlay_map_video_memory(fbi, ofb);
948 if (ret) {
949 dev_err(fbi->dev,
950 "failed to map video memory for overlay %d\n",
951 i);
952 unregister_framebuffer(&ofb->fb);
953 continue;
954 }
955 ofb->registered = 1;
956 }
957
958 /* mask all IU/BS/EOF/SOF interrupts */
959 lcd_writel(fbi, LCCR5, ~0);
960
961 pr_info("PXA Overlay driver loaded successfully!\n");
962}
963
964static void pxafb_overlay_exit(struct pxafb_info *fbi)
965{
966 int i;
967
968 if (!pxafb_overlay_supported())
969 return;
970
971 for (i = 0; i < 2; i++) {
972 struct pxafb_layer *ofb = &fbi->overlay[i];
973 if (ofb->registered) {
974 if (ofb->video_mem)
975 free_pages_exact(ofb->video_mem,
976 ofb->video_mem_size);
977 unregister_framebuffer(&ofb->fb);
978 }
979 }
980}
981#else
982static inline void pxafb_overlay_init(struct pxafb_info *fbi) {}
983static inline void pxafb_overlay_exit(struct pxafb_info *fbi) {}
984#endif /* CONFIG_FB_PXA_OVERLAY */
985
986/*
987 * Calculate the PCD value from the clock rate (in picoseconds).
988 * We take account of the PPCR clock setting.
989 * From PXA Developer's Manual:
990 *
991 * PixelClock = LCLK
992 * -------------
993 * 2 ( PCD + 1 )
994 *
995 * PCD = LCLK
996 * ------------- - 1
997 * 2(PixelClock)
998 *
999 * Where:
1000 * LCLK = LCD/Memory Clock
1001 * PCD = LCCR3[7:0]
1002 *
1003 * PixelClock here is in Hz while the pixclock argument given is the
1004 * period in picoseconds. Hence PixelClock = 1 / ( pixclock * 10^-12 )
1005 *
1006 * The function get_lclk_frequency_10khz returns LCLK in units of
1007 * 10khz. Calling the result of this function lclk gives us the
1008 * following
1009 *
1010 * PCD = (lclk * 10^4 ) * ( pixclock * 10^-12 )
1011 * -------------------------------------- - 1
1012 * 2
1013 *
1014 * Factoring the 10^4 and 10^-12 out gives 10^-8 == 1 / 100000000 as used below.
1015 */
1016static inline unsigned int get_pcd(struct pxafb_info *fbi,
1017 unsigned int pixclock)
1018{
1019 unsigned long long pcd;
1020
1021 /* FIXME: Need to take into account Double Pixel Clock mode
1022 * (DPC) bit? or perhaps set it based on the various clock
1023 * speeds */
1024 pcd = (unsigned long long)(clk_get_rate(fbi->clk) / 10000);
1025 pcd *= pixclock;
1026 do_div(pcd, 100000000 * 2);
1027 /* no need for this, since we should subtract 1 anyway. they cancel */
1028 /* pcd += 1; */ /* make up for integer math truncations */
1029 return (unsigned int)pcd;
1030}
1031
1032/*
1033 * Some touchscreens need hsync information from the video driver to
1034 * function correctly. We export it here. Note that 'hsync_time' is
1035 * the *reciprocal* of the hsync period in seconds.
1036 */
1037static inline void set_hsync_time(struct pxafb_info *fbi, unsigned int pcd)
1038{
1039 unsigned long htime;
1040
1041 if ((pcd == 0) || (fbi->fb.var.hsync_len == 0)) {
1042 fbi->hsync_time = 0;
1043 return;
1044 }
1045
1046 htime = clk_get_rate(fbi->clk) / (pcd * fbi->fb.var.hsync_len);
1047
1048 fbi->hsync_time = htime;
1049}
1050
1051static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal,
1052 unsigned long start, size_t size)
1053{
1054 struct pxafb_dma_descriptor *dma_desc, *pal_desc;
1055 unsigned int dma_desc_off, pal_desc_off;
1056
1057 if (dma < 0 || dma >= DMA_MAX * 2)
1058 return -EINVAL;
1059
1060 dma_desc = &fbi->dma_buff->dma_desc[dma];
1061 dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[dma]);
1062
1063 dma_desc->fsadr = start;
1064 dma_desc->fidr = 0;
1065 dma_desc->ldcmd = size;
1066
1067 if (pal < 0 || pal >= PAL_MAX * 2) {
1068 dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
1069 fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
1070 } else {
1071 pal_desc = &fbi->dma_buff->pal_desc[pal];
1072 pal_desc_off = offsetof(struct pxafb_dma_buff, pal_desc[pal]);
1073
1074 pal_desc->fsadr = fbi->dma_buff_phys + pal * PALETTE_SIZE;
1075 pal_desc->fidr = 0;
1076
1077 if ((fbi->lccr4 & LCCR4_PAL_FOR_MASK) == LCCR4_PAL_FOR_0)
1078 pal_desc->ldcmd = fbi->palette_size * sizeof(u16);
1079 else
1080 pal_desc->ldcmd = fbi->palette_size * sizeof(u32);
1081
1082 pal_desc->ldcmd |= LDCMD_PAL;
1083
1084 /* flip back and forth between palette and frame buffer */
1085 pal_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
1086 dma_desc->fdadr = fbi->dma_buff_phys + pal_desc_off;
1087 fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
1088 }
1089
1090 return 0;
1091}
1092
1093static void setup_base_frame(struct pxafb_info *fbi,
1094 struct fb_var_screeninfo *var,
1095 int branch)
1096{
1097 struct fb_fix_screeninfo *fix = &fbi->fb.fix;
1098 int nbytes, dma, pal, bpp = var->bits_per_pixel;
1099 unsigned long offset;
1100
1101 dma = DMA_BASE + (branch ? DMA_MAX : 0);
1102 pal = (bpp >= 16) ? PAL_NONE : PAL_BASE + (branch ? PAL_MAX : 0);
1103
1104 nbytes = fix->line_length * var->yres;
1105 offset = fix->line_length * var->yoffset + fbi->video_mem_phys;
1106
1107 if (fbi->lccr0 & LCCR0_SDS) {
1108 nbytes = nbytes / 2;
1109 setup_frame_dma(fbi, dma + 1, PAL_NONE, offset + nbytes, nbytes);
1110 }
1111
1112 setup_frame_dma(fbi, dma, pal, offset, nbytes);
1113}
1114
1115#ifdef CONFIG_FB_PXA_SMARTPANEL
1116static int setup_smart_dma(struct pxafb_info *fbi)
1117{
1118 struct pxafb_dma_descriptor *dma_desc;
1119 unsigned long dma_desc_off, cmd_buff_off;
1120
1121 dma_desc = &fbi->dma_buff->dma_desc[DMA_CMD];
1122 dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[DMA_CMD]);
1123 cmd_buff_off = offsetof(struct pxafb_dma_buff, cmd_buff);
1124
1125 dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
1126 dma_desc->fsadr = fbi->dma_buff_phys + cmd_buff_off;
1127 dma_desc->fidr = 0;
1128 dma_desc->ldcmd = fbi->n_smart_cmds * sizeof(uint16_t);
1129
1130 fbi->fdadr[DMA_CMD] = dma_desc->fdadr;
1131 return 0;
1132}
1133
1134int pxafb_smart_flush(struct fb_info *info)
1135{
1136 struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
1137 uint32_t prsr;
1138 int ret = 0;
1139
1140 /* disable controller until all registers are set up */
1141 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
1142
1143 /* 1. make it an even number of commands to align on 32-bit boundary
1144 * 2. add the interrupt command to the end of the chain so we can
1145 * keep track of the end of the transfer
1146 */
1147
1148 while (fbi->n_smart_cmds & 1)
1149 fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_NOOP;
1150
1151 fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_INTERRUPT;
1152 fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_WAIT_FOR_VSYNC;
1153 setup_smart_dma(fbi);
1154
1155 /* continue to execute next command */
1156 prsr = lcd_readl(fbi, PRSR) | PRSR_ST_OK | PRSR_CON_NT;
1157 lcd_writel(fbi, PRSR, prsr);
1158
1159 /* stop the processor in case it executed "wait for sync" cmd */
1160 lcd_writel(fbi, CMDCR, 0x0001);
1161
1162 /* don't send interrupts for fifo underruns on channel 6 */
1163 lcd_writel(fbi, LCCR5, LCCR5_IUM(6));
1164
1165 lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
1166 lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
1167 lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
1168 lcd_writel(fbi, LCCR4, fbi->reg_lccr4);
1169 lcd_writel(fbi, FDADR0, fbi->fdadr[0]);
1170 lcd_writel(fbi, FDADR6, fbi->fdadr[6]);
1171
1172 /* begin sending */
1173 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB);
1174
1175 if (wait_for_completion_timeout(&fbi->command_done, HZ/2) == 0) {
1176 pr_warn("%s: timeout waiting for command done\n", __func__);
1177 ret = -ETIMEDOUT;
1178 }
1179
1180 /* quick disable */
1181 prsr = lcd_readl(fbi, PRSR) & ~(PRSR_ST_OK | PRSR_CON_NT);
1182 lcd_writel(fbi, PRSR, prsr);
1183 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
1184 lcd_writel(fbi, FDADR6, 0);
1185 fbi->n_smart_cmds = 0;
1186 return ret;
1187}
1188
1189int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int n_cmds)
1190{
1191 int i;
1192 struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
1193
1194 for (i = 0; i < n_cmds; i++, cmds++) {
1195 /* if it is a software delay, flush and delay */
1196 if ((*cmds & 0xff00) == SMART_CMD_DELAY) {
1197 pxafb_smart_flush(info);
1198 mdelay(*cmds & 0xff);
1199 continue;
1200 }
1201
1202 /* leave 2 commands for INTERRUPT and WAIT_FOR_SYNC */
1203 if (fbi->n_smart_cmds == CMD_BUFF_SIZE - 8)
1204 pxafb_smart_flush(info);
1205
1206 fbi->smart_cmds[fbi->n_smart_cmds++] = *cmds;
1207 }
1208
1209 return 0;
1210}
1211
1212static unsigned int __smart_timing(unsigned time_ns, unsigned long lcd_clk)
1213{
1214 unsigned int t = (time_ns * (lcd_clk / 1000000) / 1000);
1215 return (t == 0) ? 1 : t;
1216}
1217
1218static void setup_smart_timing(struct pxafb_info *fbi,
1219 struct fb_var_screeninfo *var)
1220{
1221 struct pxafb_mach_info *inf = fbi->inf;
1222 struct pxafb_mode_info *mode = &inf->modes[0];
1223 unsigned long lclk = clk_get_rate(fbi->clk);
1224 unsigned t1, t2, t3, t4;
1225
1226 t1 = max(mode->a0csrd_set_hld, mode->a0cswr_set_hld);
1227 t2 = max(mode->rd_pulse_width, mode->wr_pulse_width);
1228 t3 = mode->op_hold_time;
1229 t4 = mode->cmd_inh_time;
1230
1231 fbi->reg_lccr1 =
1232 LCCR1_DisWdth(var->xres) |
1233 LCCR1_BegLnDel(__smart_timing(t1, lclk)) |
1234 LCCR1_EndLnDel(__smart_timing(t2, lclk)) |
1235 LCCR1_HorSnchWdth(__smart_timing(t3, lclk));
1236
1237 fbi->reg_lccr2 = LCCR2_DisHght(var->yres);
1238 fbi->reg_lccr3 = fbi->lccr3 | LCCR3_PixClkDiv(__smart_timing(t4, lclk));
1239 fbi->reg_lccr3 |= (var->sync & FB_SYNC_HOR_HIGH_ACT) ? LCCR3_HSP : 0;
1240 fbi->reg_lccr3 |= (var->sync & FB_SYNC_VERT_HIGH_ACT) ? LCCR3_VSP : 0;
1241
1242 /* FIXME: make this configurable */
1243 fbi->reg_cmdcr = 1;
1244}
1245
1246static int pxafb_smart_thread(void *arg)
1247{
1248 struct pxafb_info *fbi = arg;
1249 struct pxafb_mach_info *inf = fbi->inf;
1250
1251 if (!inf->smart_update) {
1252 pr_err("%s: not properly initialized, thread terminated\n",
1253 __func__);
1254 return -EINVAL;
1255 }
1256
1257 pr_debug("%s(): task starting\n", __func__);
1258
1259 set_freezable();
1260 while (!kthread_should_stop()) {
1261
1262 if (try_to_freeze())
1263 continue;
1264
1265 mutex_lock(&fbi->ctrlr_lock);
1266
1267 if (fbi->state == C_ENABLE) {
1268 inf->smart_update(&fbi->fb);
1269 complete(&fbi->refresh_done);
1270 }
1271
1272 mutex_unlock(&fbi->ctrlr_lock);
1273
1274 set_current_state(TASK_INTERRUPTIBLE);
1275 schedule_timeout(msecs_to_jiffies(30));
1276 }
1277
1278 pr_debug("%s(): task ending\n", __func__);
1279 return 0;
1280}
1281
1282static int pxafb_smart_init(struct pxafb_info *fbi)
1283{
1284 if (!(fbi->lccr0 & LCCR0_LCDT))
1285 return 0;
1286
1287 fbi->smart_cmds = (uint16_t *) fbi->dma_buff->cmd_buff;
1288 fbi->n_smart_cmds = 0;
1289
1290 init_completion(&fbi->command_done);
1291 init_completion(&fbi->refresh_done);
1292
1293 fbi->smart_thread = kthread_run(pxafb_smart_thread, fbi,
1294 "lcd_refresh");
1295 if (IS_ERR(fbi->smart_thread)) {
1296 pr_err("%s: unable to create kernel thread\n", __func__);
1297 return PTR_ERR(fbi->smart_thread);
1298 }
1299
1300 return 0;
1301}
1302#else
1303static inline int pxafb_smart_init(struct pxafb_info *fbi) { return 0; }
1304#endif /* CONFIG_FB_PXA_SMARTPANEL */
1305
1306static void setup_parallel_timing(struct pxafb_info *fbi,
1307 struct fb_var_screeninfo *var)
1308{
1309 unsigned int lines_per_panel, pcd = get_pcd(fbi, var->pixclock);
1310
1311 fbi->reg_lccr1 =
1312 LCCR1_DisWdth(var->xres) +
1313 LCCR1_HorSnchWdth(var->hsync_len) +
1314 LCCR1_BegLnDel(var->left_margin) +
1315 LCCR1_EndLnDel(var->right_margin);
1316
1317 /*
1318 * If we have a dual scan LCD, we need to halve
1319 * the YRES parameter.
1320 */
1321 lines_per_panel = var->yres;
1322 if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual)
1323 lines_per_panel /= 2;
1324
1325 fbi->reg_lccr2 =
1326 LCCR2_DisHght(lines_per_panel) +
1327 LCCR2_VrtSnchWdth(var->vsync_len) +
1328 LCCR2_BegFrmDel(var->upper_margin) +
1329 LCCR2_EndFrmDel(var->lower_margin);
1330
1331 fbi->reg_lccr3 = fbi->lccr3 |
1332 (var->sync & FB_SYNC_HOR_HIGH_ACT ?
1333 LCCR3_HorSnchH : LCCR3_HorSnchL) |
1334 (var->sync & FB_SYNC_VERT_HIGH_ACT ?
1335 LCCR3_VrtSnchH : LCCR3_VrtSnchL);
1336
1337 if (pcd) {
1338 fbi->reg_lccr3 |= LCCR3_PixClkDiv(pcd);
1339 set_hsync_time(fbi, pcd);
1340 }
1341}
1342
1343/*
1344 * pxafb_activate_var():
1345 * Configures LCD Controller based on entries in var parameter.
1346 * Settings are only written to the controller if changes were made.
1347 */
1348static int pxafb_activate_var(struct fb_var_screeninfo *var,
1349 struct pxafb_info *fbi)
1350{
1351 u_long flags;
1352
1353 /* Update shadow copy atomically */
1354 local_irq_save(flags);
1355
1356#ifdef CONFIG_FB_PXA_SMARTPANEL
1357 if (fbi->lccr0 & LCCR0_LCDT)
1358 setup_smart_timing(fbi, var);
1359 else
1360#endif
1361 setup_parallel_timing(fbi, var);
1362
1363 setup_base_frame(fbi, var, 0);
1364
1365 fbi->reg_lccr0 = fbi->lccr0 |
1366 (LCCR0_LDM | LCCR0_SFM | LCCR0_IUM | LCCR0_EFM |
1367 LCCR0_QDM | LCCR0_BM | LCCR0_OUM);
1368
1369 fbi->reg_lccr3 |= pxafb_var_to_lccr3(var);
1370
1371 fbi->reg_lccr4 = lcd_readl(fbi, LCCR4) & ~LCCR4_PAL_FOR_MASK;
1372 fbi->reg_lccr4 |= (fbi->lccr4 & LCCR4_PAL_FOR_MASK);
1373 local_irq_restore(flags);
1374
1375 /*
1376 * Only update the registers if the controller is enabled
1377 * and something has changed.
1378 */
1379 if ((lcd_readl(fbi, LCCR0) != fbi->reg_lccr0) ||
1380 (lcd_readl(fbi, LCCR1) != fbi->reg_lccr1) ||
1381 (lcd_readl(fbi, LCCR2) != fbi->reg_lccr2) ||
1382 (lcd_readl(fbi, LCCR3) != fbi->reg_lccr3) ||
1383 (lcd_readl(fbi, LCCR4) != fbi->reg_lccr4) ||
1384 (lcd_readl(fbi, FDADR0) != fbi->fdadr[0]) ||
1385 ((fbi->lccr0 & LCCR0_SDS) &&
1386 (lcd_readl(fbi, FDADR1) != fbi->fdadr[1])))
1387 pxafb_schedule_work(fbi, C_REENABLE);
1388
1389 return 0;
1390}
1391
1392/*
1393 * NOTE! The following functions are purely helpers for set_ctrlr_state.
1394 * Do not call them directly; set_ctrlr_state does the correct serialisation
1395 * to ensure that things happen in the right way 100% of time time.
1396 * -- rmk
1397 */
1398static inline void __pxafb_backlight_power(struct pxafb_info *fbi, int on)
1399{
1400 pr_debug("pxafb: backlight o%s\n", on ? "n" : "ff");
1401
1402 if (fbi->backlight_power)
1403 fbi->backlight_power(on);
1404}
1405
1406static inline void __pxafb_lcd_power(struct pxafb_info *fbi, int on)
1407{
1408 pr_debug("pxafb: LCD power o%s\n", on ? "n" : "ff");
1409
1410 if (fbi->lcd_power)
1411 fbi->lcd_power(on, &fbi->fb.var);
1412
1413 if (fbi->lcd_supply && fbi->lcd_supply_enabled != on) {
1414 int ret;
1415
1416 if (on)
1417 ret = regulator_enable(fbi->lcd_supply);
1418 else
1419 ret = regulator_disable(fbi->lcd_supply);
1420
1421 if (ret < 0)
1422 pr_warn("Unable to %s LCD supply regulator: %d\n",
1423 str_enable_disable(on), ret);
1424 else
1425 fbi->lcd_supply_enabled = on;
1426 }
1427}
1428
1429static void pxafb_enable_controller(struct pxafb_info *fbi)
1430{
1431 pr_debug("pxafb: Enabling LCD controller\n");
1432 pr_debug("fdadr0 0x%08x\n", (unsigned int) fbi->fdadr[0]);
1433 pr_debug("fdadr1 0x%08x\n", (unsigned int) fbi->fdadr[1]);
1434 pr_debug("reg_lccr0 0x%08x\n", (unsigned int) fbi->reg_lccr0);
1435 pr_debug("reg_lccr1 0x%08x\n", (unsigned int) fbi->reg_lccr1);
1436 pr_debug("reg_lccr2 0x%08x\n", (unsigned int) fbi->reg_lccr2);
1437 pr_debug("reg_lccr3 0x%08x\n", (unsigned int) fbi->reg_lccr3);
1438
1439 /* enable LCD controller clock */
1440 if (clk_prepare_enable(fbi->clk)) {
1441 pr_err("%s: Failed to prepare clock\n", __func__);
1442 return;
1443 }
1444
1445 if (fbi->lccr0 & LCCR0_LCDT)
1446 return;
1447
1448 /* Sequence from 11.7.10 */
1449 lcd_writel(fbi, LCCR4, fbi->reg_lccr4);
1450 lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
1451 lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
1452 lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
1453 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
1454
1455 lcd_writel(fbi, FDADR0, fbi->fdadr[0]);
1456 if (fbi->lccr0 & LCCR0_SDS)
1457 lcd_writel(fbi, FDADR1, fbi->fdadr[1]);
1458 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB);
1459}
1460
1461static void pxafb_disable_controller(struct pxafb_info *fbi)
1462{
1463 uint32_t lccr0;
1464
1465#ifdef CONFIG_FB_PXA_SMARTPANEL
1466 if (fbi->lccr0 & LCCR0_LCDT) {
1467 wait_for_completion_timeout(&fbi->refresh_done,
1468 msecs_to_jiffies(200));
1469 return;
1470 }
1471#endif
1472
1473 /* Clear LCD Status Register */
1474 lcd_writel(fbi, LCSR, 0xffffffff);
1475
1476 lccr0 = lcd_readl(fbi, LCCR0) & ~LCCR0_LDM;
1477 lcd_writel(fbi, LCCR0, lccr0);
1478 lcd_writel(fbi, LCCR0, lccr0 | LCCR0_DIS);
1479
1480 wait_for_completion_timeout(&fbi->disable_done, msecs_to_jiffies(200));
1481
1482 /* disable LCD controller clock */
1483 clk_disable_unprepare(fbi->clk);
1484}
1485
1486/*
1487 * pxafb_handle_irq: Handle 'LCD DONE' interrupts.
1488 */
1489static irqreturn_t pxafb_handle_irq(int irq, void *dev_id)
1490{
1491 struct pxafb_info *fbi = dev_id;
1492 unsigned int lccr0, lcsr;
1493
1494 lcsr = lcd_readl(fbi, LCSR);
1495 if (lcsr & LCSR_LDD) {
1496 lccr0 = lcd_readl(fbi, LCCR0);
1497 lcd_writel(fbi, LCCR0, lccr0 | LCCR0_LDM);
1498 complete(&fbi->disable_done);
1499 }
1500
1501#ifdef CONFIG_FB_PXA_SMARTPANEL
1502 if (lcsr & LCSR_CMD_INT)
1503 complete(&fbi->command_done);
1504#endif
1505 lcd_writel(fbi, LCSR, lcsr);
1506
1507#ifdef CONFIG_FB_PXA_OVERLAY
1508 {
1509 unsigned int lcsr1 = lcd_readl(fbi, LCSR1);
1510 if (lcsr1 & LCSR1_BS(1))
1511 complete(&fbi->overlay[0].branch_done);
1512
1513 if (lcsr1 & LCSR1_BS(2))
1514 complete(&fbi->overlay[1].branch_done);
1515
1516 lcd_writel(fbi, LCSR1, lcsr1);
1517 }
1518#endif
1519 return IRQ_HANDLED;
1520}
1521
1522/*
1523 * This function must be called from task context only, since it will
1524 * sleep when disabling the LCD controller, or if we get two contending
1525 * processes trying to alter state.
1526 */
1527static void set_ctrlr_state(struct pxafb_info *fbi, u_int state)
1528{
1529 u_int old_state;
1530
1531 mutex_lock(&fbi->ctrlr_lock);
1532
1533 old_state = fbi->state;
1534
1535 /*
1536 * Hack around fbcon initialisation.
1537 */
1538 if (old_state == C_STARTUP && state == C_REENABLE)
1539 state = C_ENABLE;
1540
1541 switch (state) {
1542 case C_DISABLE_CLKCHANGE:
1543 /*
1544 * Disable controller for clock change. If the
1545 * controller is already disabled, then do nothing.
1546 */
1547 if (old_state != C_DISABLE && old_state != C_DISABLE_PM) {
1548 fbi->state = state;
1549 /* TODO __pxafb_lcd_power(fbi, 0); */
1550 pxafb_disable_controller(fbi);
1551 }
1552 break;
1553
1554 case C_DISABLE_PM:
1555 case C_DISABLE:
1556 /*
1557 * Disable controller
1558 */
1559 if (old_state != C_DISABLE) {
1560 fbi->state = state;
1561 __pxafb_backlight_power(fbi, 0);
1562 __pxafb_lcd_power(fbi, 0);
1563 if (old_state != C_DISABLE_CLKCHANGE)
1564 pxafb_disable_controller(fbi);
1565 }
1566 break;
1567
1568 case C_ENABLE_CLKCHANGE:
1569 /*
1570 * Enable the controller after clock change. Only
1571 * do this if we were disabled for the clock change.
1572 */
1573 if (old_state == C_DISABLE_CLKCHANGE) {
1574 fbi->state = C_ENABLE;
1575 pxafb_enable_controller(fbi);
1576 /* TODO __pxafb_lcd_power(fbi, 1); */
1577 }
1578 break;
1579
1580 case C_REENABLE:
1581 /*
1582 * Re-enable the controller only if it was already
1583 * enabled. This is so we reprogram the control
1584 * registers.
1585 */
1586 if (old_state == C_ENABLE) {
1587 __pxafb_lcd_power(fbi, 0);
1588 pxafb_disable_controller(fbi);
1589 pxafb_enable_controller(fbi);
1590 __pxafb_lcd_power(fbi, 1);
1591 }
1592 break;
1593
1594 case C_ENABLE_PM:
1595 /*
1596 * Re-enable the controller after PM. This is not
1597 * perfect - think about the case where we were doing
1598 * a clock change, and we suspended half-way through.
1599 */
1600 if (old_state != C_DISABLE_PM)
1601 break;
1602 fallthrough;
1603
1604 case C_ENABLE:
1605 /*
1606 * Power up the LCD screen, enable controller, and
1607 * turn on the backlight.
1608 */
1609 if (old_state != C_ENABLE) {
1610 fbi->state = C_ENABLE;
1611 pxafb_enable_controller(fbi);
1612 __pxafb_lcd_power(fbi, 1);
1613 __pxafb_backlight_power(fbi, 1);
1614 }
1615 break;
1616 }
1617 mutex_unlock(&fbi->ctrlr_lock);
1618}
1619
1620/*
1621 * Our LCD controller task (which is called when we blank or unblank)
1622 * via keventd.
1623 */
1624static void pxafb_task(struct work_struct *work)
1625{
1626 struct pxafb_info *fbi =
1627 container_of(work, struct pxafb_info, task);
1628 u_int state = xchg(&fbi->task_state, -1);
1629
1630 set_ctrlr_state(fbi, state);
1631}
1632
1633#ifdef CONFIG_CPU_FREQ
1634/*
1635 * CPU clock speed change handler. We need to adjust the LCD timing
1636 * parameters when the CPU clock is adjusted by the power management
1637 * subsystem.
1638 *
1639 * TODO: Determine why f->new != 10*get_lclk_frequency_10khz()
1640 */
1641static int
1642pxafb_freq_transition(struct notifier_block *nb, unsigned long val, void *data)
1643{
1644 struct pxafb_info *fbi = TO_INF(nb, freq_transition);
1645 /* TODO struct cpufreq_freqs *f = data; */
1646 u_int pcd;
1647
1648 switch (val) {
1649 case CPUFREQ_PRECHANGE:
1650#ifdef CONFIG_FB_PXA_OVERLAY
1651 if (!(fbi->overlay[0].usage || fbi->overlay[1].usage))
1652#endif
1653 set_ctrlr_state(fbi, C_DISABLE_CLKCHANGE);
1654 break;
1655
1656 case CPUFREQ_POSTCHANGE:
1657 pcd = get_pcd(fbi, fbi->fb.var.pixclock);
1658 set_hsync_time(fbi, pcd);
1659 fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) |
1660 LCCR3_PixClkDiv(pcd);
1661 set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE);
1662 break;
1663 }
1664 return 0;
1665}
1666#endif
1667
1668#ifdef CONFIG_PM
1669/*
1670 * Power management hooks. Note that we won't be called from IRQ context,
1671 * unlike the blank functions above, so we may sleep.
1672 */
1673static int pxafb_suspend(struct device *dev)
1674{
1675 struct pxafb_info *fbi = dev_get_drvdata(dev);
1676
1677 set_ctrlr_state(fbi, C_DISABLE_PM);
1678 return 0;
1679}
1680
1681static int pxafb_resume(struct device *dev)
1682{
1683 struct pxafb_info *fbi = dev_get_drvdata(dev);
1684
1685 set_ctrlr_state(fbi, C_ENABLE_PM);
1686 return 0;
1687}
1688
1689static const struct dev_pm_ops pxafb_pm_ops = {
1690 .suspend = pxafb_suspend,
1691 .resume = pxafb_resume,
1692};
1693#endif
1694
1695static int pxafb_init_video_memory(struct pxafb_info *fbi)
1696{
1697 int size = PAGE_ALIGN(fbi->video_mem_size);
1698
1699 fbi->video_mem = alloc_pages_exact(size, GFP_KERNEL | __GFP_ZERO);
1700 if (fbi->video_mem == NULL)
1701 return -ENOMEM;
1702
1703 fbi->video_mem_phys = virt_to_phys(fbi->video_mem);
1704 fbi->video_mem_size = size;
1705
1706 fbi->fb.fix.smem_start = fbi->video_mem_phys;
1707 fbi->fb.fix.smem_len = fbi->video_mem_size;
1708 fbi->fb.screen_base = fbi->video_mem;
1709
1710 return fbi->video_mem ? 0 : -ENOMEM;
1711}
1712
1713static void pxafb_decode_mach_info(struct pxafb_info *fbi,
1714 struct pxafb_mach_info *inf)
1715{
1716 unsigned int lcd_conn = inf->lcd_conn;
1717 struct pxafb_mode_info *m;
1718 int i;
1719
1720 fbi->cmap_inverse = inf->cmap_inverse;
1721 fbi->cmap_static = inf->cmap_static;
1722 fbi->lccr4 = inf->lccr4;
1723
1724 switch (lcd_conn & LCD_TYPE_MASK) {
1725 case LCD_TYPE_MONO_STN:
1726 fbi->lccr0 = LCCR0_CMS;
1727 break;
1728 case LCD_TYPE_MONO_DSTN:
1729 fbi->lccr0 = LCCR0_CMS | LCCR0_SDS;
1730 break;
1731 case LCD_TYPE_COLOR_STN:
1732 fbi->lccr0 = 0;
1733 break;
1734 case LCD_TYPE_COLOR_DSTN:
1735 fbi->lccr0 = LCCR0_SDS;
1736 break;
1737 case LCD_TYPE_COLOR_TFT:
1738 fbi->lccr0 = LCCR0_PAS;
1739 break;
1740 case LCD_TYPE_SMART_PANEL:
1741 fbi->lccr0 = LCCR0_LCDT | LCCR0_PAS;
1742 break;
1743 default:
1744 /* fall back to backward compatibility way */
1745 fbi->lccr0 = inf->lccr0;
1746 fbi->lccr3 = inf->lccr3;
1747 goto decode_mode;
1748 }
1749
1750 if (lcd_conn == LCD_MONO_STN_8BPP)
1751 fbi->lccr0 |= LCCR0_DPD;
1752
1753 fbi->lccr0 |= (lcd_conn & LCD_ALTERNATE_MAPPING) ? LCCR0_LDDALT : 0;
1754
1755 fbi->lccr3 = LCCR3_Acb((inf->lcd_conn >> 10) & 0xff);
1756 fbi->lccr3 |= (lcd_conn & LCD_BIAS_ACTIVE_LOW) ? LCCR3_OEP : 0;
1757 fbi->lccr3 |= (lcd_conn & LCD_PCLK_EDGE_FALL) ? LCCR3_PCP : 0;
1758
1759decode_mode:
1760 pxafb_setmode(&fbi->fb.var, &inf->modes[0]);
1761
1762 /* decide video memory size as follows:
1763 * 1. default to mode of maximum resolution
1764 * 2. allow platform to override
1765 * 3. allow module parameter to override
1766 */
1767 for (i = 0, m = &inf->modes[0]; i < inf->num_modes; i++, m++)
1768 fbi->video_mem_size = max_t(size_t, fbi->video_mem_size,
1769 m->xres * m->yres * m->bpp / 8);
1770
1771 if (inf->video_mem_size > fbi->video_mem_size)
1772 fbi->video_mem_size = inf->video_mem_size;
1773
1774 if (video_mem_size > fbi->video_mem_size)
1775 fbi->video_mem_size = video_mem_size;
1776}
1777
1778static struct pxafb_info *pxafb_init_fbinfo(struct device *dev,
1779 struct pxafb_mach_info *inf)
1780{
1781 struct pxafb_info *fbi;
1782 void *addr;
1783
1784 /* Alloc the pxafb_info and pseudo_palette in one step */
1785 fbi = devm_kzalloc(dev, sizeof(struct pxafb_info) + sizeof(u32) * 16,
1786 GFP_KERNEL);
1787 if (!fbi)
1788 return ERR_PTR(-ENOMEM);
1789
1790 fbi->dev = dev;
1791 fbi->inf = inf;
1792
1793 fbi->clk = devm_clk_get(dev, NULL);
1794 if (IS_ERR(fbi->clk))
1795 return ERR_CAST(fbi->clk);
1796
1797 strcpy(fbi->fb.fix.id, PXA_NAME);
1798
1799 fbi->fb.fix.type = FB_TYPE_PACKED_PIXELS;
1800 fbi->fb.fix.type_aux = 0;
1801 fbi->fb.fix.xpanstep = 0;
1802 fbi->fb.fix.ypanstep = 1;
1803 fbi->fb.fix.ywrapstep = 0;
1804 fbi->fb.fix.accel = FB_ACCEL_NONE;
1805
1806 fbi->fb.var.nonstd = 0;
1807 fbi->fb.var.activate = FB_ACTIVATE_NOW;
1808 fbi->fb.var.height = -1;
1809 fbi->fb.var.width = -1;
1810 fbi->fb.var.accel_flags = FB_ACCELF_TEXT;
1811 fbi->fb.var.vmode = FB_VMODE_NONINTERLACED;
1812
1813 fbi->fb.fbops = &pxafb_ops;
1814 fbi->fb.node = -1;
1815
1816 addr = fbi;
1817 addr = addr + sizeof(struct pxafb_info);
1818 fbi->fb.pseudo_palette = addr;
1819
1820 fbi->state = C_STARTUP;
1821 fbi->task_state = (u_char)-1;
1822
1823 pxafb_decode_mach_info(fbi, inf);
1824
1825#ifdef CONFIG_FB_PXA_OVERLAY
1826 /* place overlay(s) on top of base */
1827 if (pxafb_overlay_supported())
1828 fbi->lccr0 |= LCCR0_OUC;
1829#endif
1830
1831 init_waitqueue_head(&fbi->ctrlr_wait);
1832 INIT_WORK(&fbi->task, pxafb_task);
1833 mutex_init(&fbi->ctrlr_lock);
1834 init_completion(&fbi->disable_done);
1835
1836 return fbi;
1837}
1838
1839#ifdef CONFIG_FB_PXA_PARAMETERS
1840static int parse_opt_mode(struct device *dev, const char *this_opt,
1841 struct pxafb_mach_info *inf)
1842{
1843 const char *name = this_opt+5;
1844 unsigned int namelen = strlen(name);
1845 int res_specified = 0, bpp_specified = 0;
1846 unsigned int xres = 0, yres = 0, bpp = 0;
1847 int yres_specified = 0;
1848 int i;
1849 for (i = namelen-1; i >= 0; i--) {
1850 switch (name[i]) {
1851 case '-':
1852 namelen = i;
1853 if (!bpp_specified && !yres_specified) {
1854 bpp = simple_strtoul(&name[i+1], NULL, 0);
1855 bpp_specified = 1;
1856 } else
1857 goto done;
1858 break;
1859 case 'x':
1860 if (!yres_specified) {
1861 yres = simple_strtoul(&name[i+1], NULL, 0);
1862 yres_specified = 1;
1863 } else
1864 goto done;
1865 break;
1866 case '0' ... '9':
1867 break;
1868 default:
1869 goto done;
1870 }
1871 }
1872 if (i < 0 && yres_specified) {
1873 xres = simple_strtoul(name, NULL, 0);
1874 res_specified = 1;
1875 }
1876done:
1877 if (res_specified) {
1878 dev_info(dev, "overriding resolution: %dx%d\n", xres, yres);
1879 inf->modes[0].xres = xres; inf->modes[0].yres = yres;
1880 }
1881 if (bpp_specified)
1882 switch (bpp) {
1883 case 1:
1884 case 2:
1885 case 4:
1886 case 8:
1887 case 16:
1888 inf->modes[0].bpp = bpp;
1889 dev_info(dev, "overriding bit depth: %d\n", bpp);
1890 break;
1891 default:
1892 dev_err(dev, "Depth %d is not valid\n", bpp);
1893 return -EINVAL;
1894 }
1895 return 0;
1896}
1897
1898static int parse_opt(struct device *dev, char *this_opt,
1899 struct pxafb_mach_info *inf)
1900{
1901 struct pxafb_mode_info *mode = &inf->modes[0];
1902 char s[64];
1903
1904 s[0] = '\0';
1905
1906 if (!strncmp(this_opt, "vmem:", 5)) {
1907 video_mem_size = memparse(this_opt + 5, NULL);
1908 } else if (!strncmp(this_opt, "mode:", 5)) {
1909 return parse_opt_mode(dev, this_opt, inf);
1910 } else if (!strncmp(this_opt, "pixclock:", 9)) {
1911 mode->pixclock = simple_strtoul(this_opt+9, NULL, 0);
1912 sprintf(s, "pixclock: %ld\n", mode->pixclock);
1913 } else if (!strncmp(this_opt, "left:", 5)) {
1914 mode->left_margin = simple_strtoul(this_opt+5, NULL, 0);
1915 sprintf(s, "left: %u\n", mode->left_margin);
1916 } else if (!strncmp(this_opt, "right:", 6)) {
1917 mode->right_margin = simple_strtoul(this_opt+6, NULL, 0);
1918 sprintf(s, "right: %u\n", mode->right_margin);
1919 } else if (!strncmp(this_opt, "upper:", 6)) {
1920 mode->upper_margin = simple_strtoul(this_opt+6, NULL, 0);
1921 sprintf(s, "upper: %u\n", mode->upper_margin);
1922 } else if (!strncmp(this_opt, "lower:", 6)) {
1923 mode->lower_margin = simple_strtoul(this_opt+6, NULL, 0);
1924 sprintf(s, "lower: %u\n", mode->lower_margin);
1925 } else if (!strncmp(this_opt, "hsynclen:", 9)) {
1926 mode->hsync_len = simple_strtoul(this_opt+9, NULL, 0);
1927 sprintf(s, "hsynclen: %u\n", mode->hsync_len);
1928 } else if (!strncmp(this_opt, "vsynclen:", 9)) {
1929 mode->vsync_len = simple_strtoul(this_opt+9, NULL, 0);
1930 sprintf(s, "vsynclen: %u\n", mode->vsync_len);
1931 } else if (!strncmp(this_opt, "hsync:", 6)) {
1932 if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1933 sprintf(s, "hsync: Active Low\n");
1934 mode->sync &= ~FB_SYNC_HOR_HIGH_ACT;
1935 } else {
1936 sprintf(s, "hsync: Active High\n");
1937 mode->sync |= FB_SYNC_HOR_HIGH_ACT;
1938 }
1939 } else if (!strncmp(this_opt, "vsync:", 6)) {
1940 if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1941 sprintf(s, "vsync: Active Low\n");
1942 mode->sync &= ~FB_SYNC_VERT_HIGH_ACT;
1943 } else {
1944 sprintf(s, "vsync: Active High\n");
1945 mode->sync |= FB_SYNC_VERT_HIGH_ACT;
1946 }
1947 } else if (!strncmp(this_opt, "dpc:", 4)) {
1948 if (simple_strtoul(this_opt+4, NULL, 0) == 0) {
1949 sprintf(s, "double pixel clock: false\n");
1950 inf->lccr3 &= ~LCCR3_DPC;
1951 } else {
1952 sprintf(s, "double pixel clock: true\n");
1953 inf->lccr3 |= LCCR3_DPC;
1954 }
1955 } else if (!strncmp(this_opt, "outputen:", 9)) {
1956 if (simple_strtoul(this_opt+9, NULL, 0) == 0) {
1957 sprintf(s, "output enable: active low\n");
1958 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnL;
1959 } else {
1960 sprintf(s, "output enable: active high\n");
1961 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnH;
1962 }
1963 } else if (!strncmp(this_opt, "pixclockpol:", 12)) {
1964 if (simple_strtoul(this_opt+12, NULL, 0) == 0) {
1965 sprintf(s, "pixel clock polarity: falling edge\n");
1966 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixFlEdg;
1967 } else {
1968 sprintf(s, "pixel clock polarity: rising edge\n");
1969 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixRsEdg;
1970 }
1971 } else if (!strncmp(this_opt, "color", 5)) {
1972 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Color;
1973 } else if (!strncmp(this_opt, "mono", 4)) {
1974 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Mono;
1975 } else if (!strncmp(this_opt, "active", 6)) {
1976 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Act;
1977 } else if (!strncmp(this_opt, "passive", 7)) {
1978 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Pas;
1979 } else if (!strncmp(this_opt, "single", 6)) {
1980 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Sngl;
1981 } else if (!strncmp(this_opt, "dual", 4)) {
1982 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Dual;
1983 } else if (!strncmp(this_opt, "4pix", 4)) {
1984 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_4PixMono;
1985 } else if (!strncmp(this_opt, "8pix", 4)) {
1986 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_8PixMono;
1987 } else {
1988 dev_err(dev, "unknown option: %s\n", this_opt);
1989 return -EINVAL;
1990 }
1991
1992 if (s[0] != '\0')
1993 dev_info(dev, "override %s", s);
1994
1995 return 0;
1996}
1997
1998static int pxafb_parse_options(struct device *dev, char *options,
1999 struct pxafb_mach_info *inf)
2000{
2001 char *this_opt;
2002 int ret;
2003
2004 if (!options || !*options)
2005 return 0;
2006
2007 dev_dbg(dev, "options are \"%s\"\n", options ? options : "null");
2008
2009 /* could be made table driven or similar?... */
2010 while ((this_opt = strsep(&options, ",")) != NULL) {
2011 ret = parse_opt(dev, this_opt, inf);
2012 if (ret)
2013 return ret;
2014 }
2015 return 0;
2016}
2017
2018static char g_options[256] = "";
2019
2020#ifndef MODULE
2021static int __init pxafb_setup_options(void)
2022{
2023 char *options = NULL;
2024
2025 if (fb_get_options("pxafb", &options))
2026 return -ENODEV;
2027
2028 if (options)
2029 strscpy(g_options, options, sizeof(g_options));
2030
2031 return 0;
2032}
2033#else
2034#define pxafb_setup_options() (0)
2035
2036module_param_string(options, g_options, sizeof(g_options), 0);
2037MODULE_PARM_DESC(options, "LCD parameters (see Documentation/fb/pxafb.rst)");
2038#endif
2039
2040#else
2041#define pxafb_parse_options(...) (0)
2042#define pxafb_setup_options() (0)
2043#endif
2044
2045#ifdef DEBUG_VAR
2046/* Check for various illegal bit-combinations. Currently only
2047 * a warning is given. */
2048static void pxafb_check_options(struct device *dev, struct pxafb_mach_info *inf)
2049{
2050 if (inf->lcd_conn)
2051 return;
2052
2053 if (inf->lccr0 & LCCR0_INVALID_CONFIG_MASK)
2054 dev_warn(dev, "machine LCCR0 setting contains "
2055 "illegal bits: %08x\n",
2056 inf->lccr0 & LCCR0_INVALID_CONFIG_MASK);
2057 if (inf->lccr3 & LCCR3_INVALID_CONFIG_MASK)
2058 dev_warn(dev, "machine LCCR3 setting contains "
2059 "illegal bits: %08x\n",
2060 inf->lccr3 & LCCR3_INVALID_CONFIG_MASK);
2061 if (inf->lccr0 & LCCR0_DPD &&
2062 ((inf->lccr0 & LCCR0_PAS) != LCCR0_Pas ||
2063 (inf->lccr0 & LCCR0_SDS) != LCCR0_Sngl ||
2064 (inf->lccr0 & LCCR0_CMS) != LCCR0_Mono))
2065 dev_warn(dev, "Double Pixel Data (DPD) mode is "
2066 "only valid in passive mono"
2067 " single panel mode\n");
2068 if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Act &&
2069 (inf->lccr0 & LCCR0_SDS) == LCCR0_Dual)
2070 dev_warn(dev, "Dual panel only valid in passive mode\n");
2071 if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Pas &&
2072 (inf->modes->upper_margin || inf->modes->lower_margin))
2073 dev_warn(dev, "Upper and lower margins must be 0 in "
2074 "passive mode\n");
2075}
2076#else
2077#define pxafb_check_options(...) do {} while (0)
2078#endif
2079
2080#if defined(CONFIG_OF)
2081static const char * const lcd_types[] = {
2082 "unknown", "mono-stn", "mono-dstn", "color-stn", "color-dstn",
2083 "color-tft", "smart-panel", NULL
2084};
2085
2086static int of_get_pxafb_display(struct device *dev, struct device_node *disp,
2087 struct pxafb_mach_info *info, u32 bus_width)
2088{
2089 struct display_timings *timings;
2090 struct videomode vm;
2091 int i, ret = -EINVAL;
2092 const char *s;
2093
2094 ret = of_property_read_string(disp, "lcd-type", &s);
2095 if (ret)
2096 s = "color-tft";
2097
2098 i = match_string(lcd_types, -1, s);
2099 if (i < 0) {
2100 dev_err(dev, "lcd-type %s is unknown\n", s);
2101 return i;
2102 }
2103 info->lcd_conn |= LCD_CONN_TYPE(i);
2104 info->lcd_conn |= LCD_CONN_WIDTH(bus_width);
2105
2106 timings = of_get_display_timings(disp);
2107 if (!timings)
2108 return -EINVAL;
2109
2110 ret = -ENOMEM;
2111 info->modes = devm_kcalloc(dev, timings->num_timings,
2112 sizeof(info->modes[0]),
2113 GFP_KERNEL);
2114 if (!info->modes)
2115 goto out;
2116 info->num_modes = timings->num_timings;
2117
2118 for (i = 0; i < timings->num_timings; i++) {
2119 ret = videomode_from_timings(timings, &vm, i);
2120 if (ret) {
2121 dev_err(dev, "videomode_from_timings %d failed: %d\n",
2122 i, ret);
2123 goto out;
2124 }
2125 if (vm.flags & DISPLAY_FLAGS_PIXDATA_POSEDGE)
2126 info->lcd_conn |= LCD_PCLK_EDGE_RISE;
2127 if (vm.flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
2128 info->lcd_conn |= LCD_PCLK_EDGE_FALL;
2129 if (vm.flags & DISPLAY_FLAGS_DE_HIGH)
2130 info->lcd_conn |= LCD_BIAS_ACTIVE_HIGH;
2131 if (vm.flags & DISPLAY_FLAGS_DE_LOW)
2132 info->lcd_conn |= LCD_BIAS_ACTIVE_LOW;
2133 if (vm.flags & DISPLAY_FLAGS_HSYNC_HIGH)
2134 info->modes[i].sync |= FB_SYNC_HOR_HIGH_ACT;
2135 if (vm.flags & DISPLAY_FLAGS_VSYNC_HIGH)
2136 info->modes[i].sync |= FB_SYNC_VERT_HIGH_ACT;
2137
2138 info->modes[i].pixclock = 1000000000UL / (vm.pixelclock / 1000);
2139 info->modes[i].xres = vm.hactive;
2140 info->modes[i].yres = vm.vactive;
2141 info->modes[i].hsync_len = vm.hsync_len;
2142 info->modes[i].left_margin = vm.hback_porch;
2143 info->modes[i].right_margin = vm.hfront_porch;
2144 info->modes[i].vsync_len = vm.vsync_len;
2145 info->modes[i].upper_margin = vm.vback_porch;
2146 info->modes[i].lower_margin = vm.vfront_porch;
2147 }
2148 ret = 0;
2149
2150out:
2151 display_timings_release(timings);
2152 return ret;
2153}
2154
2155static int of_get_pxafb_mode_info(struct device *dev,
2156 struct pxafb_mach_info *info)
2157{
2158 struct device_node *display, *np;
2159 u32 bus_width;
2160 int ret, i;
2161
2162 np = of_graph_get_endpoint_by_regs(dev->of_node, 0, -1);
2163 if (!np) {
2164 dev_err(dev, "could not find endpoint\n");
2165 return -EINVAL;
2166 }
2167 ret = of_property_read_u32(np, "bus-width", &bus_width);
2168 if (ret) {
2169 dev_err(dev, "no bus-width specified: %d\n", ret);
2170 of_node_put(np);
2171 return ret;
2172 }
2173
2174 display = of_graph_get_remote_port_parent(np);
2175 of_node_put(np);
2176 if (!display) {
2177 dev_err(dev, "no display defined\n");
2178 return -EINVAL;
2179 }
2180
2181 ret = of_get_pxafb_display(dev, display, info, bus_width);
2182 of_node_put(display);
2183 if (ret)
2184 return ret;
2185
2186 for (i = 0; i < info->num_modes; i++)
2187 info->modes[i].bpp = bus_width;
2188
2189 return 0;
2190}
2191
2192static struct pxafb_mach_info *of_pxafb_of_mach_info(struct device *dev)
2193{
2194 int ret;
2195 struct pxafb_mach_info *info;
2196
2197 if (!dev->of_node)
2198 return NULL;
2199 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
2200 if (!info)
2201 return ERR_PTR(-ENOMEM);
2202 ret = of_get_pxafb_mode_info(dev, info);
2203 if (ret)
2204 return ERR_PTR(ret);
2205
2206 /*
2207 * On purpose, neither lccrX registers nor video memory size can be
2208 * specified through device-tree, they are considered more a debug hack
2209 * available through command line.
2210 */
2211 return info;
2212}
2213#else
2214static struct pxafb_mach_info *of_pxafb_of_mach_info(struct device *dev)
2215{
2216 return NULL;
2217}
2218#endif
2219
2220static int pxafb_probe(struct platform_device *dev)
2221{
2222 struct pxafb_info *fbi;
2223 struct pxafb_mach_info *inf, *pdata;
2224 int irq, ret;
2225
2226 dev_dbg(&dev->dev, "pxafb_probe\n");
2227
2228 ret = -ENOMEM;
2229 pdata = dev_get_platdata(&dev->dev);
2230 if (pdata) {
2231 inf = devm_kmemdup(&dev->dev, pdata, sizeof(*pdata), GFP_KERNEL);
2232 if (!inf)
2233 goto failed;
2234
2235 inf->modes = devm_kmemdup_array(&dev->dev, pdata->modes, pdata->num_modes,
2236 sizeof(*pdata->modes), GFP_KERNEL);
2237 if (!inf->modes)
2238 goto failed;
2239 } else {
2240 inf = of_pxafb_of_mach_info(&dev->dev);
2241 if (IS_ERR_OR_NULL(inf))
2242 goto failed;
2243 }
2244
2245 ret = pxafb_parse_options(&dev->dev, g_options, inf);
2246 if (ret < 0)
2247 goto failed;
2248
2249 pxafb_check_options(&dev->dev, inf);
2250
2251 dev_dbg(&dev->dev, "got a %dx%dx%d LCD\n",
2252 inf->modes->xres,
2253 inf->modes->yres,
2254 inf->modes->bpp);
2255 if (inf->modes->xres == 0 ||
2256 inf->modes->yres == 0 ||
2257 inf->modes->bpp == 0) {
2258 dev_err(&dev->dev, "Invalid resolution or bit depth\n");
2259 ret = -EINVAL;
2260 goto failed;
2261 }
2262
2263 fbi = pxafb_init_fbinfo(&dev->dev, inf);
2264 if (IS_ERR(fbi)) {
2265 dev_err(&dev->dev, "Failed to initialize framebuffer device\n");
2266 ret = PTR_ERR(fbi);
2267 goto failed;
2268 }
2269
2270 if (cpu_is_pxa3xx() && inf->acceleration_enabled)
2271 fbi->fb.fix.accel = FB_ACCEL_PXA3XX;
2272
2273 fbi->backlight_power = inf->pxafb_backlight_power;
2274 fbi->lcd_power = inf->pxafb_lcd_power;
2275
2276 fbi->lcd_supply = devm_regulator_get_optional(&dev->dev, "lcd");
2277 if (IS_ERR(fbi->lcd_supply)) {
2278 if (PTR_ERR(fbi->lcd_supply) == -EPROBE_DEFER)
2279 return -EPROBE_DEFER;
2280
2281 fbi->lcd_supply = NULL;
2282 }
2283
2284 fbi->mmio_base = devm_platform_ioremap_resource(dev, 0);
2285 if (IS_ERR(fbi->mmio_base)) {
2286 dev_err(&dev->dev, "failed to get I/O memory\n");
2287 ret = PTR_ERR(fbi->mmio_base);
2288 goto failed;
2289 }
2290
2291 fbi->dma_buff_size = PAGE_ALIGN(sizeof(struct pxafb_dma_buff));
2292 fbi->dma_buff = dma_alloc_coherent(fbi->dev, fbi->dma_buff_size,
2293 &fbi->dma_buff_phys, GFP_KERNEL);
2294 if (fbi->dma_buff == NULL) {
2295 dev_err(&dev->dev, "failed to allocate memory for DMA\n");
2296 ret = -ENOMEM;
2297 goto failed;
2298 }
2299
2300 ret = pxafb_init_video_memory(fbi);
2301 if (ret) {
2302 dev_err(&dev->dev, "Failed to allocate video RAM: %d\n", ret);
2303 ret = -ENOMEM;
2304 goto failed_free_dma;
2305 }
2306
2307 irq = platform_get_irq(dev, 0);
2308 if (irq < 0) {
2309 ret = -ENODEV;
2310 goto failed_free_mem;
2311 }
2312
2313 ret = devm_request_irq(&dev->dev, irq, pxafb_handle_irq, 0, "LCD", fbi);
2314 if (ret) {
2315 ret = -EBUSY;
2316 goto failed_free_mem;
2317 }
2318
2319 ret = pxafb_smart_init(fbi);
2320 if (ret) {
2321 dev_err(&dev->dev, "failed to initialize smartpanel\n");
2322 goto failed_free_mem;
2323 }
2324
2325 /*
2326 * This makes sure that our colour bitfield
2327 * descriptors are correctly initialised.
2328 */
2329 ret = pxafb_check_var(&fbi->fb.var, &fbi->fb);
2330 if (ret) {
2331 dev_err(&dev->dev, "failed to get suitable mode\n");
2332 goto failed_free_mem;
2333 }
2334
2335 ret = pxafb_set_par(&fbi->fb);
2336 if (ret) {
2337 dev_err(&dev->dev, "Failed to set parameters\n");
2338 goto failed_free_mem;
2339 }
2340
2341 platform_set_drvdata(dev, fbi);
2342
2343 ret = register_framebuffer(&fbi->fb);
2344 if (ret < 0) {
2345 dev_err(&dev->dev,
2346 "Failed to register framebuffer device: %d\n", ret);
2347 goto failed_free_cmap;
2348 }
2349
2350 pxafb_overlay_init(fbi);
2351
2352#ifdef CONFIG_CPU_FREQ
2353 fbi->freq_transition.notifier_call = pxafb_freq_transition;
2354 cpufreq_register_notifier(&fbi->freq_transition,
2355 CPUFREQ_TRANSITION_NOTIFIER);
2356#endif
2357
2358 /*
2359 * Ok, now enable the LCD controller
2360 */
2361 set_ctrlr_state(fbi, C_ENABLE);
2362
2363 return 0;
2364
2365failed_free_cmap:
2366 if (fbi->fb.cmap.len)
2367 fb_dealloc_cmap(&fbi->fb.cmap);
2368failed_free_mem:
2369 free_pages_exact(fbi->video_mem, fbi->video_mem_size);
2370failed_free_dma:
2371 dma_free_coherent(&dev->dev, fbi->dma_buff_size,
2372 fbi->dma_buff, fbi->dma_buff_phys);
2373failed:
2374 return ret;
2375}
2376
2377static void pxafb_remove(struct platform_device *dev)
2378{
2379 struct pxafb_info *fbi = platform_get_drvdata(dev);
2380 struct fb_info *info;
2381
2382 if (!fbi)
2383 return;
2384
2385 info = &fbi->fb;
2386
2387 pxafb_overlay_exit(fbi);
2388 cancel_work_sync(&fbi->task);
2389 unregister_framebuffer(info);
2390
2391 pxafb_disable_controller(fbi);
2392
2393 if (fbi->fb.cmap.len)
2394 fb_dealloc_cmap(&fbi->fb.cmap);
2395
2396 free_pages_exact(fbi->video_mem, fbi->video_mem_size);
2397
2398 dma_free_coherent(&dev->dev, fbi->dma_buff_size, fbi->dma_buff,
2399 fbi->dma_buff_phys);
2400}
2401
2402static const struct of_device_id pxafb_of_dev_id[] = {
2403 { .compatible = "marvell,pxa270-lcdc", },
2404 { .compatible = "marvell,pxa300-lcdc", },
2405 { .compatible = "marvell,pxa2xx-lcdc", },
2406 { /* sentinel */ }
2407};
2408MODULE_DEVICE_TABLE(of, pxafb_of_dev_id);
2409
2410static struct platform_driver pxafb_driver = {
2411 .probe = pxafb_probe,
2412 .remove = pxafb_remove,
2413 .driver = {
2414 .name = "pxa2xx-fb",
2415 .of_match_table = pxafb_of_dev_id,
2416#ifdef CONFIG_PM
2417 .pm = &pxafb_pm_ops,
2418#endif
2419 },
2420};
2421
2422static int __init pxafb_init(void)
2423{
2424 if (pxafb_setup_options())
2425 return -EINVAL;
2426
2427 return platform_driver_register(&pxafb_driver);
2428}
2429
2430static void __exit pxafb_exit(void)
2431{
2432 platform_driver_unregister(&pxafb_driver);
2433}
2434
2435module_init(pxafb_init);
2436module_exit(pxafb_exit);
2437
2438MODULE_DESCRIPTION("loadable framebuffer driver for PXA");
2439MODULE_LICENSE("GPL");