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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * intel TCO Watchdog Driver
4 *
5 * (c) Copyright 2006-2011 Wim Van Sebroeck <[email protected]>.
6 *
7 * Neither Wim Van Sebroeck nor Iguana vzw. admit liability nor
8 * provide warranty for any of this software. This material is
9 * provided "AS-IS" and at no charge.
10 *
11 * The TCO watchdog is implemented in the following I/O controller hubs:
12 * (See the intel documentation on http://developer.intel.com.)
13 * document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO)
14 * document number 290687-002, 298242-027: 82801BA (ICH2)
15 * document number 290733-003, 290739-013: 82801CA (ICH3-S)
16 * document number 290716-001, 290718-007: 82801CAM (ICH3-M)
17 * document number 290744-001, 290745-025: 82801DB (ICH4)
18 * document number 252337-001, 252663-008: 82801DBM (ICH4-M)
19 * document number 273599-001, 273645-002: 82801E (C-ICH)
20 * document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R)
21 * document number 300641-004, 300884-013: 6300ESB
22 * document number 301473-002, 301474-026: 82801F (ICH6)
23 * document number 313082-001, 313075-006: 631xESB, 632xESB
24 * document number 307013-003, 307014-024: 82801G (ICH7)
25 * document number 322896-001, 322897-001: NM10
26 * document number 313056-003, 313057-017: 82801H (ICH8)
27 * document number 316972-004, 316973-012: 82801I (ICH9)
28 * document number 319973-002, 319974-002: 82801J (ICH10)
29 * document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH)
30 * document number 320066-003, 320257-008: EP80597 (IICH)
31 * document number 324645-001, 324646-001: Cougar Point (CPT)
32 * document number TBD : Patsburg (PBG)
33 * document number TBD : DH89xxCC
34 * document number TBD : Panther Point
35 * document number TBD : Lynx Point
36 * document number TBD : Lynx Point-LP
37 */
38
39/*
40 * Includes, defines, variables, module parameters, ...
41 */
42
43/* Module and version information */
44#define DRV_NAME "iTCO_wdt"
45#define DRV_VERSION "1.11"
46
47/* Includes */
48#include <linux/acpi.h> /* For ACPI support */
49#include <linux/bits.h> /* For BIT() */
50#include <linux/module.h> /* For module specific items */
51#include <linux/moduleparam.h> /* For new moduleparam's */
52#include <linux/types.h> /* For standard types (like size_t) */
53#include <linux/errno.h> /* For the -ENODEV/... values */
54#include <linux/kernel.h> /* For printk/panic/... */
55#include <linux/watchdog.h> /* For the watchdog specific items */
56#include <linux/init.h> /* For __init/__exit/... */
57#include <linux/fs.h> /* For file operations */
58#include <linux/platform_device.h> /* For platform_driver framework */
59#include <linux/pci.h> /* For pci functions */
60#include <linux/ioport.h> /* For io-port access */
61#include <linux/uaccess.h> /* For copy_to_user/put_user/... */
62#include <linux/io.h> /* For inb/outb/... */
63#include <linux/platform_data/itco_wdt.h>
64#include <linux/mfd/intel_pmc_bxt.h>
65
66/* Address definitions for the TCO */
67/* TCO base address */
68#define TCOBASE(p) ((p)->tco_res->start)
69/* SMI Control and Enable Register */
70#define SMI_EN(p) ((p)->smi_res->start)
71
72#define TCO_RLD(p) (TCOBASE(p) + 0x00) /* TCO Timer Reload/Curr. Value */
73#define TCOv1_TMR(p) (TCOBASE(p) + 0x01) /* TCOv1 Timer Initial Value*/
74#define TCO_DAT_IN(p) (TCOBASE(p) + 0x02) /* TCO Data In Register */
75#define TCO_DAT_OUT(p) (TCOBASE(p) + 0x03) /* TCO Data Out Register */
76#define TCO1_STS(p) (TCOBASE(p) + 0x04) /* TCO1 Status Register */
77#define TCO2_STS(p) (TCOBASE(p) + 0x06) /* TCO2 Status Register */
78#define TCO1_CNT(p) (TCOBASE(p) + 0x08) /* TCO1 Control Register */
79#define TCO2_CNT(p) (TCOBASE(p) + 0x0a) /* TCO2 Control Register */
80#define TCOv2_TMR(p) (TCOBASE(p) + 0x12) /* TCOv2 Timer Initial Value*/
81
82/*
83 * NMI_NOW is bit 8 of TCO1_CNT register
84 * Read/Write
85 * This bit is implemented as RW but has no effect on HW.
86 */
87#define NMI_NOW BIT(8)
88
89/* internal variables */
90struct iTCO_wdt_private {
91 struct watchdog_device wddev;
92
93 /* TCO version/generation */
94 unsigned int iTCO_version;
95 struct resource *tco_res;
96 struct resource *smi_res;
97 /*
98 * NO_REBOOT flag is Memory-Mapped GCS register bit 5 (TCO version 2),
99 * or memory-mapped PMC register bit 4 (TCO version 3).
100 */
101 unsigned long __iomem *gcs_pmc;
102 /* the PCI-device */
103 struct pci_dev *pci_dev;
104 /* whether or not the watchdog has been suspended */
105 bool suspended;
106 /* no reboot API private data */
107 void *no_reboot_priv;
108 /* no reboot update function pointer */
109 int (*update_no_reboot_bit)(void *p, bool set);
110};
111
112/* module parameters */
113#define WATCHDOG_TIMEOUT 30 /* 30 sec default heartbeat */
114static int heartbeat = WATCHDOG_TIMEOUT; /* in seconds */
115module_param(heartbeat, int, 0);
116MODULE_PARM_DESC(heartbeat, "Watchdog timeout in seconds. "
117 "5..76 (TCO v1) or 3..614 (TCO v2), default="
118 __MODULE_STRING(WATCHDOG_TIMEOUT) ")");
119
120static bool nowayout = WATCHDOG_NOWAYOUT;
121module_param(nowayout, bool, 0);
122MODULE_PARM_DESC(nowayout,
123 "Watchdog cannot be stopped once started (default="
124 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
125
126static int turn_SMI_watchdog_clear_off = 1;
127module_param(turn_SMI_watchdog_clear_off, int, 0);
128MODULE_PARM_DESC(turn_SMI_watchdog_clear_off,
129 "Turn off SMI clearing watchdog (depends on TCO-version)(default=1)");
130
131/*
132 * Some TCO specific functions
133 */
134
135/*
136 * The iTCO v1 and v2's internal timer is stored as ticks which decrement
137 * every 0.6 seconds. v3's internal timer is stored as seconds (some
138 * datasheets incorrectly state 0.6 seconds).
139 */
140static inline unsigned int seconds_to_ticks(struct iTCO_wdt_private *p,
141 int secs)
142{
143 return p->iTCO_version == 3 ? secs : (secs * 10) / 6;
144}
145
146static inline unsigned int ticks_to_seconds(struct iTCO_wdt_private *p,
147 int ticks)
148{
149 return p->iTCO_version == 3 ? ticks : (ticks * 6) / 10;
150}
151
152static inline u32 no_reboot_bit(struct iTCO_wdt_private *p)
153{
154 u32 enable_bit;
155
156 switch (p->iTCO_version) {
157 case 5:
158 case 3:
159 enable_bit = 0x00000010;
160 break;
161 case 2:
162 enable_bit = 0x00000020;
163 break;
164 case 4:
165 case 1:
166 default:
167 enable_bit = 0x00000002;
168 break;
169 }
170
171 return enable_bit;
172}
173
174static int update_no_reboot_bit_def(void *priv, bool set)
175{
176 return 0;
177}
178
179static int update_no_reboot_bit_pci(void *priv, bool set)
180{
181 struct iTCO_wdt_private *p = priv;
182 u32 val32 = 0, newval32 = 0;
183
184 pci_read_config_dword(p->pci_dev, 0xd4, &val32);
185 if (set)
186 val32 |= no_reboot_bit(p);
187 else
188 val32 &= ~no_reboot_bit(p);
189 pci_write_config_dword(p->pci_dev, 0xd4, val32);
190 pci_read_config_dword(p->pci_dev, 0xd4, &newval32);
191
192 /* make sure the update is successful */
193 if (val32 != newval32)
194 return -EIO;
195
196 return 0;
197}
198
199static int update_no_reboot_bit_mem(void *priv, bool set)
200{
201 struct iTCO_wdt_private *p = priv;
202 u32 val32 = 0, newval32 = 0;
203
204 val32 = readl(p->gcs_pmc);
205 if (set)
206 val32 |= no_reboot_bit(p);
207 else
208 val32 &= ~no_reboot_bit(p);
209 writel(val32, p->gcs_pmc);
210 newval32 = readl(p->gcs_pmc);
211
212 /* make sure the update is successful */
213 if (val32 != newval32)
214 return -EIO;
215
216 return 0;
217}
218
219static int update_no_reboot_bit_cnt(void *priv, bool set)
220{
221 struct iTCO_wdt_private *p = priv;
222 u16 val, newval;
223
224 /*
225 * writing back 1b1 to NMI_NOW of TCO1_CNT register
226 * causes NMI_NOW bit inversion what consequently does
227 * not allow to perform the register's value comparison
228 * properly.
229 *
230 * NMI_NOW bit masking for TCO1_CNT register values
231 * helps to avoid possible NMI_NOW bit inversions on
232 * following write operation.
233 */
234 val = inw(TCO1_CNT(p)) & ~NMI_NOW;
235 if (set)
236 val |= BIT(0);
237 else
238 val &= ~BIT(0);
239 outw(val, TCO1_CNT(p));
240 newval = inw(TCO1_CNT(p)) & ~NMI_NOW;
241
242 /* make sure the update is successful */
243 return val != newval ? -EIO : 0;
244}
245
246static int update_no_reboot_bit_pmc(void *priv, bool set)
247{
248 struct intel_pmc_dev *pmc = priv;
249 u32 bits = PMC_CFG_NO_REBOOT_EN;
250 u32 value = set ? bits : 0;
251
252 return intel_pmc_gcr_update(pmc, PMC_GCR_PMC_CFG_REG, bits, value);
253}
254
255static void iTCO_wdt_no_reboot_bit_setup(struct iTCO_wdt_private *p,
256 struct platform_device *pdev,
257 struct itco_wdt_platform_data *pdata)
258{
259 if (pdata->no_reboot_use_pmc) {
260 struct intel_pmc_dev *pmc = dev_get_drvdata(pdev->dev.parent);
261
262 p->update_no_reboot_bit = update_no_reboot_bit_pmc;
263 p->no_reboot_priv = pmc;
264 return;
265 }
266
267 if (p->iTCO_version >= 6)
268 p->update_no_reboot_bit = update_no_reboot_bit_cnt;
269 else if (p->iTCO_version >= 2)
270 p->update_no_reboot_bit = update_no_reboot_bit_mem;
271 else if (p->iTCO_version == 1)
272 p->update_no_reboot_bit = update_no_reboot_bit_pci;
273 else
274 p->update_no_reboot_bit = update_no_reboot_bit_def;
275
276 p->no_reboot_priv = p;
277}
278
279static int iTCO_wdt_start(struct watchdog_device *wd_dev)
280{
281 struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
282 unsigned int val;
283
284 /* disable chipset's NO_REBOOT bit */
285 if (p->update_no_reboot_bit(p->no_reboot_priv, false)) {
286 dev_err(wd_dev->parent, "failed to reset NO_REBOOT flag, reboot disabled by hardware/BIOS\n");
287 return -EIO;
288 }
289
290 /* Force the timer to its reload value by writing to the TCO_RLD
291 register */
292 if (p->iTCO_version >= 2)
293 outw(0x01, TCO_RLD(p));
294 else if (p->iTCO_version == 1)
295 outb(0x01, TCO_RLD(p));
296
297 /* Bit 11: TCO Timer Halt -> 0 = The TCO timer is enabled to count */
298 val = inw(TCO1_CNT(p));
299 val &= 0xf7ff;
300 outw(val, TCO1_CNT(p));
301 val = inw(TCO1_CNT(p));
302
303 if (val & 0x0800)
304 return -1;
305 return 0;
306}
307
308static int iTCO_wdt_stop(struct watchdog_device *wd_dev)
309{
310 struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
311 unsigned int val;
312
313 /* Bit 11: TCO Timer Halt -> 1 = The TCO timer is disabled */
314 val = inw(TCO1_CNT(p));
315 val |= 0x0800;
316 outw(val, TCO1_CNT(p));
317 val = inw(TCO1_CNT(p));
318
319 /* Set the NO_REBOOT bit to prevent later reboots, just for sure */
320 p->update_no_reboot_bit(p->no_reboot_priv, true);
321
322 if ((val & 0x0800) == 0)
323 return -1;
324 return 0;
325}
326
327static int iTCO_wdt_ping(struct watchdog_device *wd_dev)
328{
329 struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
330
331 /* Reload the timer by writing to the TCO Timer Counter register */
332 if (p->iTCO_version >= 2) {
333 outw(0x01, TCO_RLD(p));
334 } else if (p->iTCO_version == 1) {
335 /* Reset the timeout status bit so that the timer
336 * needs to count down twice again before rebooting */
337 outw(0x0008, TCO1_STS(p)); /* write 1 to clear bit */
338
339 outb(0x01, TCO_RLD(p));
340 }
341
342 return 0;
343}
344
345static int iTCO_wdt_set_timeout(struct watchdog_device *wd_dev, unsigned int t)
346{
347 struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
348 unsigned int val16;
349 unsigned char val8;
350 unsigned int tmrval;
351
352 tmrval = seconds_to_ticks(p, t);
353
354 /* For TCO v1 the timer counts down twice before rebooting */
355 if (p->iTCO_version == 1)
356 tmrval /= 2;
357
358 /* from the specs: */
359 /* "Values of 0h-3h are ignored and should not be attempted" */
360 if (tmrval < 0x04)
361 return -EINVAL;
362 if ((p->iTCO_version >= 2 && tmrval > 0x3ff) ||
363 (p->iTCO_version == 1 && tmrval > 0x03f))
364 return -EINVAL;
365
366 /* Write new heartbeat to watchdog */
367 if (p->iTCO_version >= 2) {
368 val16 = inw(TCOv2_TMR(p));
369 val16 &= 0xfc00;
370 val16 |= tmrval;
371 outw(val16, TCOv2_TMR(p));
372 val16 = inw(TCOv2_TMR(p));
373
374 if ((val16 & 0x3ff) != tmrval)
375 return -EINVAL;
376 } else if (p->iTCO_version == 1) {
377 val8 = inb(TCOv1_TMR(p));
378 val8 &= 0xc0;
379 val8 |= (tmrval & 0xff);
380 outb(val8, TCOv1_TMR(p));
381 val8 = inb(TCOv1_TMR(p));
382
383 if ((val8 & 0x3f) != tmrval)
384 return -EINVAL;
385 }
386
387 wd_dev->timeout = t;
388 return 0;
389}
390
391static unsigned int iTCO_wdt_get_timeleft(struct watchdog_device *wd_dev)
392{
393 struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
394 unsigned int val16;
395 unsigned char val8;
396 unsigned int time_left = 0;
397
398 /* read the TCO Timer */
399 if (p->iTCO_version >= 2) {
400 val16 = inw(TCO_RLD(p));
401 val16 &= 0x3ff;
402
403 time_left = ticks_to_seconds(p, val16);
404 } else if (p->iTCO_version == 1) {
405 val8 = inb(TCO_RLD(p));
406 val8 &= 0x3f;
407 if (!(inw(TCO1_STS(p)) & 0x0008))
408 val8 += (inb(TCOv1_TMR(p)) & 0x3f);
409
410 time_left = ticks_to_seconds(p, val8);
411 }
412 return time_left;
413}
414
415/* Returns true if the watchdog was running */
416static bool iTCO_wdt_set_running(struct iTCO_wdt_private *p)
417{
418 u16 val;
419
420 /* Bit 11: TCO Timer Halt -> 0 = The TCO timer is enabled */
421 val = inw(TCO1_CNT(p));
422 if (!(val & BIT(11))) {
423 set_bit(WDOG_HW_RUNNING, &p->wddev.status);
424 return true;
425 }
426 return false;
427}
428
429/*
430 * Kernel Interfaces
431 */
432
433static struct watchdog_info ident = {
434 .options = WDIOF_SETTIMEOUT |
435 WDIOF_KEEPALIVEPING |
436 WDIOF_MAGICCLOSE,
437 .identity = DRV_NAME,
438};
439
440static const struct watchdog_ops iTCO_wdt_ops = {
441 .owner = THIS_MODULE,
442 .start = iTCO_wdt_start,
443 .stop = iTCO_wdt_stop,
444 .ping = iTCO_wdt_ping,
445 .set_timeout = iTCO_wdt_set_timeout,
446 .get_timeleft = iTCO_wdt_get_timeleft,
447};
448
449/*
450 * Init & exit routines
451 */
452
453static int iTCO_wdt_probe(struct platform_device *pdev)
454{
455 struct device *dev = &pdev->dev;
456 struct itco_wdt_platform_data *pdata = dev_get_platdata(dev);
457 struct iTCO_wdt_private *p;
458 unsigned long val32;
459 int ret;
460
461 if (!pdata)
462 return -ENODEV;
463
464 p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
465 if (!p)
466 return -ENOMEM;
467
468 p->tco_res = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_IO_TCO);
469 if (!p->tco_res)
470 return -ENODEV;
471
472 p->iTCO_version = pdata->version;
473 p->pci_dev = to_pci_dev(dev->parent);
474
475 p->smi_res = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_IO_SMI);
476 if (p->smi_res) {
477 /* The TCO logic uses the TCO_EN bit in the SMI_EN register */
478 if (!devm_request_region(dev, p->smi_res->start,
479 resource_size(p->smi_res),
480 pdev->name)) {
481 dev_err(dev, "I/O address 0x%04llx already in use, device disabled\n",
482 (u64)SMI_EN(p));
483 return -EBUSY;
484 }
485 } else if (turn_SMI_watchdog_clear_off >= p->iTCO_version) {
486 dev_err(dev, "SMI I/O resource is missing\n");
487 return -ENODEV;
488 }
489
490 iTCO_wdt_no_reboot_bit_setup(p, pdev, pdata);
491
492 /*
493 * Get the Memory-Mapped GCS or PMC register, we need it for the
494 * NO_REBOOT flag (TCO v2 and v3).
495 */
496 if (p->iTCO_version >= 2 && p->iTCO_version < 6 &&
497 !pdata->no_reboot_use_pmc) {
498 p->gcs_pmc = devm_platform_ioremap_resource(pdev, ICH_RES_MEM_GCS_PMC);
499 if (IS_ERR(p->gcs_pmc))
500 return PTR_ERR(p->gcs_pmc);
501 }
502
503 /* Check chipset's NO_REBOOT bit */
504 if (p->update_no_reboot_bit(p->no_reboot_priv, false)) {
505 dev_info(dev, "unable to reset NO_REBOOT flag, device disabled by hardware/BIOS\n");
506 return -ENODEV; /* Cannot reset NO_REBOOT bit */
507 }
508
509 if (turn_SMI_watchdog_clear_off >= p->iTCO_version) {
510 /*
511 * Bit 13: TCO_EN -> 0
512 * Disables TCO logic generating an SMI#
513 */
514 val32 = inl(SMI_EN(p));
515 val32 &= 0xffffdfff; /* Turn off SMI clearing watchdog */
516 outl(val32, SMI_EN(p));
517 }
518
519 if (!devm_request_region(dev, p->tco_res->start,
520 resource_size(p->tco_res),
521 pdev->name)) {
522 dev_err(dev, "I/O address 0x%04llx already in use, device disabled\n",
523 (u64)TCOBASE(p));
524 return -EBUSY;
525 }
526
527 dev_info(dev, "Found a %s TCO device (Version=%d, TCOBASE=0x%04llx)\n",
528 pdata->name, pdata->version, (u64)TCOBASE(p));
529
530 /* Clear out the (probably old) status */
531 switch (p->iTCO_version) {
532 case 6:
533 case 5:
534 case 4:
535 outw(0x0008, TCO1_STS(p)); /* Clear the Time Out Status bit */
536 outw(0x0002, TCO2_STS(p)); /* Clear SECOND_TO_STS bit */
537 break;
538 case 3:
539 outl(0x20008, TCO1_STS(p));
540 break;
541 case 2:
542 case 1:
543 default:
544 outw(0x0008, TCO1_STS(p)); /* Clear the Time Out Status bit */
545 outw(0x0002, TCO2_STS(p)); /* Clear SECOND_TO_STS bit */
546 outw(0x0004, TCO2_STS(p)); /* Clear BOOT_STS bit */
547 break;
548 }
549
550 ident.firmware_version = p->iTCO_version;
551 p->wddev.info = &ident;
552 p->wddev.ops = &iTCO_wdt_ops;
553 p->wddev.bootstatus = 0;
554 p->wddev.timeout = WATCHDOG_TIMEOUT;
555 watchdog_set_nowayout(&p->wddev, nowayout);
556 p->wddev.parent = dev;
557
558 watchdog_set_drvdata(&p->wddev, p);
559 platform_set_drvdata(pdev, p);
560
561 if (!iTCO_wdt_set_running(p)) {
562 /*
563 * If the watchdog was not running set NO_REBOOT now to
564 * prevent later reboots.
565 */
566 p->update_no_reboot_bit(p->no_reboot_priv, true);
567 }
568
569 /* Check that the heartbeat value is within it's range;
570 if not reset to the default */
571 if (iTCO_wdt_set_timeout(&p->wddev, heartbeat)) {
572 ret = iTCO_wdt_set_timeout(&p->wddev, WATCHDOG_TIMEOUT);
573 if (ret != 0) {
574 dev_err(dev, "Failed to set watchdog timeout (%d)\n", WATCHDOG_TIMEOUT);
575 return ret;
576 }
577 dev_info(dev, "timeout value out of range, using %d\n",
578 WATCHDOG_TIMEOUT);
579 heartbeat = WATCHDOG_TIMEOUT;
580 }
581
582 watchdog_stop_on_reboot(&p->wddev);
583 watchdog_stop_on_unregister(&p->wddev);
584 ret = devm_watchdog_register_device(dev, &p->wddev);
585 if (ret != 0)
586 return ret;
587
588 dev_info(dev, "initialized. heartbeat=%d sec (nowayout=%d)\n",
589 heartbeat, nowayout);
590
591 return 0;
592}
593
594/*
595 * Suspend-to-idle requires this, because it stops the ticks and timekeeping, so
596 * the watchdog cannot be pinged while in that state. In ACPI sleep states the
597 * watchdog is stopped by the platform firmware.
598 */
599
600#ifdef CONFIG_ACPI
601static inline bool __maybe_unused need_suspend(void)
602{
603 return acpi_target_system_state() == ACPI_STATE_S0;
604}
605#else
606static inline bool __maybe_unused need_suspend(void) { return true; }
607#endif
608
609static int __maybe_unused iTCO_wdt_suspend_noirq(struct device *dev)
610{
611 struct iTCO_wdt_private *p = dev_get_drvdata(dev);
612 int ret = 0;
613
614 p->suspended = false;
615 if (watchdog_active(&p->wddev) && need_suspend()) {
616 ret = iTCO_wdt_stop(&p->wddev);
617 if (!ret)
618 p->suspended = true;
619 }
620 return ret;
621}
622
623static int __maybe_unused iTCO_wdt_resume_noirq(struct device *dev)
624{
625 struct iTCO_wdt_private *p = dev_get_drvdata(dev);
626
627 if (p->suspended)
628 iTCO_wdt_start(&p->wddev);
629
630 return 0;
631}
632
633static const struct dev_pm_ops iTCO_wdt_pm = {
634 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(iTCO_wdt_suspend_noirq,
635 iTCO_wdt_resume_noirq)
636};
637
638static struct platform_driver iTCO_wdt_driver = {
639 .probe = iTCO_wdt_probe,
640 .driver = {
641 .name = DRV_NAME,
642 .pm = &iTCO_wdt_pm,
643 },
644};
645
646module_platform_driver(iTCO_wdt_driver);
647
648MODULE_AUTHOR("Wim Van Sebroeck <[email protected]>");
649MODULE_DESCRIPTION("Intel TCO WatchDog Timer Driver");
650MODULE_VERSION(DRV_VERSION);
651MODULE_LICENSE("GPL");
652MODULE_ALIAS("platform:" DRV_NAME);