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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Watchdog driver for S32G SoC
4 *
5 * Copyright 2017-2019, 2021-2025 NXP.
6 *
7 */
8#include <linux/clk.h>
9#include <linux/debugfs.h>
10#include <linux/io.h>
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/of.h>
15#include <linux/platform_device.h>
16#include <linux/watchdog.h>
17
18#define DRIVER_NAME "s32g-swt"
19
20#define S32G_SWT_CR(__base) ((__base) + 0x00) /* Control Register offset */
21#define S32G_SWT_CR_SM (BIT(9) | BIT(10)) /* -> Service Mode */
22#define S32G_SWT_CR_STP BIT(2) /* -> Stop Mode Control */
23#define S32G_SWT_CR_FRZ BIT(1) /* -> Debug Mode Control */
24#define S32G_SWT_CR_WEN BIT(0) /* -> Watchdog Enable */
25
26#define S32G_SWT_TO(__base) ((__base) + 0x08) /* Timeout Register offset */
27
28#define S32G_SWT_SR(__base) ((__base) + 0x10) /* Service Register offset */
29#define S32G_WDT_SEQ1 0xA602 /* -> service sequence number 1 */
30#define S32G_WDT_SEQ2 0xB480 /* -> service sequence number 2 */
31
32#define S32G_SWT_CO(__base) ((__base) + 0x14) /* Counter output register */
33
34#define S32G_WDT_DEFAULT_TIMEOUT 30
35
36struct s32g_wdt_device {
37 int rate;
38 void __iomem *base;
39 struct watchdog_device wdog;
40};
41
42static bool nowayout = WATCHDOG_NOWAYOUT;
43module_param(nowayout, bool, 0);
44MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
45 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
46
47static unsigned int timeout_param = S32G_WDT_DEFAULT_TIMEOUT;
48module_param(timeout_param, uint, 0);
49MODULE_PARM_DESC(timeout_param, "Watchdog timeout in seconds (default="
50 __MODULE_STRING(S32G_WDT_DEFAULT_TIMEOUT) ")");
51
52static bool early_enable;
53module_param(early_enable, bool, 0);
54MODULE_PARM_DESC(early_enable,
55 "Watchdog is started on module insertion (default=false)");
56
57static const struct watchdog_info s32g_wdt_info = {
58 .identity = "s32g watchdog",
59 .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE,
60};
61
62static struct s32g_wdt_device *wdd_to_s32g_wdt(struct watchdog_device *wdd)
63{
64 return container_of(wdd, struct s32g_wdt_device, wdog);
65}
66
67static unsigned int wdog_sec_to_count(struct s32g_wdt_device *wdev, unsigned int timeout)
68{
69 return wdev->rate * timeout;
70}
71
72static int s32g_wdt_ping(struct watchdog_device *wdog)
73{
74 struct s32g_wdt_device *wdev = wdd_to_s32g_wdt(wdog);
75
76 writel(S32G_WDT_SEQ1, S32G_SWT_SR(wdev->base));
77 writel(S32G_WDT_SEQ2, S32G_SWT_SR(wdev->base));
78
79 return 0;
80}
81
82static int s32g_wdt_start(struct watchdog_device *wdog)
83{
84 struct s32g_wdt_device *wdev = wdd_to_s32g_wdt(wdog);
85 unsigned long val;
86
87 val = readl(S32G_SWT_CR(wdev->base));
88
89 val |= S32G_SWT_CR_WEN;
90
91 writel(val, S32G_SWT_CR(wdev->base));
92
93 return 0;
94}
95
96static int s32g_wdt_stop(struct watchdog_device *wdog)
97{
98 struct s32g_wdt_device *wdev = wdd_to_s32g_wdt(wdog);
99 unsigned long val;
100
101 val = readl(S32G_SWT_CR(wdev->base));
102
103 val &= ~S32G_SWT_CR_WEN;
104
105 writel(val, S32G_SWT_CR(wdev->base));
106
107 return 0;
108}
109
110static int s32g_wdt_set_timeout(struct watchdog_device *wdog, unsigned int timeout)
111{
112 struct s32g_wdt_device *wdev = wdd_to_s32g_wdt(wdog);
113
114 writel(wdog_sec_to_count(wdev, timeout), S32G_SWT_TO(wdev->base));
115
116 wdog->timeout = timeout;
117
118 /*
119 * Conforming to the documentation, the timeout counter is
120 * loaded when servicing is operated (aka ping) or when the
121 * counter is enabled. In case the watchdog is already started
122 * it must be stopped and started again to update the timeout
123 * register or a ping can be sent to refresh the counter. Here
124 * we choose to send a ping to the watchdog which is harmless
125 * if the watchdog is stopped.
126 */
127 return s32g_wdt_ping(wdog);
128}
129
130static unsigned int s32g_wdt_get_timeleft(struct watchdog_device *wdog)
131{
132 struct s32g_wdt_device *wdev = wdd_to_s32g_wdt(wdog);
133 unsigned long counter;
134 bool is_running;
135
136 /*
137 * The counter output can be read only if the SWT is
138 * disabled. Given the latency between the internal counter
139 * and the counter output update, there can be very small
140 * difference. However, we can accept this matter of fact
141 * given the resolution is a second based unit for the output.
142 */
143 is_running = watchdog_hw_running(wdog);
144
145 if (is_running)
146 s32g_wdt_stop(wdog);
147
148 counter = readl(S32G_SWT_CO(wdev->base));
149
150 if (is_running)
151 s32g_wdt_start(wdog);
152
153 return counter / wdev->rate;
154}
155
156static const struct watchdog_ops s32g_wdt_ops = {
157 .owner = THIS_MODULE,
158 .start = s32g_wdt_start,
159 .stop = s32g_wdt_stop,
160 .ping = s32g_wdt_ping,
161 .set_timeout = s32g_wdt_set_timeout,
162 .get_timeleft = s32g_wdt_get_timeleft,
163};
164
165static void s32g_wdt_init(struct s32g_wdt_device *wdev)
166{
167 unsigned long val;
168
169 /* Set the watchdog's Time-Out value */
170 val = wdog_sec_to_count(wdev, wdev->wdog.timeout);
171
172 writel(val, S32G_SWT_TO(wdev->base));
173
174 /*
175 * Get the control register content. We are at init time, the
176 * watchdog should not be started.
177 */
178 val = readl(S32G_SWT_CR(wdev->base));
179
180 /*
181 * We want to allow the watchdog timer to be stopped when
182 * device enters debug mode.
183 */
184 val |= S32G_SWT_CR_FRZ;
185
186 /*
187 * However, when the CPU is in WFI or suspend mode, the
188 * watchdog must continue. The documentation refers it as the
189 * stopped mode.
190 */
191 val &= ~S32G_SWT_CR_STP;
192
193 /*
194 * Use Fixed Service Sequence to ping the watchdog which is
195 * 0x00 configuration value for the service mode. It should be
196 * already set because it is the default value but we reset it
197 * in case.
198 */
199 val &= ~S32G_SWT_CR_SM;
200
201 writel(val, S32G_SWT_CR(wdev->base));
202
203 /*
204 * When the 'early_enable' option is set, we start the
205 * watchdog from the kernel.
206 */
207 if (early_enable) {
208 s32g_wdt_start(&wdev->wdog);
209 set_bit(WDOG_HW_RUNNING, &wdev->wdog.status);
210 }
211}
212
213static int s32g_wdt_probe(struct platform_device *pdev)
214{
215 struct device *dev = &pdev->dev;
216 struct resource *res;
217 struct clk *clk;
218 struct s32g_wdt_device *wdev;
219 struct watchdog_device *wdog;
220 int ret;
221
222 wdev = devm_kzalloc(dev, sizeof(*wdev), GFP_KERNEL);
223 if (!wdev)
224 return -ENOMEM;
225
226 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
227 wdev->base = devm_ioremap_resource(dev, res);
228 if (IS_ERR(wdev->base))
229 return dev_err_probe(&pdev->dev, PTR_ERR(wdev->base), "Can not get resource\n");
230
231 clk = devm_clk_get_enabled(dev, "counter");
232 if (IS_ERR(clk))
233 return dev_err_probe(dev, PTR_ERR(clk), "Can't get Watchdog clock\n");
234
235 wdev->rate = clk_get_rate(clk);
236 if (!wdev->rate) {
237 dev_err(dev, "Input clock rate is not valid\n");
238 return -EINVAL;
239 }
240
241 wdog = &wdev->wdog;
242 wdog->info = &s32g_wdt_info;
243 wdog->ops = &s32g_wdt_ops;
244
245 /*
246 * The code converts the timeout into a counter a value, if
247 * the value is less than 0x100, then it is clamped by the SWT
248 * module, so it is safe to specify a zero value as the
249 * minimum timeout.
250 */
251 wdog->min_timeout = 0;
252
253 /*
254 * The counter register is a 32 bits long, so the maximum
255 * counter value is UINT_MAX and the timeout in second is the
256 * value divided by the rate.
257 *
258 * For instance, a rate of 51MHz lead to 84 seconds maximum
259 * timeout.
260 */
261 wdog->max_timeout = UINT_MAX / wdev->rate;
262
263 /*
264 * The module param and the DT 'timeout-sec' property will
265 * override the default value if they are specified.
266 */
267 ret = watchdog_init_timeout(wdog, timeout_param, dev);
268 if (ret)
269 return ret;
270
271 /*
272 * As soon as the watchdog is started, there is no way to stop
273 * it if the 'nowayout' option is set at boot time
274 */
275 watchdog_set_nowayout(wdog, nowayout);
276
277 /*
278 * The devm_ version of the watchdog_register_device()
279 * function will call watchdog_unregister_device() when the
280 * device is removed.
281 */
282 watchdog_stop_on_unregister(wdog);
283
284 s32g_wdt_init(wdev);
285
286 ret = devm_watchdog_register_device(dev, wdog);
287 if (ret)
288 return dev_err_probe(dev, ret, "Cannot register watchdog device\n");
289
290 dev_info(dev, "S32G Watchdog Timer Registered, timeout=%ds, nowayout=%d, early_enable=%d\n",
291 wdog->timeout, nowayout, early_enable);
292
293 return 0;
294}
295
296static const struct of_device_id s32g_wdt_dt_ids[] = {
297 { .compatible = "nxp,s32g2-swt" },
298 { /* sentinel */ }
299};
300MODULE_DEVICE_TABLE(of, s32g_wdt_dt_ids);
301
302static struct platform_driver s32g_wdt_driver = {
303 .probe = s32g_wdt_probe,
304 .driver = {
305 .name = DRIVER_NAME,
306 .of_match_table = s32g_wdt_dt_ids,
307 },
308};
309
310module_platform_driver(s32g_wdt_driver);
311
312MODULE_AUTHOR("Daniel Lezcano <[email protected]>");
313MODULE_DESCRIPTION("Watchdog driver for S32G SoC");
314MODULE_LICENSE("GPL");