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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Window watchdog device driver for Xilinx Versal WWDT
4 *
5 * Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc.
6 */
7
8#include <linux/clk.h>
9#include <linux/interrupt.h>
10#include <linux/io.h>
11#include <linux/ioport.h>
12#include <linux/math64.h>
13#include <linux/module.h>
14#include <linux/platform_device.h>
15#include <linux/watchdog.h>
16
17/* Max timeout is calculated at 100MHz source clock */
18#define XWWDT_DEFAULT_TIMEOUT 42
19#define XWWDT_MIN_TIMEOUT 1
20
21/* Register offsets for the WWDT device */
22#define XWWDT_MWR_OFFSET 0x00
23#define XWWDT_ESR_OFFSET 0x04
24#define XWWDT_FCR_OFFSET 0x08
25#define XWWDT_FWR_OFFSET 0x0c
26#define XWWDT_SWR_OFFSET 0x10
27
28/* Master Write Control Register Masks */
29#define XWWDT_MWR_MASK BIT(0)
30
31/* Enable and Status Register Masks */
32#define XWWDT_ESR_WINT_MASK BIT(16)
33#define XWWDT_ESR_WSW_MASK BIT(8)
34#define XWWDT_ESR_WEN_MASK BIT(0)
35
36#define XWWDT_CLOSE_WINDOW_PERCENT 50
37
38/* Maximum count value of each 32 bit window */
39#define XWWDT_MAX_COUNT_WINDOW GENMASK(31, 0)
40
41/* Maximum count value of closed and open window combined */
42#define XWWDT_MAX_COUNT_WINDOW_COMBINED GENMASK_ULL(32, 1)
43
44static int wwdt_timeout;
45static int closed_window_percent;
46
47module_param(wwdt_timeout, int, 0);
48MODULE_PARM_DESC(wwdt_timeout,
49 "Watchdog time in seconds. (default="
50 __MODULE_STRING(XWWDT_DEFAULT_TIMEOUT) ")");
51module_param(closed_window_percent, int, 0);
52MODULE_PARM_DESC(closed_window_percent,
53 "Watchdog closed window percentage. (default="
54 __MODULE_STRING(XWWDT_CLOSE_WINDOW_PERCENT) ")");
55/**
56 * struct xwwdt_device - Watchdog device structure
57 * @base: base io address of WDT device
58 * @spinlock: spinlock for IO register access
59 * @xilinx_wwdt_wdd: watchdog device structure
60 * @freq: source clock frequency of WWDT
61 * @close_percent: Closed window percent
62 * @closed_timeout: Closed window timeout in ticks
63 * @open_timeout: Open window timeout in ticks
64 */
65struct xwwdt_device {
66 void __iomem *base;
67 spinlock_t spinlock; /* spinlock for register handling */
68 struct watchdog_device xilinx_wwdt_wdd;
69 unsigned long freq;
70 u32 close_percent;
71 u64 closed_timeout;
72 u64 open_timeout;
73};
74
75static int xilinx_wwdt_start(struct watchdog_device *wdd)
76{
77 struct xwwdt_device *xdev = watchdog_get_drvdata(wdd);
78 struct watchdog_device *xilinx_wwdt_wdd = &xdev->xilinx_wwdt_wdd;
79 u32 control_status_reg;
80
81 spin_lock(&xdev->spinlock);
82
83 iowrite32(XWWDT_MWR_MASK, xdev->base + XWWDT_MWR_OFFSET);
84 iowrite32(~(u32)XWWDT_ESR_WEN_MASK, xdev->base + XWWDT_ESR_OFFSET);
85 iowrite32((u32)xdev->closed_timeout, xdev->base + XWWDT_FWR_OFFSET);
86 iowrite32((u32)xdev->open_timeout, xdev->base + XWWDT_SWR_OFFSET);
87
88 /* Enable the window watchdog timer */
89 control_status_reg = ioread32(xdev->base + XWWDT_ESR_OFFSET);
90 control_status_reg |= XWWDT_ESR_WEN_MASK;
91 iowrite32(control_status_reg, xdev->base + XWWDT_ESR_OFFSET);
92
93 spin_unlock(&xdev->spinlock);
94
95 dev_dbg(xilinx_wwdt_wdd->parent, "Watchdog Started!\n");
96
97 return 0;
98}
99
100static int xilinx_wwdt_keepalive(struct watchdog_device *wdd)
101{
102 struct xwwdt_device *xdev = watchdog_get_drvdata(wdd);
103 u32 control_status_reg;
104
105 spin_lock(&xdev->spinlock);
106
107 /* Enable write access control bit for the window watchdog */
108 iowrite32(XWWDT_MWR_MASK, xdev->base + XWWDT_MWR_OFFSET);
109
110 /* Trigger restart kick to watchdog */
111 control_status_reg = ioread32(xdev->base + XWWDT_ESR_OFFSET);
112 control_status_reg |= XWWDT_ESR_WSW_MASK;
113 iowrite32(control_status_reg, xdev->base + XWWDT_ESR_OFFSET);
114
115 spin_unlock(&xdev->spinlock);
116
117 return 0;
118}
119
120static const struct watchdog_info xilinx_wwdt_ident = {
121 .options = WDIOF_KEEPALIVEPING |
122 WDIOF_SETTIMEOUT,
123 .firmware_version = 1,
124 .identity = "xlnx_window watchdog",
125};
126
127static const struct watchdog_ops xilinx_wwdt_ops = {
128 .owner = THIS_MODULE,
129 .start = xilinx_wwdt_start,
130 .ping = xilinx_wwdt_keepalive,
131};
132
133static int xwwdt_probe(struct platform_device *pdev)
134{
135 struct watchdog_device *xilinx_wwdt_wdd;
136 struct device *dev = &pdev->dev;
137 struct xwwdt_device *xdev;
138 u64 max_per_window_ms;
139 u64 min_per_window_ms;
140 u64 timeout_count;
141 struct clk *clk;
142 u32 timeout_ms;
143 u64 ms_count;
144 int ret;
145
146 xdev = devm_kzalloc(dev, sizeof(*xdev), GFP_KERNEL);
147 if (!xdev)
148 return -ENOMEM;
149
150 xilinx_wwdt_wdd = &xdev->xilinx_wwdt_wdd;
151 xilinx_wwdt_wdd->info = &xilinx_wwdt_ident;
152 xilinx_wwdt_wdd->ops = &xilinx_wwdt_ops;
153 xilinx_wwdt_wdd->parent = dev;
154
155 xdev->base = devm_platform_ioremap_resource(pdev, 0);
156 if (IS_ERR(xdev->base))
157 return PTR_ERR(xdev->base);
158
159 clk = devm_clk_get_enabled(dev, NULL);
160 if (IS_ERR(clk))
161 return PTR_ERR(clk);
162
163 xdev->freq = clk_get_rate(clk);
164 if (xdev->freq < 1000000)
165 return -EINVAL;
166
167 xilinx_wwdt_wdd->min_timeout = XWWDT_MIN_TIMEOUT;
168 xilinx_wwdt_wdd->timeout = XWWDT_DEFAULT_TIMEOUT;
169 xilinx_wwdt_wdd->max_hw_heartbeat_ms =
170 div64_u64(XWWDT_MAX_COUNT_WINDOW_COMBINED, xdev->freq) * 1000;
171
172 if (closed_window_percent == 0 || closed_window_percent >= 100)
173 xdev->close_percent = XWWDT_CLOSE_WINDOW_PERCENT;
174 else
175 xdev->close_percent = closed_window_percent;
176
177 watchdog_init_timeout(xilinx_wwdt_wdd, wwdt_timeout, &pdev->dev);
178
179 /* Calculate ticks for 1 milli-second */
180 ms_count = div_u64(xdev->freq, 1000);
181 timeout_ms = xilinx_wwdt_wdd->timeout * 1000;
182 timeout_count = timeout_ms * ms_count;
183
184 if (timeout_ms > xilinx_wwdt_wdd->max_hw_heartbeat_ms) {
185 /*
186 * To avoid ping restrictions until the minimum hardware heartbeat,
187 * we will solely rely on the open window and
188 * adjust the minimum hardware heartbeat to 0.
189 */
190 xdev->closed_timeout = 0;
191 xdev->open_timeout = XWWDT_MAX_COUNT_WINDOW;
192 xilinx_wwdt_wdd->min_hw_heartbeat_ms = 0;
193 xilinx_wwdt_wdd->max_hw_heartbeat_ms = xilinx_wwdt_wdd->max_hw_heartbeat_ms / 2;
194 } else {
195 xdev->closed_timeout = div64_u64(timeout_count * xdev->close_percent, 100);
196 xilinx_wwdt_wdd->min_hw_heartbeat_ms =
197 div64_u64(timeout_ms * xdev->close_percent, 100);
198
199 if (timeout_ms > xilinx_wwdt_wdd->max_hw_heartbeat_ms / 2) {
200 max_per_window_ms = xilinx_wwdt_wdd->max_hw_heartbeat_ms / 2;
201 min_per_window_ms = timeout_ms - max_per_window_ms;
202
203 if (xilinx_wwdt_wdd->min_hw_heartbeat_ms > max_per_window_ms) {
204 dev_info(xilinx_wwdt_wdd->parent,
205 "Closed window cannot be set to %d%%. Using maximum supported value.\n",
206 xdev->close_percent);
207 xdev->closed_timeout = max_per_window_ms * ms_count;
208 xilinx_wwdt_wdd->min_hw_heartbeat_ms = max_per_window_ms;
209 } else if (xilinx_wwdt_wdd->min_hw_heartbeat_ms < min_per_window_ms) {
210 dev_info(xilinx_wwdt_wdd->parent,
211 "Closed window cannot be set to %d%%. Using minimum supported value.\n",
212 xdev->close_percent);
213 xdev->closed_timeout = min_per_window_ms * ms_count;
214 xilinx_wwdt_wdd->min_hw_heartbeat_ms = min_per_window_ms;
215 }
216 }
217 xdev->open_timeout = timeout_count - xdev->closed_timeout;
218 }
219
220 spin_lock_init(&xdev->spinlock);
221 watchdog_set_drvdata(xilinx_wwdt_wdd, xdev);
222 watchdog_set_nowayout(xilinx_wwdt_wdd, 1);
223
224 ret = devm_watchdog_register_device(dev, xilinx_wwdt_wdd);
225 if (ret)
226 return ret;
227
228 dev_info(dev, "Xilinx window watchdog Timer with timeout %ds\n",
229 xilinx_wwdt_wdd->timeout);
230
231 return 0;
232}
233
234static const struct of_device_id xwwdt_of_match[] = {
235 { .compatible = "xlnx,versal-wwdt", },
236 {},
237};
238MODULE_DEVICE_TABLE(of, xwwdt_of_match);
239
240static struct platform_driver xwwdt_driver = {
241 .probe = xwwdt_probe,
242 .driver = {
243 .name = "Xilinx window watchdog",
244 .of_match_table = xwwdt_of_match,
245 },
246};
247
248module_platform_driver(xwwdt_driver);
249
250MODULE_AUTHOR("Neeli Srinivas <[email protected]>");
251MODULE_DESCRIPTION("Xilinx window watchdog driver");
252MODULE_LICENSE("GPL");