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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2014-2026 NVIDIA Corporation
4 */
5
6#ifndef __SOC_TEGRA_MC_H__
7#define __SOC_TEGRA_MC_H__
8
9#include <linux/bits.h>
10#include <linux/debugfs.h>
11#include <linux/err.h>
12#include <linux/interconnect-provider.h>
13#include <linux/interrupt.h>
14#include <linux/irq.h>
15#include <linux/reset-controller.h>
16#include <linux/tegra-icc.h>
17#include <linux/types.h>
18
19struct clk;
20struct device;
21struct page;
22
23struct tegra_mc_timing {
24 unsigned long rate;
25
26 u32 *emem_data;
27};
28
29struct tegra_mc_client {
30 unsigned int id;
31 unsigned int bpmp_id;
32 enum tegra_icc_client_type type;
33 const char *name;
34 /*
35 * For Tegra210 and earlier, this is the SWGROUP ID used for IOVA translations in the
36 * Tegra SMMU, whereas on Tegra186 and later this is the ID used to override the ARM SMMU
37 * stream ID used for IOVA translations for the given memory client.
38 */
39 union {
40 unsigned int swgroup;
41 unsigned int sid;
42 };
43
44 unsigned int fifo_size;
45
46 struct {
47 /* Tegra SMMU enable (Tegra210 and earlier) */
48 struct {
49 unsigned int reg;
50 unsigned int bit;
51 } smmu;
52
53 /* latency allowance */
54 struct {
55 unsigned int reg;
56 unsigned int shift;
57 unsigned int mask;
58 unsigned int def;
59 } la;
60
61 /* stream ID overrides (Tegra186 and later) */
62 struct {
63 unsigned int override;
64 unsigned int security;
65 } sid;
66 } regs;
67};
68
69struct tegra_smmu_swgroup {
70 const char *name;
71 unsigned int swgroup;
72 unsigned int reg;
73};
74
75struct tegra_smmu_group_soc {
76 const char *name;
77 const unsigned int *swgroups;
78 unsigned int num_swgroups;
79};
80
81struct tegra_smmu_soc {
82 const struct tegra_mc_client *clients;
83 unsigned int num_clients;
84
85 const struct tegra_smmu_swgroup *swgroups;
86 unsigned int num_swgroups;
87
88 const struct tegra_smmu_group_soc *groups;
89 unsigned int num_groups;
90
91 bool supports_round_robin_arbitration;
92 bool supports_request_limit;
93
94 unsigned int num_tlb_lines;
95 unsigned int num_asids;
96};
97
98struct tegra_mc;
99struct tegra_smmu;
100
101#ifdef CONFIG_TEGRA_IOMMU_SMMU
102struct tegra_smmu *tegra_smmu_probe(struct device *dev,
103 const struct tegra_smmu_soc *soc,
104 struct tegra_mc *mc);
105void tegra_smmu_remove(struct tegra_smmu *smmu);
106#else
107static inline struct tegra_smmu *
108tegra_smmu_probe(struct device *dev, const struct tegra_smmu_soc *soc,
109 struct tegra_mc *mc)
110{
111 return NULL;
112}
113
114static inline void tegra_smmu_remove(struct tegra_smmu *smmu)
115{
116}
117#endif
118
119struct tegra_mc_reset {
120 const char *name;
121 unsigned long id;
122 unsigned int control;
123 unsigned int status;
124 unsigned int reset;
125 unsigned int bit;
126};
127
128struct tegra_mc_reset_ops {
129 int (*hotreset_assert)(struct tegra_mc *mc,
130 const struct tegra_mc_reset *rst);
131 int (*hotreset_deassert)(struct tegra_mc *mc,
132 const struct tegra_mc_reset *rst);
133 int (*block_dma)(struct tegra_mc *mc,
134 const struct tegra_mc_reset *rst);
135 bool (*dma_idling)(struct tegra_mc *mc,
136 const struct tegra_mc_reset *rst);
137 int (*unblock_dma)(struct tegra_mc *mc,
138 const struct tegra_mc_reset *rst);
139 int (*reset_status)(struct tegra_mc *mc,
140 const struct tegra_mc_reset *rst);
141};
142
143#define TEGRA_MC_ICC_TAG_DEFAULT 0
144#define TEGRA_MC_ICC_TAG_ISO BIT(0)
145
146struct tegra_mc_icc_ops {
147 int (*set)(struct icc_node *src, struct icc_node *dst);
148 int (*aggregate)(struct icc_node *node, u32 tag, u32 avg_bw,
149 u32 peak_bw, u32 *agg_avg, u32 *agg_peak);
150 struct icc_node* (*xlate)(const struct of_phandle_args *spec, void *data);
151 struct icc_node_data *(*xlate_extended)(const struct of_phandle_args *spec,
152 void *data);
153 int (*get_bw)(struct icc_node *node, u32 *avg, u32 *peak);
154};
155
156struct icc_node *tegra_mc_icc_xlate(const struct of_phandle_args *spec,
157 void *data);
158extern const struct tegra_mc_icc_ops tegra_mc_icc_ops;
159
160struct tegra_mc_ops {
161 /*
162 * @probe: Callback to set up SoC-specific bits of the memory controller. This is called
163 * after basic, common set up that is done by the SoC-agnostic bits.
164 */
165 int (*probe)(struct tegra_mc *mc);
166 void (*remove)(struct tegra_mc *mc);
167 void (*resume)(struct tegra_mc *mc);
168 int (*probe_device)(struct tegra_mc *mc, struct device *dev);
169};
170
171struct tegra_mc_regs {
172 unsigned int cfg_channel_enable;
173 unsigned int err_status;
174 unsigned int err_add;
175 unsigned int err_add_hi;
176 unsigned int err_vpr_status;
177 unsigned int err_vpr_add;
178 unsigned int err_sec_status;
179 unsigned int err_sec_add;
180 unsigned int err_mts_status;
181 unsigned int err_mts_add;
182 unsigned int err_gen_co_status;
183 unsigned int err_gen_co_add;
184 unsigned int err_route_status;
185 unsigned int err_route_add;
186};
187
188struct tegra_mc_intmask {
189 u32 reg;
190 u32 mask;
191};
192
193struct tegra_mc_soc {
194 const struct tegra_mc_client *clients;
195 unsigned int num_clients;
196
197 const unsigned long *emem_regs;
198 unsigned int num_emem_regs;
199
200 unsigned int num_address_bits;
201 unsigned int atom_size;
202
203 unsigned int num_carveouts;
204
205 u16 client_id_mask;
206 u8 num_channels;
207
208 const struct tegra_smmu_soc *smmu;
209
210 u32 ch_intmask;
211 u32 global_intstatus_channel_shift;
212 bool has_addr_hi_reg;
213
214 const struct tegra_mc_reset_ops *reset_ops;
215 const struct tegra_mc_reset *resets;
216 unsigned int num_resets;
217
218 const struct tegra_mc_icc_ops *icc_ops;
219 const struct tegra_mc_ops *ops;
220 const struct tegra_mc_regs *regs;
221
222 const irq_handler_t *handle_irq;
223 unsigned int num_interrupts;
224 unsigned int mc_addr_hi_mask;
225 unsigned int mc_err_status_type_mask;
226 const struct tegra_mc_intmask *intmasks;
227 unsigned int num_intmasks;
228};
229
230struct tegra_mc {
231 struct tegra_bpmp *bpmp;
232 struct device *dev;
233 struct tegra_smmu *smmu;
234 void __iomem *regs;
235 void __iomem *bcast_ch_regs;
236 void __iomem **ch_regs;
237 struct clk *clk;
238
239 const struct tegra_mc_soc *soc;
240 unsigned long tick;
241
242 struct tegra_mc_timing *timings;
243 unsigned int num_timings;
244 unsigned int num_channels;
245
246 bool bwmgr_mrq_supported;
247 struct reset_controller_dev reset;
248
249 struct icc_provider provider;
250
251 spinlock_t lock;
252
253 struct {
254 struct dentry *root;
255 } debugfs;
256};
257
258int tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate);
259unsigned int tegra_mc_get_emem_device_count(struct tegra_mc *mc);
260
261#ifdef CONFIG_TEGRA_MC
262struct tegra_mc *devm_tegra_memory_controller_get(struct device *dev);
263int tegra_mc_probe_device(struct tegra_mc *mc, struct device *dev);
264int tegra_mc_get_carveout_info(struct tegra_mc *mc, unsigned int id,
265 phys_addr_t *base, u64 *size);
266#else
267static inline struct tegra_mc *
268devm_tegra_memory_controller_get(struct device *dev)
269{
270 return ERR_PTR(-ENODEV);
271}
272
273static inline int
274tegra_mc_probe_device(struct tegra_mc *mc, struct device *dev)
275{
276 return -ENODEV;
277}
278
279static inline int
280tegra_mc_get_carveout_info(struct tegra_mc *mc, unsigned int id,
281 phys_addr_t *base, u64 *size)
282{
283 return -ENODEV;
284}
285#endif
286
287extern const struct tegra_mc_regs tegra20_mc_regs;
288
289#endif /* __SOC_TEGRA_MC_H__ */