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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * HD-audio core stuff
4 */
5
6#ifndef __SOUND_HDAUDIO_H
7#define __SOUND_HDAUDIO_H
8
9#include <linux/device.h>
10#include <linux/interrupt.h>
11#include <linux/io.h>
12#include <linux/io-64-nonatomic-lo-hi.h>
13#include <linux/iopoll.h>
14#include <linux/device-id/hda.h>
15#include <linux/pci.h>
16#include <linux/pm_runtime.h>
17#include <linux/timecounter.h>
18#include <sound/core.h>
19#include <sound/pcm.h>
20#include <sound/memalloc.h>
21#include <sound/hda_verbs.h>
22#include <drm/intel/i915_component.h>
23
24/* codec node id */
25typedef u16 hda_nid_t;
26
27struct hdac_bus;
28struct hdac_stream;
29struct hdac_device;
30struct hdac_driver;
31struct hdac_widget_tree;
32struct hda_device_id;
33
34/*
35 * exported bus type
36 */
37extern const struct bus_type snd_hda_bus_type;
38
39/*
40 * generic arrays
41 */
42struct snd_array {
43 unsigned int used;
44 unsigned int alloced;
45 unsigned int elem_size;
46 unsigned int alloc_align;
47 void *list;
48};
49
50/*
51 * HD-audio codec base device
52 */
53struct hdac_device {
54 struct device dev;
55 int type;
56 struct hdac_bus *bus;
57 unsigned int addr; /* codec address */
58 struct list_head list; /* list point for bus codec_list */
59
60 hda_nid_t afg; /* AFG node id */
61 hda_nid_t mfg; /* MFG node id */
62
63 /* ids */
64 unsigned int vendor_id;
65 unsigned int subsystem_id;
66 unsigned int revision_id;
67 unsigned int afg_function_id;
68 unsigned int mfg_function_id;
69 unsigned int afg_unsol:1;
70 unsigned int mfg_unsol:1;
71
72 unsigned int power_caps; /* FG power caps */
73
74 const char *vendor_name; /* codec vendor name */
75 const char *chip_name; /* codec chip name */
76
77 /* verb exec op override */
78 int (*exec_verb)(struct hdac_device *dev, unsigned int cmd,
79 unsigned int flags, unsigned int *res);
80
81 /* widgets */
82 unsigned int num_nodes;
83 hda_nid_t start_nid, end_nid;
84
85 /* misc flags */
86 atomic_t in_pm; /* suspend/resume being performed */
87
88 /* sysfs */
89 struct mutex widget_lock;
90 struct hdac_widget_tree *widgets;
91
92 /* regmap */
93 struct regmap *regmap;
94 struct mutex regmap_lock;
95 struct snd_array vendor_verbs;
96 bool lazy_cache:1; /* don't wake up for writes */
97 bool caps_overwriting:1; /* caps overwrite being in process */
98 bool cache_coef:1; /* cache COEF read/write too */
99 unsigned int registered:1; /* codec was registered */
100};
101
102/* device/driver type used for matching */
103enum {
104 HDA_DEV_CORE,
105 HDA_DEV_LEGACY,
106 HDA_DEV_ASOC,
107};
108
109enum {
110 SND_SKL_PCI_BIND_AUTO, /* automatic selection based on pci class */
111 SND_SKL_PCI_BIND_LEGACY,/* bind only with legacy driver */
112 SND_SKL_PCI_BIND_ASOC /* bind only with ASoC driver */
113};
114
115/* direction */
116enum {
117 HDA_INPUT, HDA_OUTPUT
118};
119
120#define dev_to_hdac_dev(_dev) container_of(_dev, struct hdac_device, dev)
121
122int snd_hdac_device_init(struct hdac_device *dev, struct hdac_bus *bus,
123 const char *name, unsigned int addr);
124void snd_hdac_device_exit(struct hdac_device *dev);
125int snd_hdac_device_register(struct hdac_device *codec);
126void snd_hdac_device_unregister(struct hdac_device *codec);
127int snd_hdac_device_set_chip_name(struct hdac_device *codec, const char *name);
128int snd_hdac_codec_modalias(const struct hdac_device *hdac, char *buf, size_t size);
129
130int snd_hdac_refresh_widgets(struct hdac_device *codec);
131
132int snd_hdac_read(struct hdac_device *codec, hda_nid_t nid,
133 unsigned int verb, unsigned int parm, unsigned int *res);
134int _snd_hdac_read_parm(struct hdac_device *codec, hda_nid_t nid, int parm,
135 unsigned int *res);
136int snd_hdac_read_parm_uncached(struct hdac_device *codec, hda_nid_t nid,
137 int parm);
138int snd_hdac_override_parm(struct hdac_device *codec, hda_nid_t nid,
139 unsigned int parm, unsigned int val);
140int snd_hdac_get_connections(struct hdac_device *codec, hda_nid_t nid,
141 hda_nid_t *conn_list, int max_conns);
142int snd_hdac_get_sub_nodes(struct hdac_device *codec, hda_nid_t nid,
143 hda_nid_t *start_id);
144unsigned int snd_hdac_stream_format_bits(snd_pcm_format_t format, snd_pcm_subformat_t subformat,
145 unsigned int maxbits);
146unsigned int snd_hdac_stream_format(unsigned int channels, unsigned int bits, unsigned int rate);
147unsigned int snd_hdac_spdif_stream_format(unsigned int channels, unsigned int bits,
148 unsigned int rate, unsigned short spdif_ctls);
149int snd_hdac_query_supported_pcm(struct hdac_device *codec, hda_nid_t nid,
150 u32 *ratesp, u64 *formatsp, u32 *subformatsp,
151 unsigned int *bpsp);
152bool snd_hdac_is_supported_format(struct hdac_device *codec, hda_nid_t nid,
153 unsigned int format);
154
155int snd_hdac_codec_read(struct hdac_device *hdac, hda_nid_t nid,
156 int flags, unsigned int verb, unsigned int parm);
157int snd_hdac_codec_write(struct hdac_device *hdac, hda_nid_t nid,
158 int flags, unsigned int verb, unsigned int parm);
159bool snd_hdac_check_power_state(struct hdac_device *hdac,
160 hda_nid_t nid, unsigned int target_state);
161unsigned int snd_hdac_sync_power_state(struct hdac_device *hdac,
162 hda_nid_t nid, unsigned int target_state);
163/**
164 * snd_hdac_read_parm - read a codec parameter
165 * @codec: the codec object
166 * @nid: NID to read a parameter
167 * @parm: parameter to read
168 *
169 * Returns -1 for error. If you need to distinguish the error more
170 * strictly, use _snd_hdac_read_parm() directly.
171 */
172static inline int snd_hdac_read_parm(struct hdac_device *codec, hda_nid_t nid,
173 int parm)
174{
175 unsigned int val;
176
177 return _snd_hdac_read_parm(codec, nid, parm, &val) < 0 ? -1 : val;
178}
179
180#ifdef CONFIG_PM
181int snd_hdac_power_up(struct hdac_device *codec);
182int snd_hdac_power_down(struct hdac_device *codec);
183int snd_hdac_power_up_pm(struct hdac_device *codec);
184int snd_hdac_power_down_pm(struct hdac_device *codec);
185int snd_hdac_keep_power_up(struct hdac_device *codec);
186
187/* call this at entering into suspend/resume callbacks in codec driver */
188static inline void snd_hdac_enter_pm(struct hdac_device *codec)
189{
190 atomic_inc(&codec->in_pm);
191}
192
193/* call this at leaving from suspend/resume callbacks in codec driver */
194static inline void snd_hdac_leave_pm(struct hdac_device *codec)
195{
196 atomic_dec(&codec->in_pm);
197}
198
199static inline bool snd_hdac_is_in_pm(struct hdac_device *codec)
200{
201 return atomic_read(&codec->in_pm);
202}
203
204static inline bool snd_hdac_is_power_on(struct hdac_device *codec)
205{
206 return !pm_runtime_suspended(&codec->dev);
207}
208#else
209static inline int snd_hdac_power_up(struct hdac_device *codec) { return 0; }
210static inline int snd_hdac_power_down(struct hdac_device *codec) { return 0; }
211static inline int snd_hdac_power_up_pm(struct hdac_device *codec) { return 0; }
212static inline int snd_hdac_power_down_pm(struct hdac_device *codec) { return 0; }
213static inline int snd_hdac_keep_power_up(struct hdac_device *codec) { return 0; }
214static inline void snd_hdac_enter_pm(struct hdac_device *codec) {}
215static inline void snd_hdac_leave_pm(struct hdac_device *codec) {}
216static inline bool snd_hdac_is_in_pm(struct hdac_device *codec) { return false; }
217static inline bool snd_hdac_is_power_on(struct hdac_device *codec) { return true; }
218#endif
219
220/*
221 * HD-audio codec base driver
222 */
223struct hdac_driver {
224 struct device_driver driver;
225 int type;
226 const struct hda_device_id *id_table;
227 int (*match)(struct hdac_device *dev, const struct hdac_driver *drv);
228 void (*unsol_event)(struct hdac_device *dev, unsigned int event);
229
230 /* fields used by ext bus APIs */
231 int (*probe)(struct hdac_device *dev);
232 int (*remove)(struct hdac_device *dev);
233 void (*shutdown)(struct hdac_device *dev);
234};
235
236#define drv_to_hdac_driver(_drv) container_of(_drv, struct hdac_driver, driver)
237
238const struct hda_device_id *
239hdac_get_device_id(struct hdac_device *hdev, const struct hdac_driver *drv);
240
241/*
242 * Bus verb operators
243 */
244struct hdac_bus_ops {
245 /* send a single command */
246 int (*command)(struct hdac_bus *bus, unsigned int cmd);
247 /* get a response from the last command */
248 int (*get_response)(struct hdac_bus *bus, unsigned int addr,
249 unsigned int *res);
250 /* notify of codec link power-up/down */
251 void (*link_power)(struct hdac_device *hdev, bool enable);
252};
253
254/*
255 * ops used for ASoC HDA codec drivers
256 */
257struct hdac_ext_bus_ops {
258 int (*hdev_attach)(struct hdac_device *hdev);
259 int (*hdev_detach)(struct hdac_device *hdev);
260};
261
262#define HDA_UNSOL_QUEUE_SIZE 64
263#define HDA_MAX_CODECS 8 /* limit by controller side */
264
265/*
266 * CORB/RIRB
267 *
268 * Each CORB entry is 4byte, RIRB is 8byte
269 */
270struct hdac_rb {
271 __le32 *buf; /* virtual address of CORB/RIRB buffer */
272 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
273 unsigned short rp, wp; /* RIRB read/write pointers */
274 int cmds[HDA_MAX_CODECS]; /* number of pending requests */
275 u32 res[HDA_MAX_CODECS]; /* last read value */
276};
277
278/*
279 * HD-audio bus base driver
280 *
281 * @ppcap: pp capabilities pointer
282 * @spbcap: SPIB capabilities pointer
283 * @mlcap: MultiLink capabilities pointer
284 * @gtscap: gts capabilities pointer
285 * @drsmcap: dma resume capabilities pointer
286 * @num_streams: streams supported
287 * @idx: HDA link index
288 * @hlink_list: link list of HDA links
289 * @lock: lock for link and display power mgmt
290 * @cmd_dma_state: state of cmd DMAs: CORB and RIRB
291 */
292struct hdac_bus {
293 struct device *dev;
294 const struct hdac_bus_ops *ops;
295 const struct hdac_ext_bus_ops *ext_ops;
296
297 /* h/w resources */
298 unsigned long addr;
299 void __iomem *remap_addr;
300 int irq;
301
302 void __iomem *ppcap;
303 void __iomem *spbcap;
304 void __iomem *mlcap;
305 void __iomem *gtscap;
306 void __iomem *drsmcap;
307
308 /* codec linked list */
309 struct list_head codec_list;
310 unsigned int num_codecs;
311
312 /* link caddr -> codec */
313 struct hdac_device *caddr_tbl[HDA_MAX_CODEC_ADDRESS + 1];
314
315 /* unsolicited event queue */
316 u32 unsol_queue[HDA_UNSOL_QUEUE_SIZE * 2]; /* ring buffer */
317 unsigned int unsol_rp, unsol_wp;
318 struct work_struct unsol_work;
319
320 /* bit flags of detected codecs */
321 unsigned long codec_mask;
322
323 /* bit flags of powered codecs */
324 unsigned long codec_powered;
325
326 /* CORB/RIRB */
327 struct hdac_rb corb;
328 struct hdac_rb rirb;
329 unsigned int last_cmd[HDA_MAX_CODECS]; /* last sent command */
330 wait_queue_head_t rirb_wq;
331
332 /* CORB/RIRB and position buffers */
333 struct snd_dma_buffer rb;
334 struct snd_dma_buffer posbuf;
335 int dma_type; /* SNDRV_DMA_TYPE_XXX for CORB/RIRB */
336
337 /* hdac_stream linked list */
338 struct list_head stream_list;
339
340 /* operation state */
341 bool chip_init:1; /* h/w initialized */
342
343 /* behavior flags */
344 bool aligned_mmio:1; /* aligned MMIO access */
345 bool sync_write:1; /* sync after verb write */
346 bool use_posbuf:1; /* use position buffer */
347 bool snoop:1; /* enable snooping */
348 bool align_bdle_4k:1; /* BDLE align 4K boundary */
349 bool reverse_assign:1; /* assign devices in reverse order */
350 bool corbrp_self_clear:1; /* CORBRP clears itself after reset */
351 bool polling_mode:1;
352 bool needs_damn_long_delay:1;
353 bool not_use_interrupts:1; /* prohibiting the RIRB IRQ */
354 bool access_sdnctl_in_dword:1; /* accessing the sdnctl register by dword */
355 bool use_pio_for_commands:1; /* Use PIO instead of CORB for commands */
356
357 int poll_count;
358
359 int bdl_pos_adj; /* BDL position adjustment */
360
361 /* delay time in us for dma stop */
362 unsigned int dma_stop_delay;
363
364 /* locks */
365 spinlock_t reg_lock;
366 struct mutex cmd_mutex;
367 struct mutex lock;
368
369 /* DRM component interface */
370 struct drm_audio_component *audio_component;
371 long display_power_status;
372 unsigned long display_power_active;
373
374 /* parameters required for enhanced capabilities */
375 int num_streams;
376 int idx;
377
378 /* link management */
379 struct list_head hlink_list;
380 bool cmd_dma_state;
381
382 /* factor used to derive STRIPE control value */
383 unsigned int sdo_limit;
384
385 /* address offset between host and hadc */
386 dma_addr_t addr_offset;
387};
388
389int snd_hdac_bus_init(struct hdac_bus *bus, struct device *dev,
390 const struct hdac_bus_ops *ops);
391void snd_hdac_bus_exit(struct hdac_bus *bus);
392int snd_hdac_bus_exec_verb_unlocked(struct hdac_bus *bus, unsigned int addr,
393 unsigned int cmd, unsigned int *res);
394
395void snd_hdac_codec_link_up(struct hdac_device *codec);
396void snd_hdac_codec_link_down(struct hdac_device *codec);
397
398int snd_hdac_bus_send_cmd(struct hdac_bus *bus, unsigned int val);
399int snd_hdac_bus_get_response(struct hdac_bus *bus, unsigned int addr,
400 unsigned int *res);
401int snd_hdac_bus_parse_capabilities(struct hdac_bus *bus);
402
403bool snd_hdac_bus_init_chip(struct hdac_bus *bus, bool full_reset);
404void snd_hdac_bus_stop_chip(struct hdac_bus *bus);
405void snd_hdac_bus_init_cmd_io(struct hdac_bus *bus);
406void snd_hdac_bus_stop_cmd_io(struct hdac_bus *bus);
407void snd_hdac_bus_enter_link_reset(struct hdac_bus *bus);
408void snd_hdac_bus_exit_link_reset(struct hdac_bus *bus);
409int snd_hdac_bus_reset_link(struct hdac_bus *bus, bool full_reset);
410void snd_hdac_bus_link_power(struct hdac_device *hdev, bool enable);
411
412void snd_hdac_bus_update_rirb(struct hdac_bus *bus);
413int snd_hdac_bus_handle_stream_irq(struct hdac_bus *bus, unsigned int status,
414 void (*ack)(struct hdac_bus *,
415 struct hdac_stream *));
416
417int snd_hdac_bus_alloc_stream_pages(struct hdac_bus *bus);
418void snd_hdac_bus_free_stream_pages(struct hdac_bus *bus);
419
420#ifdef CONFIG_SND_HDA_ALIGNED_MMIO
421unsigned int snd_hdac_aligned_read(void __iomem *addr, unsigned int mask);
422void snd_hdac_aligned_write(unsigned int val, void __iomem *addr,
423 unsigned int mask);
424#define snd_hdac_aligned_mmio(bus) (bus)->aligned_mmio
425#else
426#define snd_hdac_aligned_mmio(bus) false
427#define snd_hdac_aligned_read(addr, mask) 0
428#define snd_hdac_aligned_write(val, addr, mask) do {} while (0)
429#endif
430
431static inline void snd_hdac_reg_writeb(struct hdac_bus *bus, void __iomem *addr,
432 u8 val)
433{
434 if (snd_hdac_aligned_mmio(bus))
435 snd_hdac_aligned_write(val, addr, 0xff);
436 else
437 writeb(val, addr);
438}
439
440static inline void snd_hdac_reg_writew(struct hdac_bus *bus, void __iomem *addr,
441 u16 val)
442{
443 if (snd_hdac_aligned_mmio(bus))
444 snd_hdac_aligned_write(val, addr, 0xffff);
445 else
446 writew(val, addr);
447}
448
449static inline u8 snd_hdac_reg_readb(struct hdac_bus *bus, void __iomem *addr)
450{
451 return snd_hdac_aligned_mmio(bus) ?
452 snd_hdac_aligned_read(addr, 0xff) : readb(addr);
453}
454
455static inline u16 snd_hdac_reg_readw(struct hdac_bus *bus, void __iomem *addr)
456{
457 return snd_hdac_aligned_mmio(bus) ?
458 snd_hdac_aligned_read(addr, 0xffff) : readw(addr);
459}
460
461#define snd_hdac_reg_writel(bus, addr, val) writel(val, addr)
462#define snd_hdac_reg_readl(bus, addr) readl(addr)
463#define snd_hdac_reg_writeq(bus, addr, val) writeq(val, addr)
464#define snd_hdac_reg_readq(bus, addr) readq(addr)
465
466/*
467 * macros for easy use
468 */
469#define _snd_hdac_chip_writeb(chip, reg, value) \
470 snd_hdac_reg_writeb(chip, (chip)->remap_addr + (reg), value)
471#define _snd_hdac_chip_readb(chip, reg) \
472 snd_hdac_reg_readb(chip, (chip)->remap_addr + (reg))
473#define _snd_hdac_chip_writew(chip, reg, value) \
474 snd_hdac_reg_writew(chip, (chip)->remap_addr + (reg), value)
475#define _snd_hdac_chip_readw(chip, reg) \
476 snd_hdac_reg_readw(chip, (chip)->remap_addr + (reg))
477#define _snd_hdac_chip_writel(chip, reg, value) \
478 snd_hdac_reg_writel(chip, (chip)->remap_addr + (reg), value)
479#define _snd_hdac_chip_readl(chip, reg) \
480 snd_hdac_reg_readl(chip, (chip)->remap_addr + (reg))
481
482/* read/write a register, pass without AZX_REG_ prefix */
483#define snd_hdac_chip_writel(chip, reg, value) \
484 _snd_hdac_chip_writel(chip, AZX_REG_ ## reg, value)
485#define snd_hdac_chip_writew(chip, reg, value) \
486 _snd_hdac_chip_writew(chip, AZX_REG_ ## reg, value)
487#define snd_hdac_chip_writeb(chip, reg, value) \
488 _snd_hdac_chip_writeb(chip, AZX_REG_ ## reg, value)
489#define snd_hdac_chip_readl(chip, reg) \
490 _snd_hdac_chip_readl(chip, AZX_REG_ ## reg)
491#define snd_hdac_chip_readw(chip, reg) \
492 _snd_hdac_chip_readw(chip, AZX_REG_ ## reg)
493#define snd_hdac_chip_readb(chip, reg) \
494 _snd_hdac_chip_readb(chip, AZX_REG_ ## reg)
495
496/* update a register, pass without AZX_REG_ prefix */
497#define snd_hdac_chip_updatel(chip, reg, mask, val) \
498 snd_hdac_chip_writel(chip, reg, \
499 (snd_hdac_chip_readl(chip, reg) & ~(mask)) | (val))
500#define snd_hdac_chip_updatew(chip, reg, mask, val) \
501 snd_hdac_chip_writew(chip, reg, \
502 (snd_hdac_chip_readw(chip, reg) & ~(mask)) | (val))
503#define snd_hdac_chip_updateb(chip, reg, mask, val) \
504 snd_hdac_chip_writeb(chip, reg, \
505 (snd_hdac_chip_readb(chip, reg) & ~(mask)) | (val))
506
507/* update register macro */
508#define snd_hdac_updatel(addr, reg, mask, val) \
509 writel(((readl(addr + reg) & ~(mask)) | (val)), addr + reg)
510
511#define snd_hdac_updatew(addr, reg, mask, val) \
512 writew(((readw(addr + reg) & ~(mask)) | (val)), addr + reg)
513
514/*
515 * HD-audio stream
516 */
517struct hdac_stream {
518 struct hdac_bus *bus;
519 struct snd_dma_buffer bdl; /* BDL buffer */
520 __le32 *posbuf; /* position buffer pointer */
521 int direction; /* playback / capture (SNDRV_PCM_STREAM_*) */
522
523 unsigned int bufsize; /* size of the play buffer in bytes */
524 unsigned int period_bytes; /* size of the period in bytes */
525 unsigned int frags; /* number for period in the play buffer */
526 unsigned int fifo_size; /* FIFO size */
527
528 void __iomem *sd_addr; /* stream descriptor pointer */
529
530 void __iomem *spib_addr; /* software position in buffers stream pointer */
531 void __iomem *fifo_addr; /* software position Max fifos stream pointer */
532
533 void __iomem *dpibr_addr; /* DMA position in buffer resume pointer */
534 u32 dpib; /* DMA position in buffer */
535 u32 lpib; /* Linear position in buffer */
536
537 u32 sd_int_sta_mask; /* stream int status mask */
538
539 /* pcm support */
540 struct snd_pcm_substream *substream; /* assigned substream,
541 * set in PCM open
542 */
543 struct snd_compr_stream *cstream;
544 unsigned int format_val; /* format value to be set in the
545 * controller and the codec
546 */
547 unsigned char stream_tag; /* assigned stream */
548 unsigned char index; /* stream index */
549 int assigned_key; /* last device# key assigned to */
550
551 bool opened:1;
552 bool running:1;
553 bool prepared:1;
554 bool no_period_wakeup:1;
555 bool locked:1;
556 bool stripe:1; /* apply stripe control */
557
558 u64 curr_pos;
559 /* timestamp */
560 unsigned long start_wallclk; /* start + minimum wallclk */
561 unsigned long period_wallclk; /* wallclk for period */
562 struct timecounter tc;
563 struct cyclecounter cc;
564 int delay_negative_threshold;
565
566 struct list_head list;
567#ifdef CONFIG_SND_HDA_DSP_LOADER
568 /* DSP access mutex */
569 struct mutex dsp_mutex;
570#endif
571};
572
573void snd_hdac_stream_init(struct hdac_bus *bus, struct hdac_stream *azx_dev,
574 int idx, int direction, int tag);
575struct hdac_stream *snd_hdac_stream_assign(struct hdac_bus *bus,
576 struct snd_pcm_substream *substream);
577void snd_hdac_stream_release_locked(struct hdac_stream *azx_dev);
578void snd_hdac_stream_release(struct hdac_stream *azx_dev);
579struct hdac_stream *snd_hdac_get_stream(struct hdac_bus *bus,
580 int dir, int stream_tag);
581
582int snd_hdac_stream_setup(struct hdac_stream *azx_dev, bool code_loading);
583void snd_hdac_stream_cleanup(struct hdac_stream *azx_dev);
584int snd_hdac_stream_setup_periods(struct hdac_stream *azx_dev);
585int snd_hdac_stream_set_params(struct hdac_stream *azx_dev,
586 unsigned int format_val);
587void snd_hdac_stream_start(struct hdac_stream *azx_dev);
588void snd_hdac_stream_stop(struct hdac_stream *azx_dev);
589void snd_hdac_stop_streams(struct hdac_bus *bus);
590void snd_hdac_stop_streams_and_chip(struct hdac_bus *bus);
591void snd_hdac_stream_reset(struct hdac_stream *azx_dev);
592void snd_hdac_stream_sync_trigger(struct hdac_stream *azx_dev, bool set,
593 unsigned int streams, unsigned int reg);
594void snd_hdac_stream_sync(struct hdac_stream *azx_dev, bool start,
595 unsigned int streams);
596void snd_hdac_stream_timecounter_init(struct hdac_stream *azx_dev,
597 unsigned int streams, bool start);
598int snd_hdac_get_stream_stripe_ctl(struct hdac_bus *bus,
599 struct snd_pcm_substream *substream);
600
601void snd_hdac_stream_spbcap_enable(struct hdac_bus *chip,
602 bool enable, int index);
603int snd_hdac_stream_set_spib(struct hdac_bus *bus,
604 struct hdac_stream *azx_dev, u32 value);
605void snd_hdac_stream_drsm_enable(struct hdac_bus *bus,
606 bool enable, int index);
607int snd_hdac_stream_wait_drsm(struct hdac_stream *azx_dev);
608int snd_hdac_stream_set_dpibr(struct hdac_bus *bus,
609 struct hdac_stream *azx_dev, u32 value);
610int snd_hdac_stream_set_lpib(struct hdac_stream *azx_dev, u32 value);
611
612/*
613 * macros for easy use
614 */
615/* read/write a register, pass without AZX_REG_ prefix */
616#define snd_hdac_stream_writel(dev, reg, value) \
617 snd_hdac_reg_writel((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg, value)
618#define snd_hdac_stream_writew(dev, reg, value) \
619 snd_hdac_reg_writew((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg, value)
620#define snd_hdac_stream_writeb(dev, reg, value) \
621 snd_hdac_reg_writeb((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg, value)
622#define snd_hdac_stream_readl(dev, reg) \
623 snd_hdac_reg_readl((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg)
624#define snd_hdac_stream_readw(dev, reg) \
625 snd_hdac_reg_readw((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg)
626#define snd_hdac_stream_readb(dev, reg) \
627 snd_hdac_reg_readb((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg)
628#define snd_hdac_stream_readb_poll(dev, reg, val, cond, delay_us, timeout_us) \
629 read_poll_timeout_atomic(snd_hdac_reg_readb, val, cond, delay_us, timeout_us, \
630 false, (dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg)
631#define snd_hdac_stream_readw_poll(dev, reg, val, cond, delay_us, timeout_us) \
632 read_poll_timeout_atomic(snd_hdac_reg_readw, val, cond, delay_us, timeout_us, \
633 false, (dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg)
634#define snd_hdac_stream_readl_poll(dev, reg, val, cond, delay_us, timeout_us) \
635 read_poll_timeout_atomic(snd_hdac_reg_readl, val, cond, delay_us, timeout_us, \
636 false, (dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg)
637
638/* update a register, pass without AZX_REG_ prefix */
639#define snd_hdac_stream_updatel(dev, reg, mask, val) \
640 snd_hdac_stream_writel(dev, reg, \
641 (snd_hdac_stream_readl(dev, reg) & \
642 ~(mask)) | (val))
643#define snd_hdac_stream_updatew(dev, reg, mask, val) \
644 snd_hdac_stream_writew(dev, reg, \
645 (snd_hdac_stream_readw(dev, reg) & \
646 ~(mask)) | (val))
647#define snd_hdac_stream_updateb(dev, reg, mask, val) \
648 snd_hdac_stream_writeb(dev, reg, \
649 (snd_hdac_stream_readb(dev, reg) & \
650 ~(mask)) | (val))
651
652#ifdef CONFIG_SND_HDA_DSP_LOADER
653/* DSP lock helpers */
654#define snd_hdac_dsp_lock_init(dev) mutex_init(&(dev)->dsp_mutex)
655#define snd_hdac_dsp_lock(dev) mutex_lock(&(dev)->dsp_mutex)
656#define snd_hdac_dsp_unlock(dev) mutex_unlock(&(dev)->dsp_mutex)
657#define snd_hdac_stream_is_locked(dev) ((dev)->locked)
658DEFINE_GUARD(snd_hdac_dsp_lock, struct hdac_stream *, snd_hdac_dsp_lock(_T), snd_hdac_dsp_unlock(_T))
659/* DSP loader helpers */
660int snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format,
661 unsigned int byte_size, struct snd_dma_buffer *bufp);
662void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start);
663void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev,
664 struct snd_dma_buffer *dmab);
665#else /* CONFIG_SND_HDA_DSP_LOADER */
666#define snd_hdac_dsp_lock_init(dev) do {} while (0)
667#define snd_hdac_dsp_lock(dev) do {} while (0)
668#define snd_hdac_dsp_unlock(dev) do {} while (0)
669#define snd_hdac_stream_is_locked(dev) 0
670
671static inline int
672snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format,
673 unsigned int byte_size, struct snd_dma_buffer *bufp)
674{
675 return 0;
676}
677
678static inline void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start)
679{
680}
681
682static inline void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev,
683 struct snd_dma_buffer *dmab)
684{
685}
686#endif /* CONFIG_SND_HDA_DSP_LOADER */
687
688/*
689 * Easy macros for widget capabilities
690 */
691#define snd_hdac_get_wcaps(codec, nid) \
692 snd_hdac_read_parm(codec, nid, AC_PAR_AUDIO_WIDGET_CAP)
693
694/* get the widget type from widget capability bits */
695static inline int snd_hdac_get_wcaps_type(unsigned int wcaps)
696{
697 if (!wcaps)
698 return -1; /* invalid type */
699 return (wcaps & AC_WCAP_TYPE) >> AC_WCAP_TYPE_SHIFT;
700}
701
702/* get the number of supported channels */
703static inline unsigned int snd_hdac_get_wcaps_channels(u32 wcaps)
704{
705 unsigned int chans;
706
707 chans = (wcaps & AC_WCAP_CHAN_CNT_EXT) >> 13;
708 chans = (chans + 1) * 2;
709
710 return chans;
711}
712
713/*
714 * generic array helpers
715 */
716void *snd_array_new(struct snd_array *array);
717void snd_array_free(struct snd_array *array);
718static inline void snd_array_init(struct snd_array *array, unsigned int size,
719 unsigned int align)
720{
721 array->elem_size = size;
722 array->alloc_align = align;
723}
724
725static inline void *snd_array_elem(struct snd_array *array, unsigned int idx)
726{
727 return array->list + idx * array->elem_size;
728}
729
730static inline unsigned int snd_array_index(struct snd_array *array, void *ptr)
731{
732 return (unsigned long)(ptr - array->list) / array->elem_size;
733}
734
735/* a helper macro to iterate for each snd_array element */
736#define snd_array_for_each(array, idx, ptr) \
737 for ((idx) = 0, (ptr) = (array)->list; (idx) < (array)->used; \
738 (ptr) = snd_array_elem(array, ++(idx)))
739
740/*
741 * Device matching
742 */
743
744#define HDA_CONTROLLER_IS_HSW(pci) (pci_match_id((struct pci_device_id []){ \
745 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_HSW_0) }, \
746 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_HSW_2) }, \
747 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_HSW_3) }, \
748 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_BDW) }, \
749 { } \
750 }, pci))
751
752#define HDA_CONTROLLER_IS_APL(pci) (pci_match_id((struct pci_device_id []){ \
753 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_APL) }, \
754 { } \
755 }, pci))
756
757#define HDA_CONTROLLER_IN_GPU(pci) (pci_match_id((struct pci_device_id []){ \
758 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_DG1) }, \
759 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_DG2_0) }, \
760 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_DG2_1) }, \
761 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_DG2_2) }, \
762 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_BMG) }, \
763 { } \
764 }, pci) || HDA_CONTROLLER_IS_HSW(pci))
765
766#endif /* __SOUND_HDAUDIO_H */