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1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
2/*
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * Copyright(c) 2022 Intel Corporation
7 */
8
9#ifndef __INCLUDE_SOUND_SOF_IPC4_HEADER_H__
10#define __INCLUDE_SOUND_SOF_IPC4_HEADER_H__
11
12#include <linux/types.h>
13#include <uapi/sound/sof/abi.h>
14
15/* maximum message size for mailbox Tx/Rx */
16#define SOF_IPC4_MSG_MAX_SIZE 4096
17
18/** \addtogroup sof_uapi uAPI
19 * SOF uAPI specification.
20 * @{
21 */
22
23/**
24 * struct sof_ipc4_msg - Placeholder of an IPC4 message
25 * @header_u64: IPC4 header as single u64 number
26 * @primary: Primary, mandatory part of the header
27 * @extension: Extended part of the header, if not used it should be
28 * set to 0
29 * @data_size: Size of data in bytes pointed by @data_ptr
30 * @data_ptr: Pointer to the optional payload of a message
31 */
32struct sof_ipc4_msg {
33 union {
34 u64 header_u64;
35 struct {
36 u32 primary;
37 u32 extension;
38 };
39 };
40
41 size_t data_size;
42 void *data_ptr;
43};
44
45/**
46 * struct sof_ipc4_tuple - Generic type/ID and parameter tuple
47 * @type: type/ID
48 * @size: size of the @value array in bytes
49 * @value: value for the given type
50 */
51struct sof_ipc4_tuple {
52 uint32_t type;
53 uint32_t size;
54 uint32_t value[];
55} __packed;
56
57/*
58 * IPC4 messages have two 32 bit identifier made up as follows :-
59 *
60 * header - msg type, msg id, msg direction ...
61 * extension - extra params such as msg data size in mailbox
62 *
63 * These are sent at the start of the IPC message in the mailbox. Messages
64 * should not be sent in the doorbell (special exceptions for firmware).
65 */
66
67/*
68 * IPC4 primary header bit allocation for messages
69 * bit 0-23: message type specific
70 * bit 24-28: type: enum sof_ipc4_global_msg if target is SOF_IPC4_FW_GEN_MSG
71 * enum sof_ipc4_module_type if target is SOF_IPC4_MODULE_MSG
72 * bit 29: response - sof_ipc4_msg_dir
73 * bit 30: target - enum sof_ipc4_msg_target
74 * bit 31: reserved, unused
75 */
76
77/* Value of target field - must fit into 1 bit */
78enum sof_ipc4_msg_target {
79 /* Global FW message */
80 SOF_IPC4_FW_GEN_MSG,
81
82 /* Module message */
83 SOF_IPC4_MODULE_MSG
84};
85
86/* Value of type field - must fit into 5 bits */
87enum sof_ipc4_global_msg {
88 SOF_IPC4_GLB_BOOT_CONFIG,
89 SOF_IPC4_GLB_ROM_CONTROL,
90 SOF_IPC4_GLB_IPCGATEWAY_CMD,
91
92 /* 3 .. 12: RESERVED - do not use */
93
94 SOF_IPC4_GLB_PERF_MEASUREMENTS_CMD = 13,
95 SOF_IPC4_GLB_CHAIN_DMA,
96
97 SOF_IPC4_GLB_LOAD_MULTIPLE_MODULES,
98 SOF_IPC4_GLB_UNLOAD_MULTIPLE_MODULES,
99
100 /* pipeline settings */
101 SOF_IPC4_GLB_CREATE_PIPELINE,
102 SOF_IPC4_GLB_DELETE_PIPELINE,
103 SOF_IPC4_GLB_SET_PIPELINE_STATE,
104 SOF_IPC4_GLB_GET_PIPELINE_STATE,
105 SOF_IPC4_GLB_GET_PIPELINE_CONTEXT_SIZE,
106 SOF_IPC4_GLB_SAVE_PIPELINE,
107 SOF_IPC4_GLB_RESTORE_PIPELINE,
108
109 /*
110 * library loading
111 *
112 * Loads library (using Code Load or HD/A Host Output DMA)
113 */
114 SOF_IPC4_GLB_LOAD_LIBRARY,
115 /*
116 * Prepare the host DMA channel for library loading, must be followed by
117 * a SOF_IPC4_GLB_LOAD_LIBRARY message as the library loading step
118 */
119 SOF_IPC4_GLB_LOAD_LIBRARY_PREPARE,
120
121 SOF_IPC4_GLB_INTERNAL_MESSAGE,
122
123 /* Notification (FW to SW driver) */
124 SOF_IPC4_GLB_NOTIFICATION,
125
126 /* 28 .. 31: RESERVED - do not use */
127
128 SOF_IPC4_GLB_TYPE_LAST,
129};
130
131/* Value of response field - must fit into 1 bit */
132enum sof_ipc4_msg_dir {
133 SOF_IPC4_MSG_REQUEST,
134 SOF_IPC4_MSG_REPLY,
135};
136
137enum sof_ipc4_pipeline_state {
138 SOF_IPC4_PIPE_INVALID_STATE,
139 SOF_IPC4_PIPE_UNINITIALIZED,
140 SOF_IPC4_PIPE_RESET,
141 SOF_IPC4_PIPE_PAUSED,
142 SOF_IPC4_PIPE_RUNNING,
143 SOF_IPC4_PIPE_EOS
144};
145
146/* Generic message fields (bit 24-30) */
147
148/* encoded to header's msg_tgt field */
149#define SOF_IPC4_MSG_TARGET_SHIFT 30
150#define SOF_IPC4_MSG_TARGET_MASK BIT(30)
151#define SOF_IPC4_MSG_TARGET(x) ((x) << SOF_IPC4_MSG_TARGET_SHIFT)
152#define SOF_IPC4_MSG_IS_MODULE_MSG(x) ((x) & SOF_IPC4_MSG_TARGET_MASK ? 1 : 0)
153
154/* encoded to header's rsp field */
155#define SOF_IPC4_MSG_DIR_SHIFT 29
156#define SOF_IPC4_MSG_DIR_MASK BIT(29)
157#define SOF_IPC4_MSG_DIR(x) ((x) << SOF_IPC4_MSG_DIR_SHIFT)
158
159/* encoded to header's type field */
160#define SOF_IPC4_MSG_TYPE_SHIFT 24
161#define SOF_IPC4_MSG_TYPE_MASK GENMASK(28, 24)
162#define SOF_IPC4_MSG_TYPE_SET(x) (((x) << SOF_IPC4_MSG_TYPE_SHIFT) & \
163 SOF_IPC4_MSG_TYPE_MASK)
164#define SOF_IPC4_MSG_TYPE_GET(x) (((x) & SOF_IPC4_MSG_TYPE_MASK) >> \
165 SOF_IPC4_MSG_TYPE_SHIFT)
166
167/* Global message type specific field definitions */
168
169/* pipeline creation ipc msg */
170#define SOF_IPC4_GLB_PIPE_INSTANCE_SHIFT 16
171#define SOF_IPC4_GLB_PIPE_INSTANCE_MASK GENMASK(23, 16)
172#define SOF_IPC4_GLB_PIPE_INSTANCE_ID(x) ((x) << SOF_IPC4_GLB_PIPE_INSTANCE_SHIFT)
173
174#define SOF_IPC4_GLB_PIPE_PRIORITY_SHIFT 11
175#define SOF_IPC4_GLB_PIPE_PRIORITY_MASK GENMASK(15, 11)
176#define SOF_IPC4_GLB_PIPE_PRIORITY(x) ((x) << SOF_IPC4_GLB_PIPE_PRIORITY_SHIFT)
177
178#define SOF_IPC4_GLB_PIPE_MEM_SIZE_SHIFT 0
179#define SOF_IPC4_GLB_PIPE_MEM_SIZE_MASK GENMASK(10, 0)
180#define SOF_IPC4_GLB_PIPE_MEM_SIZE(x) ((x) << SOF_IPC4_GLB_PIPE_MEM_SIZE_SHIFT)
181
182#define SOF_IPC4_GLB_PIPE_EXT_LP_SHIFT 0
183#define SOF_IPC4_GLB_PIPE_EXT_LP_MASK BIT(0)
184#define SOF_IPC4_GLB_PIPE_EXT_LP(x) ((x) << SOF_IPC4_GLB_PIPE_EXT_LP_SHIFT)
185
186#define SOF_IPC4_GLB_PIPE_EXT_CORE_ID_SHIFT 20
187#define SOF_IPC4_GLB_PIPE_EXT_CORE_ID_MASK GENMASK(23, 20)
188#define SOF_IPC4_GLB_PIPE_EXT_CORE_ID(x) ((x) << SOF_IPC4_GLB_PIPE_EXT_CORE_ID_SHIFT)
189
190#define SOF_IPC4_GLB_PIPE_PAYLOAD_SHIFT 29
191#define SOF_IPC4_GLB_PIPE_PAYLOAD_MASK BIT(29)
192#define SOF_IPC4_GLB_PIPE_PAYLOAD(x) ((x) << SOF_IPC4_GLB_PIPE_PAYLOAD_SHIFT)
193
194/* pipeline set state ipc msg */
195#define SOF_IPC4_GLB_PIPE_STATE_ID_SHIFT 16
196#define SOF_IPC4_GLB_PIPE_STATE_ID_MASK GENMASK(23, 16)
197#define SOF_IPC4_GLB_PIPE_STATE_ID(x) ((x) << SOF_IPC4_GLB_PIPE_STATE_ID_SHIFT)
198
199#define SOF_IPC4_GLB_PIPE_STATE_SHIFT 0
200#define SOF_IPC4_GLB_PIPE_STATE_MASK GENMASK(15, 0)
201#define SOF_IPC4_GLB_PIPE_STATE(x) ((x) << SOF_IPC4_GLB_PIPE_STATE_SHIFT)
202
203/* pipeline set state IPC msg extension */
204#define SOF_IPC4_GLB_PIPE_STATE_EXT_MULTI BIT(0)
205
206/* load library ipc msg */
207#define SOF_IPC4_GLB_LOAD_LIBRARY_LIB_ID_SHIFT 16
208#define SOF_IPC4_GLB_LOAD_LIBRARY_LIB_ID(x) ((x) << SOF_IPC4_GLB_LOAD_LIBRARY_LIB_ID_SHIFT)
209
210/* chain dma ipc message */
211#define SOF_IPC4_GLB_CHAIN_DMA_HOST_ID_SHIFT 0
212#define SOF_IPC4_GLB_CHAIN_DMA_HOST_ID_MASK GENMASK(4, 0)
213#define SOF_IPC4_GLB_CHAIN_DMA_HOST_ID(x) (((x) << SOF_IPC4_GLB_CHAIN_DMA_HOST_ID_SHIFT) & \
214 SOF_IPC4_GLB_CHAIN_DMA_HOST_ID_MASK)
215
216#define SOF_IPC4_GLB_CHAIN_DMA_LINK_ID_SHIFT 8
217#define SOF_IPC4_GLB_CHAIN_DMA_LINK_ID_MASK GENMASK(12, 8)
218#define SOF_IPC4_GLB_CHAIN_DMA_LINK_ID(x) (((x) << SOF_IPC4_GLB_CHAIN_DMA_LINK_ID_SHIFT) & \
219 SOF_IPC4_GLB_CHAIN_DMA_LINK_ID_MASK)
220
221#define SOF_IPC4_GLB_CHAIN_DMA_ALLOCATE_SHIFT 16
222#define SOF_IPC4_GLB_CHAIN_DMA_ALLOCATE_MASK BIT(16)
223#define SOF_IPC4_GLB_CHAIN_DMA_ALLOCATE(x) (((x) & 1) << SOF_IPC4_GLB_CHAIN_DMA_ALLOCATE_SHIFT)
224
225#define SOF_IPC4_GLB_CHAIN_DMA_ENABLE_SHIFT 17
226#define SOF_IPC4_GLB_CHAIN_DMA_ENABLE_MASK BIT(17)
227#define SOF_IPC4_GLB_CHAIN_DMA_ENABLE(x) (((x) & 1) << SOF_IPC4_GLB_CHAIN_DMA_ENABLE_SHIFT)
228
229#define SOF_IPC4_GLB_CHAIN_DMA_SCS_SHIFT 18
230#define SOF_IPC4_GLB_CHAIN_DMA_SCS_MASK BIT(18)
231#define SOF_IPC4_GLB_CHAIN_DMA_SCS(x) (((x) & 1) << SOF_IPC4_GLB_CHAIN_DMA_SCS_SHIFT)
232
233#define SOF_IPC4_GLB_EXT_CHAIN_DMA_FIFO_SIZE_SHIFT 0
234#define SOF_IPC4_GLB_EXT_CHAIN_DMA_FIFO_SIZE_MASK GENMASK(24, 0)
235#define SOF_IPC4_GLB_EXT_CHAIN_DMA_FIFO_SIZE(x) (((x) << \
236 SOF_IPC4_GLB_EXT_CHAIN_DMA_FIFO_SIZE_SHIFT) & \
237 SOF_IPC4_GLB_EXT_CHAIN_DMA_FIFO_SIZE_MASK)
238
239enum sof_ipc4_channel_config {
240 /* one channel only. */
241 SOF_IPC4_CHANNEL_CONFIG_MONO,
242 /* L & R. */
243 SOF_IPC4_CHANNEL_CONFIG_STEREO,
244 /* L, R & LFE; PCM only. */
245 SOF_IPC4_CHANNEL_CONFIG_2_POINT_1,
246 /* L, C & R; MP3 & AAC only. */
247 SOF_IPC4_CHANNEL_CONFIG_3_POINT_0,
248 /* L, C, R & LFE; PCM only. */
249 SOF_IPC4_CHANNEL_CONFIG_3_POINT_1,
250 /* L, R, Ls & Rs; PCM only. */
251 SOF_IPC4_CHANNEL_CONFIG_QUATRO,
252 /* L, C, R & Cs; MP3 & AAC only. */
253 SOF_IPC4_CHANNEL_CONFIG_4_POINT_0,
254 /* L, C, R, Ls & Rs. */
255 SOF_IPC4_CHANNEL_CONFIG_5_POINT_0,
256 /* L, C, R, Ls, Rs & LFE. */
257 SOF_IPC4_CHANNEL_CONFIG_5_POINT_1,
258 /* one channel replicated in two. */
259 SOF_IPC4_CHANNEL_CONFIG_DUAL_MONO,
260 /* Stereo (L,R) in 4 slots, 1st stream: [ L, R, -, - ] */
261 SOF_IPC4_CHANNEL_CONFIG_I2S_DUAL_STEREO_0,
262 /* Stereo (L,R) in 4 slots, 2nd stream: [ -, -, L, R ] */
263 SOF_IPC4_CHANNEL_CONFIG_I2S_DUAL_STEREO_1,
264 /* L, C, R, Ls, Rs & LFE., LS, RS */
265 SOF_IPC4_CHANNEL_CONFIG_7_POINT_1,
266};
267
268enum sof_ipc4_interleaved_style {
269 SOF_IPC4_CHANNELS_INTERLEAVED,
270 SOF_IPC4_CHANNELS_NONINTERLEAVED,
271};
272
273enum sof_ipc4_sample_type {
274 SOF_IPC4_MSB_INTEGER, /* integer with Most Significant Byte first */
275 SOF_IPC4_LSB_INTEGER, /* integer with Least Significant Byte first */
276};
277
278struct sof_ipc4_audio_format {
279 uint32_t sampling_frequency;
280 uint32_t bit_depth;
281 uint32_t ch_map;
282 uint32_t ch_cfg; /* sof_ipc4_channel_config */
283 uint32_t interleaving_style;
284 uint32_t fmt_cfg; /* channels_count valid_bit_depth s_type */
285} __packed __aligned(4);
286
287#define SOF_IPC4_AUDIO_FORMAT_CFG_CHANNELS_COUNT_SHIFT 0
288#define SOF_IPC4_AUDIO_FORMAT_CFG_CHANNELS_COUNT_MASK GENMASK(7, 0)
289#define SOF_IPC4_AUDIO_FORMAT_CFG_CHANNELS_COUNT(x) \
290 ((x) & SOF_IPC4_AUDIO_FORMAT_CFG_CHANNELS_COUNT_MASK)
291#define SOF_IPC4_AUDIO_FORMAT_CFG_V_BIT_DEPTH_SHIFT 8
292#define SOF_IPC4_AUDIO_FORMAT_CFG_V_BIT_DEPTH_MASK GENMASK(15, 8)
293#define SOF_IPC4_AUDIO_FORMAT_CFG_V_BIT_DEPTH(x) \
294 (((x) & SOF_IPC4_AUDIO_FORMAT_CFG_V_BIT_DEPTH_MASK) >> \
295 SOF_IPC4_AUDIO_FORMAT_CFG_V_BIT_DEPTH_SHIFT)
296#define SOF_IPC4_AUDIO_FORMAT_CFG_SAMPLE_TYPE_SHIFT 16
297#define SOF_IPC4_AUDIO_FORMAT_CFG_SAMPLE_TYPE_MASK GENMASK(23, 16)
298#define SOF_IPC4_AUDIO_FORMAT_CFG_SAMPLE_TYPE(x) \
299 (((x) & SOF_IPC4_AUDIO_FORMAT_CFG_SAMPLE_TYPE_MASK) >> \
300 SOF_IPC4_AUDIO_FORMAT_CFG_SAMPLE_TYPE_SHIFT)
301
302/* Module message type specific field definitions */
303
304enum sof_ipc4_module_type {
305 SOF_IPC4_MOD_INIT_INSTANCE,
306 SOF_IPC4_MOD_CONFIG_GET,
307 SOF_IPC4_MOD_CONFIG_SET,
308 SOF_IPC4_MOD_LARGE_CONFIG_GET,
309 SOF_IPC4_MOD_LARGE_CONFIG_SET,
310 SOF_IPC4_MOD_BIND,
311 SOF_IPC4_MOD_UNBIND,
312 SOF_IPC4_MOD_SET_DX,
313 SOF_IPC4_MOD_SET_D0IX,
314 SOF_IPC4_MOD_ENTER_MODULE_RESTORE,
315 SOF_IPC4_MOD_EXIT_MODULE_RESTORE,
316 SOF_IPC4_MOD_DELETE_INSTANCE,
317
318 SOF_IPC4_MOD_TYPE_LAST,
319};
320
321struct sof_ipc4_base_module_cfg {
322 uint32_t cpc; /* the max count of Cycles Per Chunk processing */
323 uint32_t ibs; /* input Buffer Size (in bytes) */
324 uint32_t obs; /* output Buffer Size (in bytes) */
325 uint32_t is_pages; /* number of physical pages used */
326 struct sof_ipc4_audio_format audio_fmt;
327} __packed __aligned(4);
328
329/* common module ipc msg */
330#define SOF_IPC4_MOD_INSTANCE_SHIFT 16
331#define SOF_IPC4_MOD_INSTANCE_MASK GENMASK(23, 16)
332#define SOF_IPC4_MOD_INSTANCE(x) ((x) << SOF_IPC4_MOD_INSTANCE_SHIFT)
333#define SOF_IPC4_MOD_INSTANCE_GET(x) (((x) & SOF_IPC4_MOD_INSTANCE_MASK) \
334 >> SOF_IPC4_MOD_INSTANCE_SHIFT)
335
336#define SOF_IPC4_MOD_ID_SHIFT 0
337#define SOF_IPC4_MOD_ID_MASK GENMASK(15, 0)
338#define SOF_IPC4_MOD_ID(x) ((x) << SOF_IPC4_MOD_ID_SHIFT)
339#define SOF_IPC4_MOD_ID_GET(x) (((x) & SOF_IPC4_MOD_ID_MASK) \
340 >> SOF_IPC4_MOD_ID_SHIFT)
341
342/* init module ipc msg */
343#define SOF_IPC4_MOD_EXT_PARAM_SIZE_SHIFT 0
344#define SOF_IPC4_MOD_EXT_PARAM_SIZE_MASK GENMASK(15, 0)
345#define SOF_IPC4_MOD_EXT_PARAM_SIZE(x) ((x) << SOF_IPC4_MOD_EXT_PARAM_SIZE_SHIFT)
346
347#define SOF_IPC4_MOD_EXT_PPL_ID_SHIFT 16
348#define SOF_IPC4_MOD_EXT_PPL_ID_MASK GENMASK(23, 16)
349#define SOF_IPC4_MOD_EXT_PPL_ID(x) ((x) << SOF_IPC4_MOD_EXT_PPL_ID_SHIFT)
350
351#define SOF_IPC4_MOD_EXT_CORE_ID_SHIFT 24
352#define SOF_IPC4_MOD_EXT_CORE_ID_MASK GENMASK(27, 24)
353#define SOF_IPC4_MOD_EXT_CORE_ID(x) ((x) << SOF_IPC4_MOD_EXT_CORE_ID_SHIFT)
354
355#define SOF_IPC4_MOD_EXT_DOMAIN_SHIFT 28
356#define SOF_IPC4_MOD_EXT_DOMAIN_MASK BIT(28)
357#define SOF_IPC4_MOD_EXT_DOMAIN(x) ((x) << SOF_IPC4_MOD_EXT_DOMAIN_SHIFT)
358
359#define SOF_IPC4_MOD_EXT_EXTENDED_INIT_SHIFT 29
360#define SOF_IPC4_MOD_EXT_EXTENDED_INIT_MASK BIT(29)
361#define SOF_IPC4_MOD_EXT_EXTENDED_INIT(x) ((x) << SOF_IPC4_MOD_EXT_EXTENDED_SHIFT)
362
363/* bind/unbind module ipc msg */
364#define SOF_IPC4_MOD_EXT_DST_MOD_ID_SHIFT 0
365#define SOF_IPC4_MOD_EXT_DST_MOD_ID_MASK GENMASK(15, 0)
366#define SOF_IPC4_MOD_EXT_DST_MOD_ID(x) ((x) << SOF_IPC4_MOD_EXT_DST_MOD_ID_SHIFT)
367
368#define SOF_IPC4_MOD_EXT_DST_MOD_INSTANCE_SHIFT 16
369#define SOF_IPC4_MOD_EXT_DST_MOD_INSTANCE_MASK GENMASK(23, 16)
370#define SOF_IPC4_MOD_EXT_DST_MOD_INSTANCE(x) ((x) << SOF_IPC4_MOD_EXT_DST_MOD_INSTANCE_SHIFT)
371
372#define SOF_IPC4_MOD_EXT_DST_MOD_QUEUE_ID_SHIFT 24
373#define SOF_IPC4_MOD_EXT_DST_MOD_QUEUE_ID_MASK GENMASK(26, 24)
374#define SOF_IPC4_MOD_EXT_DST_MOD_QUEUE_ID(x) ((x) << SOF_IPC4_MOD_EXT_DST_MOD_QUEUE_ID_SHIFT)
375
376#define SOF_IPC4_MOD_EXT_SRC_MOD_QUEUE_ID_SHIFT 27
377#define SOF_IPC4_MOD_EXT_SRC_MOD_QUEUE_ID_MASK GENMASK(29, 27)
378#define SOF_IPC4_MOD_EXT_SRC_MOD_QUEUE_ID(x) ((x) << SOF_IPC4_MOD_EXT_SRC_MOD_QUEUE_ID_SHIFT)
379
380#define MOD_ENABLE_LOG 6
381#define MOD_SYSTEM_TIME 20
382
383/* set module large config */
384#define SOF_IPC4_MOD_EXT_MSG_SIZE_SHIFT 0
385#define SOF_IPC4_MOD_EXT_MSG_SIZE_MASK GENMASK(19, 0)
386#define SOF_IPC4_MOD_EXT_MSG_SIZE(x) ((x) << SOF_IPC4_MOD_EXT_MSG_SIZE_SHIFT)
387
388#define SOF_IPC4_MOD_EXT_MSG_PARAM_ID_SHIFT 20
389#define SOF_IPC4_MOD_EXT_MSG_PARAM_ID_MASK GENMASK(27, 20)
390#define SOF_IPC4_MOD_EXT_MSG_PARAM_ID(x) ((x) << SOF_IPC4_MOD_EXT_MSG_PARAM_ID_SHIFT)
391
392#define SOF_IPC4_MOD_EXT_MSG_LAST_BLOCK_SHIFT 28
393#define SOF_IPC4_MOD_EXT_MSG_LAST_BLOCK_MASK BIT(28)
394#define SOF_IPC4_MOD_EXT_MSG_LAST_BLOCK(x) ((x) << SOF_IPC4_MOD_EXT_MSG_LAST_BLOCK_SHIFT)
395
396#define SOF_IPC4_MOD_EXT_MSG_FIRST_BLOCK_SHIFT 29
397#define SOF_IPC4_MOD_EXT_MSG_FIRST_BLOCK_MASK BIT(29)
398#define SOF_IPC4_MOD_EXT_MSG_FIRST_BLOCK(x) ((x) << SOF_IPC4_MOD_EXT_MSG_FIRST_BLOCK_SHIFT)
399
400/* Init instance messagees */
401#define SOF_IPC4_MOD_INIT_BASEFW_MOD_ID 0
402#define SOF_IPC4_MOD_INIT_BASEFW_INSTANCE_ID 0
403
404enum sof_ipc4_base_fw_params {
405 SOF_IPC4_FW_PARAM_ENABLE_LOGS = 6,
406 SOF_IPC4_FW_PARAM_FW_CONFIG,
407 SOF_IPC4_FW_PARAM_HW_CONFIG_GET,
408 SOF_IPC4_FW_PARAM_MODULES_INFO_GET,
409 SOF_IPC4_FW_PARAM_LIBRARIES_INFO_GET = 16,
410 SOF_IPC4_FW_PARAM_SYSTEM_TIME = 20,
411 SOF_IPC4_FW_PARAM_MIC_PRIVACY_STATE_CHANGE = 35,
412};
413
414enum sof_ipc4_fw_config_params {
415 SOF_IPC4_FW_CFG_FW_VERSION,
416 SOF_IPC4_FW_CFG_MEMORY_RECLAIMED,
417 SOF_IPC4_FW_CFG_SLOW_CLOCK_FREQ_HZ,
418 SOF_IPC4_FW_CFG_FAST_CLOCK_FREQ_HZ,
419 SOF_IPC4_FW_CFG_DMA_BUFFER_CONFIG,
420 SOF_IPC4_FW_CFG_ALH_SUPPORT_LEVEL,
421 SOF_IPC4_FW_CFG_DL_MAILBOX_BYTES,
422 SOF_IPC4_FW_CFG_UL_MAILBOX_BYTES,
423 SOF_IPC4_FW_CFG_TRACE_LOG_BYTES,
424 SOF_IPC4_FW_CFG_MAX_PPL_COUNT,
425 SOF_IPC4_FW_CFG_MAX_ASTATE_COUNT,
426 SOF_IPC4_FW_CFG_MAX_MODULE_PIN_COUNT,
427 SOF_IPC4_FW_CFG_MODULES_COUNT,
428 SOF_IPC4_FW_CFG_MAX_MOD_INST_COUNT,
429 SOF_IPC4_FW_CFG_MAX_LL_TASKS_PER_PRI_COUNT,
430 SOF_IPC4_FW_CFG_LL_PRI_COUNT,
431 SOF_IPC4_FW_CFG_MAX_DP_TASKS_COUNT,
432 SOF_IPC4_FW_CFG_MAX_LIBS_COUNT,
433 SOF_IPC4_FW_CFG_SCHEDULER_CONFIG,
434 SOF_IPC4_FW_CFG_XTAL_FREQ_HZ,
435 SOF_IPC4_FW_CFG_CLOCKS_CONFIG,
436 SOF_IPC4_FW_CFG_RESERVED,
437 SOF_IPC4_FW_CFG_POWER_GATING_POLICY,
438 SOF_IPC4_FW_CFG_ASSERT_MODE,
439 SOF_IPC4_FW_RESERVED1,
440 SOF_IPC4_FW_RESERVED2,
441 SOF_IPC4_FW_RESERVED3,
442 SOF_IPC4_FW_RESERVED4,
443 SOF_IPC4_FW_RESERVED5,
444 SOF_IPC4_FW_CONTEXT_SAVE
445};
446
447struct sof_ipc4_fw_version {
448 uint16_t major;
449 uint16_t minor;
450 uint16_t hotfix;
451 uint16_t build;
452} __packed;
453
454/* Payload data for SOF_IPC4_MOD_SET_DX */
455struct sof_ipc4_dx_state_info {
456 /* core(s) to apply the change */
457 uint32_t core_mask;
458 /* core state: 0: put core_id to D3; 1: put core_id to D0 */
459 uint32_t dx_mask;
460} __packed __aligned(4);
461
462enum sof_ipc4_hw_config_params {
463 SOF_IPC4_HW_CFG_INTEL_MIC_PRIVACY_CAPS = 11,
464};
465
466#define SOF_IPC_INTEL_MIC_PRIVACY_VERSION_PTL 1
467
468struct sof_ipc4_intel_mic_privacy_cap {
469 uint32_t version;
470 uint32_t capabilities_length;
471 uint32_t capabilities[];
472} __packed;
473
474/* Reply messages */
475
476/*
477 * IPC4 primary header bit allocation for replies
478 * bit 0-23: status
479 * bit 24-28: type: enum sof_ipc4_global_msg if target is SOF_IPC4_FW_GEN_MSG
480 * enum sof_ipc4_module_type if target is SOF_IPC4_MODULE_MSG
481 * bit 29: response - sof_ipc4_msg_dir
482 * bit 30: target - enum sof_ipc4_msg_target
483 * bit 31: reserved, unused
484 */
485
486#define SOF_IPC4_REPLY_STATUS GENMASK(23, 0)
487
488/* Notification messages */
489
490/*
491 * IPC4 primary header bit allocation for notifications
492 * bit 0-15: notification type specific
493 * bit 16-23: enum sof_ipc4_notification_type
494 * bit 24-28: SOF_IPC4_GLB_NOTIFICATION
495 * bit 29: response - sof_ipc4_msg_dir
496 * bit 30: target - enum sof_ipc4_msg_target
497 * bit 31: reserved, unused
498 */
499
500#define SOF_IPC4_MSG_IS_NOTIFICATION(x) (SOF_IPC4_MSG_TYPE_GET(x) == \
501 SOF_IPC4_GLB_NOTIFICATION)
502
503#define SOF_IPC4_NOTIFICATION_TYPE_SHIFT 16
504#define SOF_IPC4_NOTIFICATION_TYPE_MASK GENMASK(23, 16)
505#define SOF_IPC4_NOTIFICATION_TYPE_GET(x) (((x) & SOF_IPC4_NOTIFICATION_TYPE_MASK) >> \
506 SOF_IPC4_NOTIFICATION_TYPE_SHIFT)
507
508#define SOF_IPC4_LOG_CORE_SHIFT 12
509#define SOF_IPC4_LOG_CORE_MASK GENMASK(15, 12)
510#define SOF_IPC4_LOG_CORE_GET(x) (((x) & SOF_IPC4_LOG_CORE_MASK) >> \
511 SOF_IPC4_LOG_CORE_SHIFT)
512
513#define SOF_IPC4_FW_READY_LIB_RESTORED BIT(15)
514
515/* Value of notification type field - must fit into 8 bits */
516enum sof_ipc4_notification_type {
517 /* Phrase detected (notification from WoV module) */
518 SOF_IPC4_NOTIFY_PHRASE_DETECTED = 4,
519 /* Event from a resource (pipeline or module instance) */
520 SOF_IPC4_NOTIFY_RESOURCE_EVENT,
521 /* Debug log buffer status changed */
522 SOF_IPC4_NOTIFY_LOG_BUFFER_STATUS,
523 /* Timestamp captured at the link */
524 SOF_IPC4_NOTIFY_TIMESTAMP_CAPTURED,
525 /* FW complete initialization */
526 SOF_IPC4_NOTIFY_FW_READY,
527 /* Audio classifier result (ACA) */
528 SOF_IPC4_NOTIFY_FW_AUD_CLASS_RESULT,
529 /* Exception caught by DSP FW */
530 SOF_IPC4_NOTIFY_EXCEPTION_CAUGHT,
531 /* 11 is skipped by the existing cavs firmware */
532 /* Custom module notification */
533 SOF_IPC4_NOTIFY_MODULE_NOTIFICATION = 12,
534 /* 13 is reserved - do not use */
535 /* Probe notify data available */
536 SOF_IPC4_NOTIFY_PROBE_DATA_AVAILABLE = 14,
537 /* AM module notifications */
538 SOF_IPC4_NOTIFY_ASYNC_MSG_SRVC_MESSAGE,
539
540 SOF_IPC4_NOTIFY_TYPE_LAST,
541};
542
543enum sof_ipc4_resource_type {
544 SOF_IPC4_MODULE_INSTANCE,
545 SOF_IPC4_PIPELINE,
546 SOF_IPC4_GATEWAY,
547 SOF_IPC4_EDF_TASK,
548 SOF_IPC4_INVALID_RESOURCE_TYPE,
549};
550
551enum sof_ipc4_event_type {
552 /* Underrun detected by the Mixer */
553 SOF_IPC4_MIXER_UNDERRUN_DETECTED = 1,
554 /* Error caught during data processing */
555 SOF_IPC4_PROCESS_DATA_ERROR = 3,
556 /* Underrun detected by gateway. */
557 SOF_IPC4_GATEWAY_UNDERRUN_DETECTED = 6,
558 /* Overrun detected by gateway */
559 SOF_IPC4_GATEWAY_OVERRUN_DETECTED,
560};
561
562/**
563 * struct sof_ipc4_process_data_error_event_data - process data error event payload
564 * @error_code: Error code returned by data processing function
565 */
566struct sof_ipc4_process_data_error_event_data {
567 uint32_t error_code;
568};
569
570/**
571 * struct sof_ipc4_mixer_underrun_event_data - mixer underrun event payload
572 * @eos_flag: Indicates EndOfStream
573 * @data_mixed: Data processed by module (in bytes)
574 * @expected_data_mixed: Expected data to be processed (in bytes)
575 */
576struct sof_ipc4_mixer_underrun_event_data {
577 uint32_t eos_flag;
578 uint32_t data_mixed;
579 uint32_t expected_data_mixed;
580};
581
582/**
583 * union sof_ipc4_resource_event_data - resource event specific payload
584 * @dws: Raw event data payload as six dwords
585 * @process_data_error: SOF_IPC4_PROCESS_DATA_ERROR payload
586 * @mixer_underrun: SOF_IPC4_MIXER_UNDERRUN_DETECTED payload
587 */
588union sof_ipc4_resource_event_data {
589 uint32_t dws[6];
590 struct sof_ipc4_process_data_error_event_data process_data_error;
591 struct sof_ipc4_mixer_underrun_event_data mixer_underrun;
592};
593
594struct sof_ipc4_notify_resource_data {
595 uint32_t resource_type;
596 uint32_t resource_id;
597 uint32_t event_type;
598 uint32_t reserved;
599 union sof_ipc4_resource_event_data data;
600} __packed __aligned(4);
601
602#define SOF_IPC4_DEBUG_DESCRIPTOR_SIZE 12 /* 3 x u32 */
603
604/*
605 * The debug memory window is divided into 16 slots, and the
606 * first slot is used as a recorder for the other 15 slots.
607 */
608#define SOF_IPC4_MAX_DEBUG_SLOTS 15
609#define SOF_IPC4_DEBUG_SLOT_SIZE 0x1000
610
611/* debug log slot types */
612#define SOF_IPC4_DEBUG_SLOT_UNUSED 0x00000000
613#define SOF_IPC4_DEBUG_SLOT_CRITICAL_LOG 0x54524300 /* byte 0: core ID */
614#define SOF_IPC4_DEBUG_SLOT_DEBUG_LOG 0x474f4c00 /* byte 0: core ID */
615#define SOF_IPC4_DEBUG_SLOT_GDB_STUB 0x42444700
616#define SOF_IPC4_DEBUG_SLOT_TELEMETRY 0x4c455400
617#define SOF_IPC4_DEBUG_SLOT_BROKEN 0x44414544
618
619/**
620 * struct sof_ipc4_notify_module_data - payload for module notification
621 * @instance_id: instance ID of the originator module of the notification
622 * @module_id: module ID of the originator of the notification
623 * @event_id: module specific event id
624 * @event_data_size: Size of the @event_data (if any) in bytes
625 * @event_data: Optional notification data, module and notification dependent
626 */
627struct sof_ipc4_notify_module_data {
628 uint16_t instance_id;
629 uint16_t module_id;
630 uint32_t event_id;
631 uint32_t event_data_size;
632 uint8_t event_data[];
633} __packed __aligned(4);
634
635/*
636 * ALSA kcontrol change notification
637 *
638 * The event_id of struct sof_ipc4_notify_module_data is divided into two u16:
639 * upper u16: magic number for ALSA kcontrol types: 0xA15A
640 * lower u16: param_id of the control, which is the type of the control
641 * The event_data contains the struct sof_ipc4_control_msg_payload of the control
642 * which sent the notification.
643 */
644#define SOF_IPC4_NOTIFY_MODULE_EVENTID_ALSA_MAGIC_MASK GENMASK(31, 16)
645#define SOF_IPC4_NOTIFY_MODULE_EVENTID_ALSA_MAGIC_VAL 0xA15A0000
646#define SOF_IPC4_NOTIFY_MODULE_EVENTID_ALSA_PARAMID_MASK GENMASK(15, 0)
647
648/*
649 * Macros for creating struct sof_ipc4_module_init_ext_init payload
650 * with its associated data. ext_init payload should be the first
651 * piece of payload following SOF_IPC4_MOD_INIT_INSTANCE msg, and its
652 * existence is indicated with SOF_IPC4_MOD_EXT_EXTENDED-bit.
653 *
654 * The macros below apply to sof_ipc4_module_init_ext_init.word0
655 */
656#define SOF_IPC4_MOD_INIT_EXT_RTOS_DOMAIN_SHIFT 0
657#define SOF_IPC4_MOD_INIT_EXT_RTOS_DOMAIN_MASK BIT(0)
658#define SOF_IPC4_MOD_INIT_EXT_RTOS_DOMAIN(x) ((x) << SOF_IPC4_MOD_INIT_EXT_RTOS_DOMAIN_SHIFT)
659
660#define SOF_IPC4_MOD_INIT_EXT_GNA_USED_SHIFT 1
661#define SOF_IPC4_MOD_INIT_EXT_GNA_USED_MASK BIT(1)
662#define SOF_IPC4_MOD_INIT_EXT_GNA_USED(x) ((x) << SOF_IPC4_MOD_INIT_EXT_GNA_USED_SHIFT)
663
664#define SOF_IPC4_MOD_INIT_EXT_OBJ_ARRAY_SHIFT 2
665#define SOF_IPC4_MOD_INIT_EXT_OBJ_ARRAY_MASK BIT(2)
666#define SOF_IPC4_MOD_INIT_EXT_DATA_ARRAY(x) ((x) << SOF_IPC4_MOD_INIT_EXT_OBJ_ARRAY_SHIFT)
667
668struct sof_ipc4_module_init_ext_init {
669 u32 word0;
670 u32 rsvd1;
671 u32 rsvd2;
672} __packed __aligned(4);
673
674/*
675 * SOF_IPC4_MOD_EXT_EXTENDED payload may be followed by arbitrary
676 * number of object array objects. SOF_IPC4_MOD_INIT_EXT_DATA_ARRAY
677 * -bit indicates that an array object follows struct
678 * sof_ipc4_module_init_ext_init.
679 *
680 * The object header's SOF_IPC4_MOD_INIT_EXT_OBJ_LAST-bit in struct
681 * sof_ipc4_module_init_ext_object indicates if the array is continued
682 * with another object. The header has also fields to identify the
683 * object, SOF_IPC4_MOD_INIT_EXT_OBJ_ID, and to indicate the object's
684 * size in 32-bit words, SOF_IPC4_MOD_INIT_EXT_OBJ_WORDS, not
685 * including the header itself.
686 *
687 * The macros below apply to sof_ipc4_module_init_ext_object.header
688 */
689#define SOF_IPC4_MOD_INIT_EXT_OBJ_LAST_SHIFT 0
690#define SOF_IPC4_MOD_INIT_EXT_OBJ_LAST_MASK BIT(0)
691#define SOF_IPC4_MOD_INIT_EXT_OBJ_LAST(x) ((x) << SOF_IPC4_MOD_INIT_EXT_OBJ_LAST_SHIFT)
692
693#define SOF_IPC4_MOD_INIT_EXT_OBJ_ID_SHIFT 1
694#define SOF_IPC4_MOD_INIT_EXT_OBJ_ID_MASK GENMASK(15, 1)
695#define SOF_IPC4_MOD_INIT_EXT_OBJ_ID(x) ((x) << SOF_IPC4_MOD_INIT_EXT_OBJ_ID_SHIFT)
696
697#define SOF_IPC4_MOD_INIT_EXT_OBJ_WORDS_SHIFT 16
698#define SOF_IPC4_MOD_INIT_EXT_OBJ_WORDS_MASK GENMASK(31, 16)
699#define SOF_IPC4_MOD_INIT_EXT_OBJ_WORDS(x) ((x) << SOF_IPC4_MOD_INIT_EXT_OBJ_WORDS_SHIFT)
700
701struct sof_ipc4_module_init_ext_object {
702 u32 header;
703 u32 data[];
704} __packed __aligned(4);
705
706enum sof_ipc4_mod_init_ext_obj_id {
707 SOF_IPC4_MOD_INIT_DATA_ID_INVALID = 0,
708 SOF_IPC4_MOD_INIT_DATA_ID_DP_DATA,
709 SOF_IPC4_MOD_INIT_DATA_ID_MAX = SOF_IPC4_MOD_INIT_DATA_ID_DP_DATA,
710};
711
712/* DP module memory configuration data object for object array */
713struct sof_ipc4_mod_init_ext_dp_memory_data {
714 u32 domain_id; /* userspace domain ID */
715 u32 stack_bytes; /* required stack size in bytes */
716 u32 heap_bytes; /* required heap size in bytes */
717} __packed __aligned(4);
718
719/*
720 * This set of macros are very similar to the set above, but these are
721 * for building payload to SOF_IPC4_GLB_CREATE_PIPELINE message.
722 *
723 * Macros for creating struct sof_ipc4_glb_pipe_payload payload with
724 * its associated data. struct sof_ipc4_glb_pipe_payload should be the
725 * first piece of payload following SOF_IPC4_GLB_CREATE_PIPELINE msg,
726 * and its existence is indicated with SOF_IPC4_GLB_PIPE_PAYLOAD bit.
727 *
728 * The macros below apply to sof_ipc4_glb_pipe_payload.word0
729 */
730#define SOF_IPC4_GLB_PIPE_PAYLOAD_WORDS_SHIFT 0
731#define SOF_IPC4_GLB_PIPE_PAYLOAD_WORDS_MASK GENMASK(23, 0)
732#define SOF_IPC4_GLB_PIPE_PAYLOAD_WORDS(x) ((x) << SOF_IPC4_GLB_PIPE_PAYLOAD_WORDS_SHIFT)
733
734#define SOF_IPC4_GLB_PIPE_EXT_OBJ_ARRAY_SHIFT 24
735#define SOF_IPC4_GLB_PIPE_EXT_OBJ_ARRAY_MASK BIT(24)
736#define SOF_IPC4_GLB_PIPE_EXT_OBJ_ARRAY(x) ((x) << SOF_IPC4_GLB_PIPE_EXT_OBJ_ARRAY_SHIFT)
737
738struct sof_ipc4_glb_pipe_payload {
739 u32 word0;
740 u32 rsvd1;
741 u32 rsvd2;
742} __packed __aligned(4);
743
744/*
745 * SOF_IPC4_GLB_CREATE_PIPELINE payload may be followed by arbitrary
746 * number of object array objects. SOF_IPC4_GLB_PIPE_EXT_OBJ_ARRAY-bit
747 * indicates that an array object follows struct
748 * sof_ipc4_glb_pipe_payload.
749 *
750 * The object header's SOF_IPC4_GLB_PIPE_EXT_OBJ_LAST-bit in struct
751 * sof_ipc4_glb_pipe_ext_object indicates if the array is continued
752 * with another object. The header has also fields to identify the
753 * object, SOF_IPC4_GLB_PIPE_EXT_OBJ_ID, and to indicate the object's
754 * size in 32-bit words, SOF_IPC4_GLB_PIPE_EXT_OBJ_WORDS, not
755 * including the header itself.
756 *
757 * The macros below apply to sof_ipc4_glb_pipe_ext_object.header
758 */
759#define SOF_IPC4_GLB_PIPE_EXT_OBJ_LAST_SHIFT 0
760#define SOF_IPC4_GLB_PIPE_EXT_OBJ_LAST_MASK BIT(0)
761#define SOF_IPC4_GLB_PIPE_EXT_OBJ_LAST(x) ((x) << SOF_IPC4_GLB_PIPE_EXT_OBJ_LAST_SHIFT)
762
763#define SOF_IPC4_GLB_PIPE_EXT_OBJ_ID_SHIFT 1
764#define SOF_IPC4_GLB_PIPE_EXT_OBJ_ID_MASK GENMASK(15, 1)
765#define SOF_IPC4_GLB_PIPE_EXT_OBJ_ID(x) ((x) << SOF_IPC4_GLB_PIPE_EXT_OBJ_ID_SHIFT)
766
767#define SOF_IPC4_GLB_PIPE_EXT_OBJ_WORDS_SHIFT 16
768#define SOF_IPC4_GLB_PIPE_EXT_OBJ_WORDS_MASK GENMASK(31, 16)
769#define SOF_IPC4_GLB_PIPE_EXT_OBJ_WORDS(x) ((x) << SOF_IPC4_GLB_PIPE_EXT_OBJ_WORDS_SHIFT)
770
771struct sof_ipc4_glb_pipe_ext_object {
772 u32 header;
773 u32 data[];
774} __packed __aligned(4);
775
776enum sof_ipc4_glb_pipe_ext_obj_id {
777 SOF_IPC4_GLB_PIPE_DATA_ID_INVALID = 0,
778 SOF_IPC4_GLB_PIPE_DATA_ID_MEM_DATA,
779 SOF_IPC4_GLB_PIPE_DATA_ID_MAX = SOF_IPC4_GLB_PIPE_DATA_ID_MEM_DATA,
780};
781
782/* Pipeline memory configuration data object for ext_init object array */
783struct sof_ipc4_glb_pipe_ext_obj_memory_data {
784 u32 domain_id; /* userspace domain ID */
785 u32 stack_bytes; /* stack size in bytes */
786 u32 heap_bytes; /* heap size in bytes */
787} __packed __aligned(4);
788
789/** @}*/
790
791#endif