| 1 |
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| 2 | |
| 3 | * Copyright © 2023 Intel Corporation
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| 4 |
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| 5 |
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| 6 | #ifndef _UAPI_XE_DRM_H_
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| 7 | #define _UAPI_XE_DRM_H_
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| 8 |
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| 9 | #include "drm.h"
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| 10 |
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| 11 | #if defined(__cplusplus)
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| 12 | extern "C" {
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| 13 | #endif
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| 14 |
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| 15 | |
| 16 | * Please note that modifications to all structs defined here are
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| 17 | * subject to backwards-compatibility constraints.
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| 18 | * Sections in this file are organized as follows:
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| 19 | * 1. IOCTL definition
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| 20 | * 2. Extension definition and helper structs
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| 21 | * 3. IOCTL's Query structs in the order of the Query's entries.
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| 22 | * 4. The rest of IOCTL structs in the order of IOCTL declaration.
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| 23 |
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| 24 |
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| 25 | |
| 26 | * DOC: Xe Device Block Diagram
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| 27 | *
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| 28 | * The diagram below represents a high-level simplification of a discrete
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| 29 | * GPU supported by the Xe driver. It shows some device components which
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| 30 | * are necessary to understand this API, as well as how their relations
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| 31 | * to each other. This diagram does not represent real hardware::
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| 32 | *
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| 33 | * ┌──────────────────────────────────────────────────────────────────┐
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| 34 | * │ ┌──────────────────────────────────────────────────┐ ┌─────────┐ │
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| 35 | * │ │ ┌───────────────────────┐ ┌─────┐ │ │ ┌─────┐ │ │
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| 36 | * │ │ │ VRAM0 ├───┤ ... │ │ │ │VRAM1│ │ │
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| 37 | * │ │ └───────────┬───────────┘ └─GT1─┘ │ │ └──┬──┘ │ │
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| 38 | * │ │ ┌──────────────────┴───────────────────────────┐ │ │ ┌──┴──┐ │ │
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| 39 | * │ │ │ ┌─────────────────────┐ ┌─────────────────┐ │ │ │ │ │ │ │
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| 40 | * │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │
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| 41 | * │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │RCS0 │ │BCS0 │ │ │ │ │ │ │ │ │
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| 42 | * │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │
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| 43 | * │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │
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| 44 | * │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │VCS0 │ │VCS1 │ │ │ │ │ │ │ │ │
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| 45 | * │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │
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| 46 | * │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │
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| 47 | * │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │VECS0│ │VECS1│ │ │ │ │ │ ... │ │ │
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| 48 | * │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │
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| 49 | * │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │
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| 50 | * │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │CCS0 │ │CCS1 │ │ │ │ │ │ │ │ │
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| 51 | * │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │
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| 52 | * │ │ │ └─────────DSS─────────┘ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │
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| 53 | * │ │ │ │ │CCS2 │ │CCS3 │ │ │ │ │ │ │ │ │
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| 54 | * │ │ │ ┌─────┐ ┌─────┐ ┌─────┐ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │
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| 55 | * │ │ │ │ ... │ │ ... │ │ ... │ │ │ │ │ │ │ │ │ │
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| 56 | * │ │ │ └─DSS─┘ └─DSS─┘ └─DSS─┘ └─────Engines─────┘ │ │ │ │ │ │ │
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| 57 | * │ │ └───────────────────────────GT0────────────────┘ │ │ └─GT2─┘ │ │
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| 58 | * │ └────────────────────────────Tile0─────────────────┘ └─ Tile1──┘ │
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| 59 | * └─────────────────────────────Device0───────┬──────────────────────┘
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| 60 | * │
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| 61 | * ───────────────────────┴────────── PCI bus
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| 62 |
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| 63 |
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| 64 | |
| 65 | * DOC: Xe uAPI Overview
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| 66 | *
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| 67 | * This section aims to describe the Xe's IOCTL entries, its structs, and other
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| 68 | * Xe related uAPI such as uevents and PMU (Platform Monitoring Unit) related
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| 69 | * entries and usage.
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| 70 | *
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| 71 | * List of supported IOCTLs:
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| 72 | * - &DRM_IOCTL_XE_DEVICE_QUERY
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| 73 | * - &DRM_IOCTL_XE_GEM_CREATE
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| 74 | * - &DRM_IOCTL_XE_GEM_MMAP_OFFSET
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| 75 | * - &DRM_IOCTL_XE_VM_CREATE
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| 76 | * - &DRM_IOCTL_XE_VM_DESTROY
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| 77 | * - &DRM_IOCTL_XE_VM_BIND
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| 78 | * - &DRM_IOCTL_XE_EXEC_QUEUE_CREATE
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| 79 | * - &DRM_IOCTL_XE_EXEC_QUEUE_DESTROY
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| 80 | * - &DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY
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| 81 | * - &DRM_IOCTL_XE_EXEC
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| 82 | * - &DRM_IOCTL_XE_WAIT_USER_FENCE
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| 83 | * - &DRM_IOCTL_XE_OBSERVATION
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| 84 | * - &DRM_IOCTL_XE_MADVISE
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| 85 | * - &DRM_IOCTL_XE_VM_QUERY_MEM_RANGE_ATTRS
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| 86 | * - &DRM_IOCTL_XE_EXEC_QUEUE_SET_PROPERTY
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| 87 | * - &DRM_IOCTL_XE_VM_GET_PROPERTY
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| 88 |
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| 89 |
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| 90 | |
| 91 | * xe specific ioctls.
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| 92 | *
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| 93 | * The device specific ioctl range is [DRM_COMMAND_BASE, DRM_COMMAND_END) ie
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| 94 | * [0x40, 0xa0) (a0 is excluded). The numbers below are defined as offset
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| 95 | * against DRM_COMMAND_BASE and should be between [0x0, 0x60).
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| 96 |
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| 97 | #define DRM_XE_DEVICE_QUERY 0x00
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| 98 | #define DRM_XE_GEM_CREATE 0x01
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| 99 | #define DRM_XE_GEM_MMAP_OFFSET 0x02
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| 100 | #define DRM_XE_VM_CREATE 0x03
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| 101 | #define DRM_XE_VM_DESTROY 0x04
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| 102 | #define DRM_XE_VM_BIND 0x05
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| 103 | #define DRM_XE_EXEC_QUEUE_CREATE 0x06
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| 104 | #define DRM_XE_EXEC_QUEUE_DESTROY 0x07
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| 105 | #define DRM_XE_EXEC_QUEUE_GET_PROPERTY 0x08
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| 106 | #define DRM_XE_EXEC 0x09
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| 107 | #define DRM_XE_WAIT_USER_FENCE 0x0a
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| 108 | #define DRM_XE_OBSERVATION 0x0b
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| 109 | #define DRM_XE_MADVISE 0x0c
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| 110 | #define DRM_XE_VM_QUERY_MEM_RANGE_ATTRS 0x0d
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| 111 | #define DRM_XE_EXEC_QUEUE_SET_PROPERTY 0x0e
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| 112 | #define DRM_XE_VM_GET_PROPERTY 0x0f
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| 113 |
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| 114 |
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| 115 |
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| 116 | #define DRM_IOCTL_XE_DEVICE_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_DEVICE_QUERY, struct drm_xe_device_query)
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| 117 | #define DRM_IOCTL_XE_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_GEM_CREATE, struct drm_xe_gem_create)
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| 118 | #define DRM_IOCTL_XE_GEM_MMAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_GEM_MMAP_OFFSET, struct drm_xe_gem_mmap_offset)
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| 119 | #define DRM_IOCTL_XE_VM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_VM_CREATE, struct drm_xe_vm_create)
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| 120 | #define DRM_IOCTL_XE_VM_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_DESTROY, struct drm_xe_vm_destroy)
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| 121 | #define DRM_IOCTL_XE_VM_BIND DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_BIND, struct drm_xe_vm_bind)
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| 122 | #define DRM_IOCTL_XE_EXEC_QUEUE_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_CREATE, struct drm_xe_exec_queue_create)
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| 123 | #define DRM_IOCTL_XE_EXEC_QUEUE_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_DESTROY, struct drm_xe_exec_queue_destroy)
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| 124 | #define DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_GET_PROPERTY, struct drm_xe_exec_queue_get_property)
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| 125 | #define DRM_IOCTL_XE_EXEC DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC, struct drm_xe_exec)
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| 126 | #define DRM_IOCTL_XE_WAIT_USER_FENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_WAIT_USER_FENCE, struct drm_xe_wait_user_fence)
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| 127 | #define DRM_IOCTL_XE_OBSERVATION DRM_IOW(DRM_COMMAND_BASE + DRM_XE_OBSERVATION, struct drm_xe_observation_param)
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| 128 | #define DRM_IOCTL_XE_MADVISE DRM_IOW(DRM_COMMAND_BASE + DRM_XE_MADVISE, struct drm_xe_madvise)
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| 129 | #define DRM_IOCTL_XE_VM_QUERY_MEM_RANGE_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_VM_QUERY_MEM_RANGE_ATTRS, struct drm_xe_vm_query_mem_range_attr)
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| 130 | #define DRM_IOCTL_XE_EXEC_QUEUE_SET_PROPERTY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_SET_PROPERTY, struct drm_xe_exec_queue_set_property)
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| 131 | #define DRM_IOCTL_XE_VM_GET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_VM_GET_PROPERTY, struct drm_xe_vm_get_property)
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| 132 |
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| 133 | |
| 134 | * DOC: Xe IOCTL Extensions
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| 135 | *
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| 136 | * Before detailing the IOCTLs and its structs, it is important to highlight
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| 137 | * that every IOCTL in Xe is extensible.
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| 138 | *
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| 139 | * Many interfaces need to grow over time. In most cases we can simply
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| 140 | * extend the struct and have userspace pass in more data. Another option,
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| 141 | * as demonstrated by Vulkan's approach to providing extensions for forward
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| 142 | * and backward compatibility, is to use a list of optional structs to
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| 143 | * provide those extra details.
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| 144 | *
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| 145 | * The key advantage to using an extension chain is that it allows us to
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| 146 | * redefine the interface more easily than an ever growing struct of
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| 147 | * increasing complexity, and for large parts of that interface to be
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| 148 | * entirely optional. The downside is more pointer chasing; chasing across
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| 149 | * the __user boundary with pointers encapsulated inside u64.
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| 150 | *
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| 151 | * Example chaining:
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| 152 | *
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| 153 | * .. code-block:: C
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| 154 | *
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| 155 | * struct drm_xe_user_extension ext3 {
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| 156 | * .next_extension = 0, // end
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| 157 | * .name = ...,
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| 158 | * };
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| 159 | * struct drm_xe_user_extension ext2 {
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| 160 | * .next_extension = (uintptr_t)&ext3,
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| 161 | * .name = ...,
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| 162 | * };
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| 163 | * struct drm_xe_user_extension ext1 {
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| 164 | * .next_extension = (uintptr_t)&ext2,
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| 165 | * .name = ...,
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| 166 | * };
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| 167 | *
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| 168 | * Typically the struct drm_xe_user_extension would be embedded in some uAPI
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| 169 | * struct, and in this case we would feed it the head of the chain(i.e ext1),
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| 170 | * which would then apply all of the above extensions.
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| 171 |
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| 172 |
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| 173 | |
| 174 | * struct drm_xe_user_extension - Base class for defining a chain of extensions
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| 175 |
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| 176 | struct drm_xe_user_extension {
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| 177 | |
| 178 | * @next_extension:
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| 179 | *
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| 180 | * Pointer to the next struct drm_xe_user_extension, or zero if the end.
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| 181 |
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| 182 | __u64 next_extension;
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| 183 |
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| 184 | |
| 185 | * @name: Name of the extension.
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| 186 | *
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| 187 | * Note that the name here is just some integer.
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| 188 | *
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| 189 | * Also note that the name space for this is not global for the whole
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| 190 | * driver, but rather its scope/meaning is limited to the specific piece
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| 191 | * of uAPI which has embedded the struct drm_xe_user_extension.
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| 192 |
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| 193 | __u32 name;
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| 194 |
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| 195 | |
| 196 | * @pad: MBZ
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| 197 | *
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| 198 | * All undefined bits must be zero.
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| 199 |
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| 200 | __u32 pad;
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| 201 | };
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| 202 |
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| 203 | |
| 204 | * struct drm_xe_ext_set_property - Generic set property extension
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| 205 | *
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| 206 | * A generic struct that allows any of the Xe's IOCTL to be extended
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| 207 | * with a set_property operation.
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| 208 |
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| 209 | struct drm_xe_ext_set_property {
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| 210 |
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| 211 | struct drm_xe_user_extension base;
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| 212 |
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| 213 |
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| 214 | __u32 property;
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| 215 |
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| 216 |
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| 217 | __u32 pad;
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| 218 |
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| 219 | union {
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| 220 |
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| 221 | __u64 value;
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| 222 |
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| 223 | __u64 ptr;
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| 224 | };
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| 225 |
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| 226 |
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| 227 | __u64 reserved[2];
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| 228 | };
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| 229 |
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| 230 | |
| 231 | * struct drm_xe_engine_class_instance - instance of an engine class
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| 232 | *
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| 233 | * It is returned as part of the &struct drm_xe_engine, but it also is used as
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| 234 | * the input of engine selection for both &struct drm_xe_exec_queue_create and
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| 235 | * &struct drm_xe_query_engine_cycles
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| 236 | *
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| 237 | * The @engine_class can be:
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| 238 | * - %DRM_XE_ENGINE_CLASS_RENDER
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| 239 | * - %DRM_XE_ENGINE_CLASS_COPY
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| 240 | * - %DRM_XE_ENGINE_CLASS_VIDEO_DECODE
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| 241 | * - %DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE
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| 242 | * - %DRM_XE_ENGINE_CLASS_COMPUTE
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| 243 | * - %DRM_XE_ENGINE_CLASS_VM_BIND - Kernel only classes (not actual
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| 244 | * hardware engine class). Used for creating ordered queues of VM
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| 245 | * bind operations.
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| 246 |
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| 247 | struct drm_xe_engine_class_instance {
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| 248 | #define DRM_XE_ENGINE_CLASS_RENDER 0
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| 249 | #define DRM_XE_ENGINE_CLASS_COPY 1
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| 250 | #define DRM_XE_ENGINE_CLASS_VIDEO_DECODE 2
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| 251 | #define DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE 3
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| 252 | #define DRM_XE_ENGINE_CLASS_COMPUTE 4
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| 253 | #define DRM_XE_ENGINE_CLASS_VM_BIND 5
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| 254 |
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| 255 | __u16 engine_class;
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| 256 |
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| 257 | __u16 engine_instance;
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| 258 |
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| 259 | __u16 gt_id;
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| 260 |
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| 261 | __u16 pad;
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| 262 | };
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| 263 |
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| 264 | |
| 265 | * struct drm_xe_engine - describe hardware engine
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| 266 |
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| 267 | struct drm_xe_engine {
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| 268 |
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| 269 | struct drm_xe_engine_class_instance instance;
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| 270 |
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| 271 |
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| 272 | __u64 reserved[3];
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| 273 | };
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| 274 |
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| 275 | |
| 276 | * struct drm_xe_query_engines - describe engines
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| 277 | *
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| 278 | * If a query is made with a &struct drm_xe_device_query where .query
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| 279 | * is equal to %DRM_XE_DEVICE_QUERY_ENGINES, then the reply uses an array of
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| 280 | * &struct drm_xe_query_engines in .data.
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| 281 |
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| 282 | struct drm_xe_query_engines {
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| 283 |
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| 284 | __u32 num_engines;
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| 285 |
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| 286 | __u32 pad;
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| 287 |
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| 288 | struct drm_xe_engine engines[];
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| 289 | };
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| 290 |
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| 291 | |
| 292 | * enum drm_xe_memory_class - Supported memory classes.
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| 293 |
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| 294 | enum drm_xe_memory_class {
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| 295 |
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| 296 | DRM_XE_MEM_REGION_CLASS_SYSMEM = 0,
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| 297 | |
| 298 | * @DRM_XE_MEM_REGION_CLASS_VRAM: On discrete platforms, this
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| 299 | * represents the memory that is local to the device, which we
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| 300 | * call VRAM. Not valid on integrated platforms.
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| 301 |
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| 302 | DRM_XE_MEM_REGION_CLASS_VRAM
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| 303 | };
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| 304 |
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| 305 | |
| 306 | * struct drm_xe_mem_region - Describes some region as known to
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| 307 | * the driver.
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| 308 |
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| 309 | struct drm_xe_mem_region {
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| 310 | |
| 311 | * @mem_class: The memory class describing this region.
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| 312 | *
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| 313 | * See enum drm_xe_memory_class for supported values.
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| 314 |
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| 315 | __u16 mem_class;
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| 316 | |
| 317 | * @instance: The unique ID for this region, which serves as the
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| 318 | * index in the placement bitmask used as argument for
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| 319 | * &DRM_IOCTL_XE_GEM_CREATE
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| 320 |
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| 321 | __u16 instance;
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| 322 | |
| 323 | * @min_page_size: Min page-size in bytes for this region.
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| 324 | *
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| 325 | * When the kernel allocates memory for this region, the
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| 326 | * underlying pages will be at least @min_page_size in size.
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| 327 | * Buffer objects with an allowable placement in this region must be
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| 328 | * created with a size aligned to this value.
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| 329 | * GPU virtual address mappings of (parts of) buffer objects that
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| 330 | * may be placed in this region must also have their GPU virtual
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| 331 | * address and range aligned to this value.
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| 332 | * Affected IOCTLS will return %-EINVAL if alignment restrictions are
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| 333 | * not met.
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| 334 |
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| 335 | __u32 min_page_size;
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| 336 | |
| 337 | * @total_size: The usable size in bytes for this region.
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| 338 |
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| 339 | __u64 total_size;
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| 340 | |
| 341 | * @used: Estimate of the memory used in bytes for this region.
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| 342 |
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| 343 | __u64 used;
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| 344 | |
| 345 | * @cpu_visible_size: How much of this region can be CPU
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| 346 | * accessed, in bytes.
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| 347 | *
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| 348 | * This will always be <= @total_size, and the remainder (if
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| 349 | * any) will not be CPU accessible. If the CPU accessible part
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| 350 | * is smaller than @total_size then this is referred to as a
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| 351 | * small BAR system.
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| 352 | *
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| 353 | * On systems without small BAR (full BAR), the @cpu_visible_size will
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| 354 | * always equal the @total_size, since all of it will be CPU
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| 355 | * accessible.
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| 356 | *
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| 357 | * Note this is only tracked for DRM_XE_MEM_REGION_CLASS_VRAM
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| 358 | * regions (for other types the value here will always equal
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| 359 | * zero).
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| 360 |
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| 361 | __u64 cpu_visible_size;
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| 362 | |
| 363 | * @cpu_visible_used: Estimate of CPU visible memory used, in
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| 364 | * bytes.
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| 365 | *
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| 366 | * Note this is only currently tracked for
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| 367 | * DRM_XE_MEM_REGION_CLASS_VRAM regions (for other types the value
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| 368 | * here will always be zero).
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| 369 |
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| 370 | __u64 cpu_visible_used;
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| 371 |
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| 372 | __u64 reserved[6];
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| 373 | };
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| 374 |
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| 375 | |
| 376 | * struct drm_xe_query_mem_regions - describe memory regions
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| 377 | *
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| 378 | * If a query is made with a struct drm_xe_device_query where .query
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| 379 | * is equal to DRM_XE_DEVICE_QUERY_MEM_REGIONS, then the reply uses
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| 380 | * struct drm_xe_query_mem_regions in .data.
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| 381 |
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| 382 | struct drm_xe_query_mem_regions {
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| 383 |
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| 384 | __u32 num_mem_regions;
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| 385 |
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| 386 | __u32 pad;
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| 387 |
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| 388 | struct drm_xe_mem_region mem_regions[];
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| 389 | };
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| 390 |
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| 391 | |
| 392 | * struct drm_xe_query_config - describe the device configuration
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| 393 | *
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| 394 | * If a query is made with a struct drm_xe_device_query where .query
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| 395 | * is equal to DRM_XE_DEVICE_QUERY_CONFIG, then the reply uses
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| 396 | * struct drm_xe_query_config in .data.
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| 397 | *
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| 398 | * The index in @info can be:
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| 399 | * - %DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID - Device ID (lower 16 bits)
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| 400 | * and the device revision (next 8 bits)
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| 401 | * - %DRM_XE_QUERY_CONFIG_FLAGS - Flags describing the device
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| 402 | * configuration, see list below
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| 403 | *
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| 404 | * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM - Flag is set if the device
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| 405 | * has usable VRAM
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| 406 | * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY - Flag is set if the device
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| 407 | * has low latency hint support
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| 408 | * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR - Flag is set if the
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| 409 | * device has CPU address mirroring support
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| 410 | * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_NO_COMPRESSION_HINT - Flag is set if the
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| 411 | * device supports the userspace hint %DRM_XE_GEM_CREATE_FLAG_NO_COMPRESSION.
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| 412 | * This is exposed only on Xe2+.
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| 413 | * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_DISABLE_STATE_CACHE_PERF_FIX - Flag is set
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| 414 | * if a queue can be created with
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| 415 | * %DRM_XE_EXEC_QUEUE_SET_DISABLE_STATE_CACHE_PERF_FIX
|
| 416 | * - %DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT - Minimal memory alignment
|
| 417 | * required by this device, typically SZ_4K or SZ_64K
|
| 418 | * - %DRM_XE_QUERY_CONFIG_VA_BITS - Maximum bits of a virtual address
|
| 419 | * - %DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY - Value of the highest
|
| 420 | * available exec queue priority
|
| 421 |
|
| 422 | struct drm_xe_query_config {
|
| 423 |
|
| 424 | __u32 num_params;
|
| 425 |
|
| 426 |
|
| 427 | __u32 pad;
|
| 428 |
|
| 429 | #define DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID 0
|
| 430 | #define DRM_XE_QUERY_CONFIG_FLAGS 1
|
| 431 | #define DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM (1 << 0)
|
| 432 | #define DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY (1 << 1)
|
| 433 | #define DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR (1 << 2)
|
| 434 | #define DRM_XE_QUERY_CONFIG_FLAG_HAS_NO_COMPRESSION_HINT (1 << 3)
|
| 435 | #define DRM_XE_QUERY_CONFIG_FLAG_HAS_DISABLE_STATE_CACHE_PERF_FIX (1 << 4)
|
| 436 | #define DRM_XE_QUERY_CONFIG_FLAG_HAS_PURGING_SUPPORT (1 << 5)
|
| 437 | #define DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT 2
|
| 438 | #define DRM_XE_QUERY_CONFIG_VA_BITS 3
|
| 439 | #define DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY 4
|
| 440 |
|
| 441 | __u64 info[];
|
| 442 | };
|
| 443 |
|
| 444 | |
| 445 | * struct drm_xe_gt - describe an individual GT.
|
| 446 | *
|
| 447 | * To be used with drm_xe_query_gt_list, which will return a list with all the
|
| 448 | * existing GT individual descriptions.
|
| 449 | * Graphics Technology (GT) is a subset of a GPU/tile that is responsible for
|
| 450 | * implementing graphics and/or media operations.
|
| 451 | *
|
| 452 | * The index in @type can be:
|
| 453 | * - %DRM_XE_QUERY_GT_TYPE_MAIN
|
| 454 | * - %DRM_XE_QUERY_GT_TYPE_MEDIA
|
| 455 |
|
| 456 | struct drm_xe_gt {
|
| 457 | #define DRM_XE_QUERY_GT_TYPE_MAIN 0
|
| 458 | #define DRM_XE_QUERY_GT_TYPE_MEDIA 1
|
| 459 |
|
| 460 | __u16 type;
|
| 461 |
|
| 462 | __u16 tile_id;
|
| 463 |
|
| 464 | __u16 gt_id;
|
| 465 |
|
| 466 | __u16 pad[3];
|
| 467 |
|
| 468 | __u32 reference_clock;
|
| 469 | |
| 470 | * @near_mem_regions: Bit mask of instances from
|
| 471 | * drm_xe_query_mem_regions that are nearest to the current engines
|
| 472 | * of this GT.
|
| 473 | * Each index in this mask refers directly to the struct
|
| 474 | * drm_xe_query_mem_regions' instance, no assumptions should
|
| 475 | * be made about order. The type of each region is described
|
| 476 | * by struct drm_xe_query_mem_regions' mem_class.
|
| 477 |
|
| 478 | __u64 near_mem_regions;
|
| 479 | |
| 480 | * @far_mem_regions: Bit mask of instances from
|
| 481 | * drm_xe_query_mem_regions that are far from the engines of this GT.
|
| 482 | * In general, they have extra indirections when compared to the
|
| 483 | * @near_mem_regions. For a discrete device this could mean system
|
| 484 | * memory and memory living in a different tile.
|
| 485 | * Each index in this mask refers directly to the struct
|
| 486 | * drm_xe_query_mem_regions' instance, no assumptions should
|
| 487 | * be made about order. The type of each region is described
|
| 488 | * by struct drm_xe_query_mem_regions' mem_class.
|
| 489 |
|
| 490 | __u64 far_mem_regions;
|
| 491 |
|
| 492 | __u16 ip_ver_major;
|
| 493 |
|
| 494 | __u16 ip_ver_minor;
|
| 495 |
|
| 496 | __u16 ip_ver_rev;
|
| 497 |
|
| 498 | __u16 pad2;
|
| 499 |
|
| 500 | __u64 reserved[7];
|
| 501 | };
|
| 502 |
|
| 503 | |
| 504 | * struct drm_xe_query_gt_list - A list with GT description items.
|
| 505 | *
|
| 506 | * If a query is made with a struct drm_xe_device_query where .query
|
| 507 | * is equal to DRM_XE_DEVICE_QUERY_GT_LIST, then the reply uses struct
|
| 508 | * drm_xe_query_gt_list in .data.
|
| 509 |
|
| 510 | struct drm_xe_query_gt_list {
|
| 511 |
|
| 512 | __u32 num_gt;
|
| 513 |
|
| 514 | __u32 pad;
|
| 515 |
|
| 516 | struct drm_xe_gt gt_list[];
|
| 517 | };
|
| 518 |
|
| 519 | |
| 520 | * struct drm_xe_query_topology_mask - describe the topology mask of a GT
|
| 521 | *
|
| 522 | * This is the hardware topology which reflects the internal physical
|
| 523 | * structure of the GPU.
|
| 524 | *
|
| 525 | * If a query is made with a struct drm_xe_device_query where .query
|
| 526 | * is equal to DRM_XE_DEVICE_QUERY_GT_TOPOLOGY, then the reply uses
|
| 527 | * struct drm_xe_query_topology_mask in .data.
|
| 528 | *
|
| 529 | * The @type can be:
|
| 530 | * - %DRM_XE_TOPO_DSS_GEOMETRY - To query the mask of Dual Sub Slices
|
| 531 | * (DSS) available for geometry operations. For example a query response
|
| 532 | * containing the following in mask:
|
| 533 | * ``DSS_GEOMETRY ff ff ff ff 00 00 00 00``
|
| 534 | * means 32 DSS are available for geometry.
|
| 535 | * - %DRM_XE_TOPO_DSS_COMPUTE - To query the mask of Dual Sub Slices
|
| 536 | * (DSS) available for compute operations. For example a query response
|
| 537 | * containing the following in mask:
|
| 538 | * ``DSS_COMPUTE ff ff ff ff 00 00 00 00``
|
| 539 | * means 32 DSS are available for compute.
|
| 540 | * - %DRM_XE_TOPO_L3_BANK - To query the mask of enabled L3 banks. This type
|
| 541 | * may be omitted if the driver is unable to query the mask from the
|
| 542 | * hardware.
|
| 543 | * - %DRM_XE_TOPO_EU_PER_DSS - To query the mask of Execution Units (EU)
|
| 544 | * available per Dual Sub Slices (DSS). For example a query response
|
| 545 | * containing the following in mask:
|
| 546 | * ``EU_PER_DSS ff ff 00 00 00 00 00 00``
|
| 547 | * means each DSS has 16 SIMD8 EUs. This type may be omitted if device
|
| 548 | * doesn't have SIMD8 EUs.
|
| 549 | * - %DRM_XE_TOPO_SIMD16_EU_PER_DSS - To query the mask of SIMD16 Execution
|
| 550 | * Units (EU) available per Dual Sub Slices (DSS). For example a query
|
| 551 | * response containing the following in mask:
|
| 552 | * ``SIMD16_EU_PER_DSS ff ff 00 00 00 00 00 00``
|
| 553 | * means each DSS has 16 SIMD16 EUs. This type may be omitted if device
|
| 554 | * doesn't have SIMD16 EUs.
|
| 555 |
|
| 556 | struct drm_xe_query_topology_mask {
|
| 557 |
|
| 558 | __u16 gt_id;
|
| 559 |
|
| 560 | #define DRM_XE_TOPO_DSS_GEOMETRY 1
|
| 561 | #define DRM_XE_TOPO_DSS_COMPUTE 2
|
| 562 | #define DRM_XE_TOPO_L3_BANK 3
|
| 563 | #define DRM_XE_TOPO_EU_PER_DSS 4
|
| 564 | #define DRM_XE_TOPO_SIMD16_EU_PER_DSS 5
|
| 565 |
|
| 566 | __u16 type;
|
| 567 |
|
| 568 |
|
| 569 | __u32 num_bytes;
|
| 570 |
|
| 571 |
|
| 572 | __u8 mask[];
|
| 573 | };
|
| 574 |
|
| 575 | |
| 576 | * struct drm_xe_query_engine_cycles - correlate CPU and GPU timestamps
|
| 577 | *
|
| 578 | * If a query is made with a struct drm_xe_device_query where .query is equal to
|
| 579 | * DRM_XE_DEVICE_QUERY_ENGINE_CYCLES, then the reply uses struct drm_xe_query_engine_cycles
|
| 580 | * in .data. struct drm_xe_query_engine_cycles is allocated by the user and
|
| 581 | * .data points to this allocated structure.
|
| 582 | *
|
| 583 | * The query returns the engine cycles, which along with GT's @reference_clock,
|
| 584 | * can be used to calculate the engine timestamp. In addition the
|
| 585 | * query returns a set of cpu timestamps that indicate when the command
|
| 586 | * streamer cycle count was captured.
|
| 587 |
|
| 588 | struct drm_xe_query_engine_cycles {
|
| 589 | |
| 590 | * @eci: This is input by the user and is the engine for which command
|
| 591 | * streamer cycles is queried.
|
| 592 |
|
| 593 | struct drm_xe_engine_class_instance eci;
|
| 594 |
|
| 595 | |
| 596 | * @clockid: This is input by the user and is the reference clock id for
|
| 597 | * CPU timestamp. For definition, see clock_gettime(2) and
|
| 598 | * perf_event_open(2). Supported clock ids are CLOCK_MONOTONIC,
|
| 599 | * CLOCK_MONOTONIC_RAW, CLOCK_REALTIME, CLOCK_BOOTTIME, CLOCK_TAI.
|
| 600 |
|
| 601 | __s32 clockid;
|
| 602 |
|
| 603 |
|
| 604 | __u32 width;
|
| 605 |
|
| 606 | |
| 607 | * @engine_cycles: Engine cycles as read from its register
|
| 608 | * at 0x358 offset.
|
| 609 |
|
| 610 | __u64 engine_cycles;
|
| 611 |
|
| 612 | |
| 613 | * @cpu_timestamp: CPU timestamp in ns. The timestamp is captured before
|
| 614 | * reading the engine_cycles register using the reference clockid set by the
|
| 615 | * user.
|
| 616 |
|
| 617 | __u64 cpu_timestamp;
|
| 618 |
|
| 619 | |
| 620 | * @cpu_delta: Time delta in ns captured around reading the lower dword
|
| 621 | * of the engine_cycles register.
|
| 622 |
|
| 623 | __u64 cpu_delta;
|
| 624 | };
|
| 625 |
|
| 626 | |
| 627 | * struct drm_xe_query_uc_fw_version - query a micro-controller firmware version
|
| 628 | *
|
| 629 | * Given a uc_type this will return the branch, major, minor and patch version
|
| 630 | * of the micro-controller firmware.
|
| 631 |
|
| 632 | struct drm_xe_query_uc_fw_version {
|
| 633 |
|
| 634 | #define XE_QUERY_UC_TYPE_GUC_SUBMISSION 0
|
| 635 | #define XE_QUERY_UC_TYPE_HUC 1
|
| 636 | __u16 uc_type;
|
| 637 |
|
| 638 |
|
| 639 | __u16 pad;
|
| 640 |
|
| 641 |
|
| 642 | __u32 branch_ver;
|
| 643 |
|
| 644 | __u32 major_ver;
|
| 645 |
|
| 646 | __u32 minor_ver;
|
| 647 |
|
| 648 | __u32 patch_ver;
|
| 649 |
|
| 650 |
|
| 651 | __u32 pad2;
|
| 652 |
|
| 653 |
|
| 654 | __u64 reserved;
|
| 655 | };
|
| 656 |
|
| 657 | |
| 658 | * struct drm_xe_query_pxp_status - query if PXP is ready
|
| 659 | *
|
| 660 | * If PXP is enabled and no fatal error has occurred, the status will be set to
|
| 661 | * one of the following values:
|
| 662 | * 0: PXP init still in progress
|
| 663 | * 1: PXP init complete
|
| 664 | *
|
| 665 | * If PXP is not enabled or something has gone wrong, the query will be failed
|
| 666 | * with one of the following error codes:
|
| 667 | * -ENODEV: PXP not supported or disabled;
|
| 668 | * -EIO: fatal error occurred during init, so PXP will never be enabled;
|
| 669 | * -EINVAL: incorrect value provided as part of the query;
|
| 670 | * -EFAULT: error copying the memory between kernel and userspace.
|
| 671 | *
|
| 672 | * The status can only be 0 in the first few seconds after driver load. If
|
| 673 | * everything works as expected, the status will transition to init complete in
|
| 674 | * less than 1 second, while in case of errors the driver might take longer to
|
| 675 | * start returning an error code, but it should still take less than 10 seconds.
|
| 676 | *
|
| 677 | * The supported session type bitmask is based on the values in
|
| 678 | * enum drm_xe_pxp_session_type. TYPE_NONE is always supported and therefore
|
| 679 | * is not reported in the bitmask.
|
| 680 | *
|
| 681 |
|
| 682 | struct drm_xe_query_pxp_status {
|
| 683 |
|
| 684 | __u32 status;
|
| 685 |
|
| 686 |
|
| 687 | __u32 supported_session_types;
|
| 688 | };
|
| 689 |
|
| 690 | |
| 691 | * struct drm_xe_device_query - Input of &DRM_IOCTL_XE_DEVICE_QUERY - main
|
| 692 | * structure to query device information
|
| 693 | *
|
| 694 | * The user selects the type of data to query among DRM_XE_DEVICE_QUERY_*
|
| 695 | * and sets the value in the query member. This determines the type of
|
| 696 | * the structure provided by the driver in data, among struct drm_xe_query_*.
|
| 697 | *
|
| 698 | * The @query can be:
|
| 699 | * - %DRM_XE_DEVICE_QUERY_ENGINES
|
| 700 | * - %DRM_XE_DEVICE_QUERY_MEM_REGIONS
|
| 701 | * - %DRM_XE_DEVICE_QUERY_CONFIG
|
| 702 | * - %DRM_XE_DEVICE_QUERY_GT_LIST
|
| 703 | * - %DRM_XE_DEVICE_QUERY_HWCONFIG - Query type to retrieve the hardware
|
| 704 | * configuration of the device such as information on slices, memory,
|
| 705 | * caches, and so on. It is provided as a table of key / value
|
| 706 | * attributes.
|
| 707 | * - %DRM_XE_DEVICE_QUERY_GT_TOPOLOGY
|
| 708 | * - %DRM_XE_DEVICE_QUERY_ENGINE_CYCLES
|
| 709 | * - %DRM_XE_DEVICE_QUERY_UC_FW_VERSION
|
| 710 | * - %DRM_XE_DEVICE_QUERY_OA_UNITS
|
| 711 | * - %DRM_XE_DEVICE_QUERY_PXP_STATUS
|
| 712 | * - %DRM_XE_DEVICE_QUERY_EU_STALL
|
| 713 | *
|
| 714 | * If size is set to 0, the driver fills it with the required size for
|
| 715 | * the requested type of data to query. If size is equal to the required
|
| 716 | * size, the queried information is copied into data. If size is set to
|
| 717 | * a value different from 0 and different from the required size, the
|
| 718 | * IOCTL call returns -EINVAL.
|
| 719 | *
|
| 720 | * For example the following code snippet allows retrieving and printing
|
| 721 | * information about the device engines with DRM_XE_DEVICE_QUERY_ENGINES:
|
| 722 | *
|
| 723 | * .. code-block:: C
|
| 724 | *
|
| 725 | * struct drm_xe_query_engines *engines;
|
| 726 | * struct drm_xe_device_query query = {
|
| 727 | * .extensions = 0,
|
| 728 | * .query = DRM_XE_DEVICE_QUERY_ENGINES,
|
| 729 | * .size = 0,
|
| 730 | * .data = 0,
|
| 731 | * };
|
| 732 | * ioctl(fd, DRM_IOCTL_XE_DEVICE_QUERY, &query);
|
| 733 | * engines = malloc(query.size);
|
| 734 | * query.data = (uintptr_t)engines;
|
| 735 | * ioctl(fd, DRM_IOCTL_XE_DEVICE_QUERY, &query);
|
| 736 | * for (int i = 0; i < engines->num_engines; i++) {
|
| 737 | * printf("Engine %d: %s\n", i,
|
| 738 | * engines->engines[i].instance.engine_class ==
|
| 739 | * DRM_XE_ENGINE_CLASS_RENDER ? "RENDER":
|
| 740 | * engines->engines[i].instance.engine_class ==
|
| 741 | * DRM_XE_ENGINE_CLASS_COPY ? "COPY":
|
| 742 | * engines->engines[i].instance.engine_class ==
|
| 743 | * DRM_XE_ENGINE_CLASS_VIDEO_DECODE ? "VIDEO_DECODE":
|
| 744 | * engines->engines[i].instance.engine_class ==
|
| 745 | * DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE ? "VIDEO_ENHANCE":
|
| 746 | * engines->engines[i].instance.engine_class ==
|
| 747 | * DRM_XE_ENGINE_CLASS_COMPUTE ? "COMPUTE":
|
| 748 | * "UNKNOWN");
|
| 749 | * }
|
| 750 | * free(engines);
|
| 751 |
|
| 752 | struct drm_xe_device_query {
|
| 753 |
|
| 754 | __u64 extensions;
|
| 755 |
|
| 756 | #define DRM_XE_DEVICE_QUERY_ENGINES 0
|
| 757 | #define DRM_XE_DEVICE_QUERY_MEM_REGIONS 1
|
| 758 | #define DRM_XE_DEVICE_QUERY_CONFIG 2
|
| 759 | #define DRM_XE_DEVICE_QUERY_GT_LIST 3
|
| 760 | #define DRM_XE_DEVICE_QUERY_HWCONFIG 4
|
| 761 | #define DRM_XE_DEVICE_QUERY_GT_TOPOLOGY 5
|
| 762 | #define DRM_XE_DEVICE_QUERY_ENGINE_CYCLES 6
|
| 763 | #define DRM_XE_DEVICE_QUERY_UC_FW_VERSION 7
|
| 764 | #define DRM_XE_DEVICE_QUERY_OA_UNITS 8
|
| 765 | #define DRM_XE_DEVICE_QUERY_PXP_STATUS 9
|
| 766 | #define DRM_XE_DEVICE_QUERY_EU_STALL 10
|
| 767 |
|
| 768 | __u32 query;
|
| 769 |
|
| 770 |
|
| 771 | __u32 size;
|
| 772 |
|
| 773 |
|
| 774 | __u64 data;
|
| 775 |
|
| 776 |
|
| 777 | __u64 reserved[2];
|
| 778 | };
|
| 779 |
|
| 780 | |
| 781 | * struct drm_xe_gem_create - Input of &DRM_IOCTL_XE_GEM_CREATE - A structure for
|
| 782 | * gem creation
|
| 783 | *
|
| 784 | * The @flags can be:
|
| 785 | * - %DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING - Modify the GEM object
|
| 786 | * allocation strategy by deferring physical memory allocation
|
| 787 | * until the object is either bound to a virtual memory region via
|
| 788 | * VM_BIND or accessed by the CPU. As a result, no backing memory is
|
| 789 | * reserved at the time of GEM object creation.
|
| 790 | * - %DRM_XE_GEM_CREATE_FLAG_SCANOUT - Indicates that the GEM object is
|
| 791 | * intended for scanout via the display engine. When set, kernel ensures
|
| 792 | * that the allocation is placed in a memory region compatible with the
|
| 793 | * display engine requirements. This may impose restrictions on tiling,
|
| 794 | * alignment, and memory placement to guarantee proper display functionality.
|
| 795 | * - %DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM - When using VRAM as a
|
| 796 | * possible placement, ensure that the corresponding VRAM allocation
|
| 797 | * will always use the CPU accessible part of VRAM. This is important
|
| 798 | * for small-bar systems (on full-bar systems this gets turned into a
|
| 799 | * noop).
|
| 800 | * Note1: System memory can be used as an extra placement if the kernel
|
| 801 | * should spill the allocation to system memory, if space can't be made
|
| 802 | * available in the CPU accessible part of VRAM (giving the same
|
| 803 | * behaviour as the i915 interface, see
|
| 804 | * I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS).
|
| 805 | * Note2: For clear-color CCS surfaces the kernel needs to read the
|
| 806 | * clear-color value stored in the buffer, and on discrete platforms we
|
| 807 | * need to use VRAM for display surfaces, therefore the kernel requires
|
| 808 | * setting this flag for such objects, otherwise an error is thrown on
|
| 809 | * small-bar systems.
|
| 810 | * - %DRM_XE_GEM_CREATE_FLAG_NO_COMPRESSION - Allows userspace to
|
| 811 | * hint that compression (CCS) should be disabled for the buffer being
|
| 812 | * created. This can avoid unnecessary memory operations and CCS state
|
| 813 | * management.
|
| 814 | * On pre-Xe2 platforms, this flag is currently rejected as compression
|
| 815 | * control is not supported via PAT index. On Xe2+ platforms, compression
|
| 816 | * is controlled via PAT entries. If this flag is set, the driver will reject
|
| 817 | * any VM bind that requests a PAT index enabling compression for this BO.
|
| 818 | * Note: On dGPU platforms, there is currently no change in behavior with
|
| 819 | * this flag, but future improvements may leverage it. The current benefit is
|
| 820 | * primarily applicable to iGPU platforms.
|
| 821 | *
|
| 822 | * @cpu_caching supports the following values:
|
| 823 | * - %DRM_XE_GEM_CPU_CACHING_WB - Allocate the pages with write-back
|
| 824 | * caching. On iGPU this can't be used for scanout surfaces. Currently
|
| 825 | * not allowed for objects placed in VRAM.
|
| 826 | * - %DRM_XE_GEM_CPU_CACHING_WC - Allocate the pages as write-combined. This
|
| 827 | * is uncached. Scanout surfaces should likely use this. All objects
|
| 828 | * that can be placed in VRAM must use this.
|
| 829 | *
|
| 830 | * This ioctl supports setting the following properties via the
|
| 831 | * %DRM_XE_GEM_CREATE_EXTENSION_SET_PROPERTY extension, which uses the
|
| 832 | * generic &struct drm_xe_ext_set_property:
|
| 833 | *
|
| 834 | * - %DRM_XE_GEM_CREATE_SET_PROPERTY_PXP_TYPE - set the type of PXP session
|
| 835 | * this object will be used with. Valid values are listed in enum
|
| 836 | * drm_xe_pxp_session_type. %DRM_XE_PXP_TYPE_NONE is the default behavior, so
|
| 837 | * there is no need to explicitly set that. Objects used with session of type
|
| 838 | * %DRM_XE_PXP_TYPE_HWDRM will be marked as invalid if a PXP invalidation
|
| 839 | * event occurs after their creation. Attempting to flip an invalid object
|
| 840 | * will cause a black frame to be displayed instead. Submissions with invalid
|
| 841 | * objects mapped in the VM will be rejected.
|
| 842 |
|
| 843 | struct drm_xe_gem_create {
|
| 844 | #define DRM_XE_GEM_CREATE_EXTENSION_SET_PROPERTY 0
|
| 845 | #define DRM_XE_GEM_CREATE_SET_PROPERTY_PXP_TYPE 0
|
| 846 |
|
| 847 | __u64 extensions;
|
| 848 |
|
| 849 | |
| 850 | * @size: Size of the object to be created, must match region
|
| 851 | * (system or vram) minimum alignment (&min_page_size).
|
| 852 |
|
| 853 | __u64 size;
|
| 854 |
|
| 855 | |
| 856 | * @placement: A mask of memory instances of where BO can be placed.
|
| 857 | * Each index in this mask refers directly to the struct
|
| 858 | * drm_xe_query_mem_regions' instance, no assumptions should
|
| 859 | * be made about order. The type of each region is described
|
| 860 | * by struct drm_xe_query_mem_regions' mem_class.
|
| 861 |
|
| 862 | __u32 placement;
|
| 863 |
|
| 864 | #define DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING (1 << 0)
|
| 865 | #define DRM_XE_GEM_CREATE_FLAG_SCANOUT (1 << 1)
|
| 866 | #define DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM (1 << 2)
|
| 867 | #define DRM_XE_GEM_CREATE_FLAG_NO_COMPRESSION (1 << 3)
|
| 868 | |
| 869 | * @flags: Flags for the GEM object, see DRM_XE_GEM_CREATE_FLAG_*
|
| 870 |
|
| 871 | __u32 flags;
|
| 872 |
|
| 873 | |
| 874 | * @vm_id: Attached VM, if any
|
| 875 | *
|
| 876 | * If a VM is specified, this BO must:
|
| 877 | *
|
| 878 | * 1. Only ever be bound to that VM.
|
| 879 | * 2. Cannot be exported as a PRIME fd.
|
| 880 |
|
| 881 | __u32 vm_id;
|
| 882 |
|
| 883 | |
| 884 | * @handle: Returned handle for the object.
|
| 885 | *
|
| 886 | * Object handles are nonzero.
|
| 887 |
|
| 888 | __u32 handle;
|
| 889 |
|
| 890 | #define DRM_XE_GEM_CPU_CACHING_WB 1
|
| 891 | #define DRM_XE_GEM_CPU_CACHING_WC 2
|
| 892 | |
| 893 | * @cpu_caching: The CPU caching mode to select for this object. If
|
| 894 | * mmapping the object the mode selected here will also be used. The
|
| 895 | * exception is when mapping system memory (including data evicted
|
| 896 | * to system) on discrete GPUs. The caching mode selected will
|
| 897 | * then be overridden to DRM_XE_GEM_CPU_CACHING_WB, and coherency
|
| 898 | * between GPU- and CPU is guaranteed. The caching mode of
|
| 899 | * existing CPU-mappings will be updated transparently to
|
| 900 | * user-space clients.
|
| 901 |
|
| 902 | __u16 cpu_caching;
|
| 903 |
|
| 904 | __u16 pad[3];
|
| 905 |
|
| 906 |
|
| 907 | __u64 reserved[2];
|
| 908 | };
|
| 909 |
|
| 910 | |
| 911 | * struct drm_xe_gem_mmap_offset - Input of &DRM_IOCTL_XE_GEM_MMAP_OFFSET
|
| 912 | *
|
| 913 | * The @flags can be:
|
| 914 | * - %DRM_XE_MMAP_OFFSET_FLAG_PCI_BARRIER - For user to query special offset
|
| 915 | * for use in mmap ioctl. Writing to the returned mmap address will generate a
|
| 916 | * PCI memory barrier with low overhead (avoiding IOCTL call as well as writing
|
| 917 | * to VRAM which would also add overhead), acting like an MI_MEM_FENCE
|
| 918 | * instruction.
|
| 919 | *
|
| 920 | * Note: The mmap size can be at most 4K, due to HW limitations. As a result
|
| 921 | * this interface is only supported on CPU architectures that support 4K page
|
| 922 | * size. The mmap_offset ioctl will detect this and gracefully return an
|
| 923 | * error, where userspace is expected to have a different fallback method for
|
| 924 | * triggering a barrier.
|
| 925 | *
|
| 926 | * Roughly the usage would be as follows:
|
| 927 | *
|
| 928 | * .. code-block:: C
|
| 929 | *
|
| 930 | * struct drm_xe_gem_mmap_offset mmo = {
|
| 931 | * .handle = 0, // must be set to 0
|
| 932 | * .flags = DRM_XE_MMAP_OFFSET_FLAG_PCI_BARRIER,
|
| 933 | * };
|
| 934 | *
|
| 935 | * err = ioctl(fd, DRM_IOCTL_XE_GEM_MMAP_OFFSET, &mmo);
|
| 936 | * map = mmap(NULL, size, PROT_WRITE, MAP_SHARED, fd, mmo.offset);
|
| 937 | * map[i] = 0xdeadbeef; // issue barrier
|
| 938 |
|
| 939 | struct drm_xe_gem_mmap_offset {
|
| 940 |
|
| 941 | __u64 extensions;
|
| 942 |
|
| 943 |
|
| 944 | __u32 handle;
|
| 945 |
|
| 946 | #define DRM_XE_MMAP_OFFSET_FLAG_PCI_BARRIER (1 << 0)
|
| 947 |
|
| 948 | __u32 flags;
|
| 949 |
|
| 950 |
|
| 951 | __u64 offset;
|
| 952 |
|
| 953 |
|
| 954 | __u64 reserved[2];
|
| 955 | };
|
| 956 |
|
| 957 | |
| 958 | * struct drm_xe_vm_create - Input of &DRM_IOCTL_XE_VM_CREATE
|
| 959 | *
|
| 960 | * The @flags can be:
|
| 961 | * - %DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE - Map the whole virtual address
|
| 962 | * space of the VM to scratch page. A vm_bind would overwrite the scratch
|
| 963 | * page mapping. This flag is mutually exclusive with the
|
| 964 | * %DRM_XE_VM_CREATE_FLAG_FAULT_MODE flag, with an exception on Xe2 and
|
| 965 | * Xe3 platforms.
|
| 966 | * - %DRM_XE_VM_CREATE_FLAG_LR_MODE - An LR, or Long Running VM accepts
|
| 967 | * exec submissions to its exec_queues that don't have an upper time
|
| 968 | * limit on the job execution time. But exec submissions to these
|
| 969 | * don't allow any of the sync types DRM_XE_SYNC_TYPE_SYNCOBJ,
|
| 970 | * DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ, used as out-syncobjs, that is,
|
| 971 | * together with sync flag DRM_XE_SYNC_FLAG_SIGNAL.
|
| 972 | * LR VMs can be created in recoverable page-fault mode using
|
| 973 | * DRM_XE_VM_CREATE_FLAG_FAULT_MODE, if the device supports it.
|
| 974 | * If that flag is omitted, the UMD can not rely on the slightly
|
| 975 | * different per-VM overcommit semantics that are enabled by
|
| 976 | * DRM_XE_VM_CREATE_FLAG_FAULT_MODE (see below), but KMD may
|
| 977 | * still enable recoverable pagefaults if supported by the device.
|
| 978 | * - %DRM_XE_VM_CREATE_FLAG_FAULT_MODE - Requires also
|
| 979 | * DRM_XE_VM_CREATE_FLAG_LR_MODE. It allows memory to be allocated on
|
| 980 | * demand when accessed, and also allows per-VM overcommit of memory.
|
| 981 | * The xe driver internally uses recoverable pagefaults to implement
|
| 982 | * this.
|
| 983 | * - %DRM_XE_VM_CREATE_FLAG_NO_VM_OVERCOMMIT - Requires also
|
| 984 | * DRM_XE_VM_CREATE_FLAG_FAULT_MODE. This disallows per-VM overcommit
|
| 985 | * but only during a &DRM_IOCTL_XE_VM_BIND operation with the
|
| 986 | * %DRM_XE_VM_BIND_FLAG_IMMEDIATE flag set. This may be useful for
|
| 987 | * user-space naively probing the amount of available memory.
|
| 988 |
|
| 989 | struct drm_xe_vm_create {
|
| 990 |
|
| 991 | __u64 extensions;
|
| 992 |
|
| 993 | #define DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE (1 << 0)
|
| 994 | #define DRM_XE_VM_CREATE_FLAG_LR_MODE (1 << 1)
|
| 995 | #define DRM_XE_VM_CREATE_FLAG_FAULT_MODE (1 << 2)
|
| 996 | #define DRM_XE_VM_CREATE_FLAG_NO_VM_OVERCOMMIT (1 << 3)
|
| 997 |
|
| 998 | __u32 flags;
|
| 999 |
|
| 1000 |
|
| 1001 | __u32 vm_id;
|
| 1002 |
|
| 1003 |
|
| 1004 | __u64 reserved[2];
|
| 1005 | };
|
| 1006 |
|
| 1007 | |
| 1008 | * struct drm_xe_vm_destroy - Input of &DRM_IOCTL_XE_VM_DESTROY
|
| 1009 |
|
| 1010 | struct drm_xe_vm_destroy {
|
| 1011 |
|
| 1012 | __u32 vm_id;
|
| 1013 |
|
| 1014 |
|
| 1015 | __u32 pad;
|
| 1016 |
|
| 1017 |
|
| 1018 | __u64 reserved[2];
|
| 1019 | };
|
| 1020 |
|
| 1021 | |
| 1022 | * struct drm_xe_vm_bind_op - run bind operations
|
| 1023 | *
|
| 1024 | * The @op can be:
|
| 1025 | * - %DRM_XE_VM_BIND_OP_MAP
|
| 1026 | * - %DRM_XE_VM_BIND_OP_UNMAP
|
| 1027 | * - %DRM_XE_VM_BIND_OP_MAP_USERPTR
|
| 1028 | * - %DRM_XE_VM_BIND_OP_UNMAP_ALL
|
| 1029 | * - %DRM_XE_VM_BIND_OP_PREFETCH
|
| 1030 | *
|
| 1031 | * and the @flags can be:
|
| 1032 | * - %DRM_XE_VM_BIND_FLAG_READONLY - Setup the page tables as read-only
|
| 1033 | * to ensure write protection
|
| 1034 | * - %DRM_XE_VM_BIND_FLAG_IMMEDIATE - On a faulting VM, do the
|
| 1035 | * MAP operation immediately rather than deferring the MAP to the page
|
| 1036 | * fault handler. This is implied on a non-faulting VM as there is no
|
| 1037 | * fault handler to defer to.
|
| 1038 | * - %DRM_XE_VM_BIND_FLAG_NULL - When the NULL flag is set, the page
|
| 1039 | * tables are setup with a special bit which indicates writes are
|
| 1040 | * dropped and all reads return zero. In the future, the NULL flags
|
| 1041 | * will only be valid for DRM_XE_VM_BIND_OP_MAP operations, the BO
|
| 1042 | * handle MBZ, and the BO offset MBZ. This flag is intended to
|
| 1043 | * implement VK sparse bindings.
|
| 1044 | * - %DRM_XE_VM_BIND_FLAG_CHECK_PXP - If the object is encrypted via PXP,
|
| 1045 | * reject the binding if the encryption key is no longer valid. This
|
| 1046 | * flag has no effect on BOs that are not marked as using PXP.
|
| 1047 | * - %DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR - When the CPU address mirror flag is
|
| 1048 | * set, no mappings are created rather the range is reserved for CPU address
|
| 1049 | * mirroring which will be populated on GPU page faults or prefetches. Only
|
| 1050 | * valid on VMs with DRM_XE_VM_CREATE_FLAG_FAULT_MODE set. The CPU address
|
| 1051 | * mirror flag is only valid for DRM_XE_VM_BIND_OP_MAP operations, the BO
|
| 1052 | * handle MBZ, and the BO offset MBZ.
|
| 1053 | * - %DRM_XE_VM_BIND_FLAG_MADVISE_AUTORESET - Can be used in combination with
|
| 1054 | * %DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR to reset madvises when the underlying
|
| 1055 | * CPU address space range is unmapped (typically with munmap(2) or brk(2)).
|
| 1056 | * The madvise values set with &DRM_IOCTL_XE_MADVISE are reset to the values
|
| 1057 | * that were present immediately after the &DRM_IOCTL_XE_VM_BIND.
|
| 1058 | * The reset GPU virtual address range is the intersection of the range bound
|
| 1059 | * using &DRM_IOCTL_XE_VM_BIND and the virtual CPU address space range
|
| 1060 | * unmapped.
|
| 1061 | * This functionality is present to mimic the behaviour of CPU address space
|
| 1062 | * madvises set using madvise(2), which are typically reset on unmap.
|
| 1063 | * Note: free(3) may or may not call munmap(2) and/or brk(2), and may thus
|
| 1064 | * not invoke autoreset. Neither will stack variables going out of scope.
|
| 1065 | * Therefore it's recommended to always explicitly reset the madvises when
|
| 1066 | * freeing the memory backing a region used in a &DRM_IOCTL_XE_MADVISE call.
|
| 1067 | *
|
| 1068 | * - %DRM_XE_VM_BIND_FLAG_DECOMPRESS - Request on-device decompression for a MAP.
|
| 1069 | * When set on a MAP bind operation, request the driver schedule an on-device
|
| 1070 | * in-place decompression (via the migrate/resolve path) for the GPU mapping
|
| 1071 | * created by this bind. Only valid for DRM_XE_VM_BIND_OP_MAP; usage on
|
| 1072 | * other ops is rejected. The bind's pat_index must select the device's
|
| 1073 | * "no-compression" PAT. Only meaningful for VRAM-backed BOs on devices that
|
| 1074 | * support Flat CCS and the required HW generation XE2+.
|
| 1075 | *
|
| 1076 | * The @prefetch_mem_region_instance for %DRM_XE_VM_BIND_OP_PREFETCH can also be:
|
| 1077 | * - %DRM_XE_CONSULT_MEM_ADVISE_PREF_LOC, which ensures prefetching occurs in
|
| 1078 | * the memory region advised by madvise.
|
| 1079 |
|
| 1080 | struct drm_xe_vm_bind_op {
|
| 1081 |
|
| 1082 | __u64 extensions;
|
| 1083 |
|
| 1084 | |
| 1085 | * @obj: GEM object to operate on, MBZ for MAP_USERPTR, MBZ for UNMAP
|
| 1086 |
|
| 1087 | __u32 obj;
|
| 1088 |
|
| 1089 | |
| 1090 | * @pat_index: The platform defined @pat_index to use for this mapping.
|
| 1091 | * The index basically maps to some predefined memory attributes,
|
| 1092 | * including things like caching, coherency, compression etc. The exact
|
| 1093 | * meaning of the pat_index is platform specific and defined in the
|
| 1094 | * Bspec and PRMs. When the KMD sets up the binding the index here is
|
| 1095 | * encoded into the ppGTT PTE.
|
| 1096 | *
|
| 1097 | * For coherency the @pat_index needs to be at least 1way coherent when
|
| 1098 | * drm_xe_gem_create.cpu_caching is DRM_XE_GEM_CPU_CACHING_WB. The KMD
|
| 1099 | * will extract the coherency mode from the @pat_index and reject if
|
| 1100 | * there is a mismatch (see note below for pre-MTL platforms).
|
| 1101 | *
|
| 1102 | * Note: On pre-MTL platforms there is only a caching mode and no
|
| 1103 | * explicit coherency mode, but on such hardware there is always a
|
| 1104 | * shared-LLC (or is dgpu) so all GT memory accesses are coherent with
|
| 1105 | * CPU caches even with the caching mode set as uncached. It's only the
|
| 1106 | * display engine that is incoherent (on dgpu it must be in VRAM which
|
| 1107 | * is always mapped as WC on the CPU). However to keep the uapi somewhat
|
| 1108 | * consistent with newer platforms the KMD groups the different cache
|
| 1109 | * levels into the following coherency buckets on all pre-MTL platforms:
|
| 1110 | *
|
| 1111 | * ppGTT UC -> COH_NONE
|
| 1112 | * ppGTT WC -> COH_NONE
|
| 1113 | * ppGTT WT -> COH_NONE
|
| 1114 | * ppGTT WB -> COH_AT_LEAST_1WAY
|
| 1115 | *
|
| 1116 | * In practice UC/WC/WT should only ever be used for scanout surfaces on
|
| 1117 | * such platforms (or perhaps in general for dma-buf if shared with
|
| 1118 | * another device) since it is only the display engine that is actually
|
| 1119 | * incoherent. Everything else should typically use WB given that we
|
| 1120 | * have a shared-LLC. On MTL+ this completely changes and the HW
|
| 1121 | * defines the coherency mode as part of the @pat_index, where
|
| 1122 | * incoherent GT access is possible.
|
| 1123 | *
|
| 1124 | * Note: For userptr and externally imported dma-buf the kernel expects
|
| 1125 | * either 1WAY or 2WAY for the @pat_index. Starting from NVL-P, for
|
| 1126 | * userptr, svm, madvise and externally imported dma-buf the kernel expects
|
| 1127 | * either 2WAY or 1WAY and XA @pat_index.
|
| 1128 | *
|
| 1129 | * For DRM_XE_VM_BIND_FLAG_NULL bindings there are no KMD restrictions
|
| 1130 | * on the @pat_index. For such mappings there is no actual memory being
|
| 1131 | * mapped (the address in the PTE is invalid), so the various PAT memory
|
| 1132 | * attributes likely do not apply. Simply leaving as zero is one
|
| 1133 | * option (still a valid pat_index). Same applies to
|
| 1134 | * DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR bindings as for such mapping
|
| 1135 | * there is no actual memory being mapped.
|
| 1136 |
|
| 1137 | __u16 pat_index;
|
| 1138 |
|
| 1139 |
|
| 1140 | __u16 pad;
|
| 1141 |
|
| 1142 | union {
|
| 1143 | |
| 1144 | * @obj_offset: Offset into the object, MBZ for CLEAR_RANGE,
|
| 1145 | * ignored for unbind
|
| 1146 |
|
| 1147 | __u64 obj_offset;
|
| 1148 |
|
| 1149 |
|
| 1150 | __u64 userptr;
|
| 1151 |
|
| 1152 | |
| 1153 | * @cpu_addr_mirror_offset: Offset from GPU @addr to create
|
| 1154 | * CPU address mirror mappings. MBZ with current level of
|
| 1155 | * support (e.g. 1 to 1 mapping between GPU and CPU mappings
|
| 1156 | * only supported).
|
| 1157 |
|
| 1158 | __s64 cpu_addr_mirror_offset;
|
| 1159 | };
|
| 1160 |
|
| 1161 | |
| 1162 | * @range: Number of bytes from the object to bind to addr, MBZ for UNMAP_ALL
|
| 1163 |
|
| 1164 | __u64 range;
|
| 1165 |
|
| 1166 |
|
| 1167 | __u64 addr;
|
| 1168 |
|
| 1169 | #define DRM_XE_VM_BIND_OP_MAP 0x0
|
| 1170 | #define DRM_XE_VM_BIND_OP_UNMAP 0x1
|
| 1171 | #define DRM_XE_VM_BIND_OP_MAP_USERPTR 0x2
|
| 1172 | #define DRM_XE_VM_BIND_OP_UNMAP_ALL 0x3
|
| 1173 | #define DRM_XE_VM_BIND_OP_PREFETCH 0x4
|
| 1174 |
|
| 1175 | __u32 op;
|
| 1176 |
|
| 1177 | #define DRM_XE_VM_BIND_FLAG_READONLY (1 << 0)
|
| 1178 | #define DRM_XE_VM_BIND_FLAG_IMMEDIATE (1 << 1)
|
| 1179 | #define DRM_XE_VM_BIND_FLAG_NULL (1 << 2)
|
| 1180 | #define DRM_XE_VM_BIND_FLAG_DUMPABLE (1 << 3)
|
| 1181 | #define DRM_XE_VM_BIND_FLAG_CHECK_PXP (1 << 4)
|
| 1182 | #define DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR (1 << 5)
|
| 1183 | #define DRM_XE_VM_BIND_FLAG_MADVISE_AUTORESET (1 << 6)
|
| 1184 | #define DRM_XE_VM_BIND_FLAG_DECOMPRESS (1 << 7)
|
| 1185 |
|
| 1186 | __u32 flags;
|
| 1187 |
|
| 1188 | #define DRM_XE_CONSULT_MEM_ADVISE_PREF_LOC -1
|
| 1189 | |
| 1190 | * @prefetch_mem_region_instance: Memory region to prefetch VMA to.
|
| 1191 | * It is a region instance, not a mask.
|
| 1192 | * To be used only with %DRM_XE_VM_BIND_OP_PREFETCH operation.
|
| 1193 |
|
| 1194 | __u32 prefetch_mem_region_instance;
|
| 1195 |
|
| 1196 |
|
| 1197 | __u32 pad2;
|
| 1198 |
|
| 1199 |
|
| 1200 | __u64 reserved[3];
|
| 1201 | };
|
| 1202 |
|
| 1203 | |
| 1204 | * struct drm_xe_vm_bind - Input of &DRM_IOCTL_XE_VM_BIND
|
| 1205 | *
|
| 1206 | * Below is an example of a minimal use of &struct drm_xe_vm_bind to
|
| 1207 | * asynchronously bind the buffer `data` at address `BIND_ADDRESS` to
|
| 1208 | * illustrate `userptr`. It can be synchronized by using the example
|
| 1209 | * provided for &struct drm_xe_sync.
|
| 1210 | *
|
| 1211 | * .. code-block:: C
|
| 1212 | *
|
| 1213 | * data = aligned_alloc(ALIGNMENT, BO_SIZE);
|
| 1214 | * struct drm_xe_vm_bind bind = {
|
| 1215 | * .vm_id = vm,
|
| 1216 | * .num_binds = 1,
|
| 1217 | * .bind.obj = 0,
|
| 1218 | * .bind.obj_offset = to_user_pointer(data),
|
| 1219 | * .bind.range = BO_SIZE,
|
| 1220 | * .bind.addr = BIND_ADDRESS,
|
| 1221 | * .bind.op = DRM_XE_VM_BIND_OP_MAP_USERPTR,
|
| 1222 | * .bind.flags = 0,
|
| 1223 | * .num_syncs = 1,
|
| 1224 | * .syncs = &sync,
|
| 1225 | * .exec_queue_id = 0,
|
| 1226 | * };
|
| 1227 | * ioctl(fd, DRM_IOCTL_XE_VM_BIND, &bind);
|
| 1228 | *
|
| 1229 |
|
| 1230 | struct drm_xe_vm_bind {
|
| 1231 |
|
| 1232 | __u64 extensions;
|
| 1233 |
|
| 1234 |
|
| 1235 | __u32 vm_id;
|
| 1236 |
|
| 1237 | |
| 1238 | * @exec_queue_id: exec_queue_id, must be of class DRM_XE_ENGINE_CLASS_VM_BIND
|
| 1239 | * and exec queue must have same vm_id. If zero, the default VM bind engine
|
| 1240 | * is used.
|
| 1241 |
|
| 1242 | __u32 exec_queue_id;
|
| 1243 |
|
| 1244 |
|
| 1245 | __u32 pad;
|
| 1246 |
|
| 1247 |
|
| 1248 | __u32 num_binds;
|
| 1249 |
|
| 1250 | union {
|
| 1251 |
|
| 1252 | struct drm_xe_vm_bind_op bind;
|
| 1253 |
|
| 1254 | |
| 1255 | * @vector_of_binds: userptr to array of struct
|
| 1256 | * drm_xe_vm_bind_op if num_binds > 1
|
| 1257 |
|
| 1258 | __u64 vector_of_binds;
|
| 1259 | };
|
| 1260 |
|
| 1261 |
|
| 1262 | __u32 pad2;
|
| 1263 |
|
| 1264 |
|
| 1265 | __u32 num_syncs;
|
| 1266 |
|
| 1267 |
|
| 1268 | __u64 syncs;
|
| 1269 |
|
| 1270 |
|
| 1271 | __u64 reserved[2];
|
| 1272 | };
|
| 1273 |
|
| 1274 |
|
| 1275 | struct xe_vm_fault {
|
| 1276 |
|
| 1277 | __u64 address;
|
| 1278 |
|
| 1279 | __u32 address_precision;
|
| 1280 |
|
| 1281 | #define FAULT_ACCESS_TYPE_READ 0
|
| 1282 | #define FAULT_ACCESS_TYPE_WRITE 1
|
| 1283 | #define FAULT_ACCESS_TYPE_ATOMIC 2
|
| 1284 | __u8 access_type;
|
| 1285 |
|
| 1286 | #define FAULT_TYPE_NOT_PRESENT 0
|
| 1287 | #define FAULT_TYPE_WRITE_ACCESS 1
|
| 1288 | #define FAULT_TYPE_ATOMIC_ACCESS 2
|
| 1289 | __u8 fault_type;
|
| 1290 |
|
| 1291 | #define FAULT_LEVEL_PTE 0
|
| 1292 | #define FAULT_LEVEL_PDE 1
|
| 1293 | #define FAULT_LEVEL_PDP 2
|
| 1294 | #define FAULT_LEVEL_PML4 3
|
| 1295 | #define FAULT_LEVEL_PML5 4
|
| 1296 | __u8 fault_level;
|
| 1297 |
|
| 1298 | __u8 pad;
|
| 1299 |
|
| 1300 | __u64 reserved[4];
|
| 1301 | };
|
| 1302 |
|
| 1303 | |
| 1304 | * struct drm_xe_vm_get_property - Input of &DRM_IOCTL_XE_VM_GET_PROPERTY
|
| 1305 | *
|
| 1306 | * The user provides a VM and a property to query among DRM_XE_VM_GET_PROPERTY_*,
|
| 1307 | * and sets the values in the vm_id and property members, respectively. This
|
| 1308 | * determines both the VM to get the property of, as well as the property to
|
| 1309 | * report.
|
| 1310 | *
|
| 1311 | * If size is set to 0, the driver fills it with the required size for the
|
| 1312 | * requested property. The user is expected here to allocate memory for the
|
| 1313 | * property structure and to provide a pointer to the allocated memory using the
|
| 1314 | * data member. For some properties, this may be zero, in which case, the
|
| 1315 | * value of the property will be saved to the value member and size will remain
|
| 1316 | * zero on return.
|
| 1317 | *
|
| 1318 | * If size is not zero, then the IOCTL will attempt to copy the requested
|
| 1319 | * property into the data member.
|
| 1320 | *
|
| 1321 | * The IOCTL will return -ENOENT if the VM could not be identified from the
|
| 1322 | * provided VM ID, or -EINVAL if the IOCTL fails for any other reason, such as
|
| 1323 | * providing an invalid size for the given property or if the property data
|
| 1324 | * could not be copied to the memory allocated to the data member.
|
| 1325 | *
|
| 1326 | * The property member can be:
|
| 1327 | * - %DRM_XE_VM_GET_PROPERTY_FAULTS
|
| 1328 |
|
| 1329 | struct drm_xe_vm_get_property {
|
| 1330 |
|
| 1331 | __u64 extensions;
|
| 1332 |
|
| 1333 |
|
| 1334 | __u32 vm_id;
|
| 1335 |
|
| 1336 | #define DRM_XE_VM_GET_PROPERTY_FAULTS 0
|
| 1337 |
|
| 1338 | __u32 property;
|
| 1339 |
|
| 1340 |
|
| 1341 | __u32 size;
|
| 1342 |
|
| 1343 |
|
| 1344 | __u32 pad;
|
| 1345 |
|
| 1346 | union {
|
| 1347 |
|
| 1348 | __u64 data;
|
| 1349 |
|
| 1350 | __u64 value;
|
| 1351 | };
|
| 1352 |
|
| 1353 |
|
| 1354 | __u64 reserved[3];
|
| 1355 | };
|
| 1356 |
|
| 1357 | |
| 1358 | * struct drm_xe_exec_queue_create - Input of &DRM_IOCTL_XE_EXEC_QUEUE_CREATE
|
| 1359 | *
|
| 1360 | * This ioctl supports setting the following properties via the
|
| 1361 | * %DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY extension, which uses the
|
| 1362 | * generic &struct drm_xe_ext_set_property:
|
| 1363 | *
|
| 1364 | * - %DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY - set the queue priority.
|
| 1365 | * CAP_SYS_NICE is required to set a value above normal.
|
| 1366 | * - %DRM_XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE - set the queue timeslice
|
| 1367 | * duration in microseconds.
|
| 1368 | * - %DRM_XE_EXEC_QUEUE_SET_PROPERTY_PXP_TYPE - set the type of PXP session
|
| 1369 | * this queue will be used with. Valid values are listed in enum
|
| 1370 | * drm_xe_pxp_session_type. %DRM_XE_PXP_TYPE_NONE is the default behavior, so
|
| 1371 | * there is no need to explicitly set that. When a queue of type
|
| 1372 | * %DRM_XE_PXP_TYPE_HWDRM is created, the PXP default HWDRM session
|
| 1373 | * (%DRM_XE_PXP_HWDRM_DEFAULT_SESSION) will be started, if it isn't already running.
|
| 1374 | * The user is expected to query the PXP status via the query ioctl (see
|
| 1375 | * %DRM_XE_DEVICE_QUERY_PXP_STATUS) and to wait for PXP to be ready before
|
| 1376 | * attempting to create a queue with this property. When a queue is created
|
| 1377 | * before PXP is ready, the ioctl will return -EBUSY if init is still in
|
| 1378 | * progress or -EIO if init failed.
|
| 1379 | * Given that going into a power-saving state kills PXP HWDRM sessions,
|
| 1380 | * runtime PM will be blocked while queues of this type are alive.
|
| 1381 | * All PXP queues will be killed if a PXP invalidation event occurs.
|
| 1382 | * - %DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP - Create a multi-queue group
|
| 1383 | * or add secondary queues to a multi-queue group.
|
| 1384 | * If the extension's 'value' field has %DRM_XE_MULTI_GROUP_CREATE flag set,
|
| 1385 | * then a new multi-queue group is created with this queue as the primary queue
|
| 1386 | * (Q0). Otherwise, the queue gets added to the multi-queue group whose primary
|
| 1387 | * queue's exec_queue_id is specified in the lower 32 bits of the 'value' field.
|
| 1388 | * All the other non-relevant bits of extension's 'value' field while adding the
|
| 1389 | * primary or the secondary queues of the group must be set to 0.
|
| 1390 | * - %DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY - Set the queue
|
| 1391 | * priority within the multi-queue group. Current valid priority values are 0–2
|
| 1392 | * (default is 1), with higher values indicating higher priority.
|
| 1393 | * - %DRM_XE_EXEC_QUEUE_SET_DISABLE_STATE_CACHE_PERF_FIX - Set the queue to
|
| 1394 | * enable render color cache keying on BTP+BTI instead of just BTI
|
| 1395 | * (only valid for render queues).
|
| 1396 | *
|
| 1397 | * The example below shows how to use &struct drm_xe_exec_queue_create to create
|
| 1398 | * a simple exec_queue (no parallel submission) of class
|
| 1399 | * %DRM_XE_ENGINE_CLASS_RENDER.
|
| 1400 | *
|
| 1401 | * .. code-block:: C
|
| 1402 | *
|
| 1403 | * struct drm_xe_engine_class_instance instance = {
|
| 1404 | * .engine_class = DRM_XE_ENGINE_CLASS_RENDER,
|
| 1405 | * };
|
| 1406 | * struct drm_xe_exec_queue_create exec_queue_create = {
|
| 1407 | * .extensions = 0,
|
| 1408 | * .vm_id = vm,
|
| 1409 | * .width = 1,
|
| 1410 | * .num_placements = 1,
|
| 1411 | * .instances = to_user_pointer(&instance),
|
| 1412 | * };
|
| 1413 | * ioctl(fd, DRM_IOCTL_XE_EXEC_QUEUE_CREATE, &exec_queue_create);
|
| 1414 | *
|
| 1415 | * Allow users to provide a hint to kernel for cases demanding low latency
|
| 1416 | * profile. Please note it will have impact on power consumption. User can
|
| 1417 | * indicate low latency hint with flag while creating exec queue as
|
| 1418 | * mentioned below:
|
| 1419 | *
|
| 1420 | * .. code-block:: C
|
| 1421 | *
|
| 1422 | * struct drm_xe_exec_queue_create exec_queue_create = {
|
| 1423 | * .flags = DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT,
|
| 1424 | * .extensions = 0,
|
| 1425 | * .vm_id = vm,
|
| 1426 | * .width = 1,
|
| 1427 | * .num_placements = 1,
|
| 1428 | * .instances = to_user_pointer(&instance),
|
| 1429 | * };
|
| 1430 | * ioctl(fd, DRM_IOCTL_XE_EXEC_QUEUE_CREATE, &exec_queue_create);
|
| 1431 | *
|
| 1432 |
|
| 1433 | struct drm_xe_exec_queue_create {
|
| 1434 | #define DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY 0
|
| 1435 | #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY 0
|
| 1436 | #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE 1
|
| 1437 | #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_PXP_TYPE 2
|
| 1438 | #define DRM_XE_EXEC_QUEUE_SET_HANG_REPLAY_STATE 3
|
| 1439 | #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP 4
|
| 1440 | #define DRM_XE_MULTI_GROUP_CREATE (1ull << 63)
|
| 1441 | #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY 5
|
| 1442 | #define DRM_XE_EXEC_QUEUE_SET_DISABLE_STATE_CACHE_PERF_FIX 6
|
| 1443 |
|
| 1444 | __u64 extensions;
|
| 1445 |
|
| 1446 |
|
| 1447 | __u16 width;
|
| 1448 |
|
| 1449 |
|
| 1450 | __u16 num_placements;
|
| 1451 |
|
| 1452 |
|
| 1453 | __u32 vm_id;
|
| 1454 |
|
| 1455 | #define DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT (1 << 0)
|
| 1456 |
|
| 1457 | __u32 flags;
|
| 1458 |
|
| 1459 |
|
| 1460 | __u32 exec_queue_id;
|
| 1461 |
|
| 1462 | |
| 1463 | * @instances: user pointer to a 2-d array of struct
|
| 1464 | * drm_xe_engine_class_instance
|
| 1465 | *
|
| 1466 | * length = width (i) * num_placements (j)
|
| 1467 | * index = j + i * width
|
| 1468 |
|
| 1469 | __u64 instances;
|
| 1470 |
|
| 1471 |
|
| 1472 | __u64 reserved[2];
|
| 1473 | };
|
| 1474 |
|
| 1475 | |
| 1476 | * struct drm_xe_exec_queue_destroy - Input of &DRM_IOCTL_XE_EXEC_QUEUE_DESTROY
|
| 1477 |
|
| 1478 | struct drm_xe_exec_queue_destroy {
|
| 1479 |
|
| 1480 | __u32 exec_queue_id;
|
| 1481 |
|
| 1482 |
|
| 1483 | __u32 pad;
|
| 1484 |
|
| 1485 |
|
| 1486 | __u64 reserved[2];
|
| 1487 | };
|
| 1488 |
|
| 1489 | |
| 1490 | * struct drm_xe_exec_queue_get_property - Input of &DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY
|
| 1491 | *
|
| 1492 | * The @property can be:
|
| 1493 | * - %DRM_XE_EXEC_QUEUE_GET_PROPERTY_BAN
|
| 1494 |
|
| 1495 | struct drm_xe_exec_queue_get_property {
|
| 1496 |
|
| 1497 | __u64 extensions;
|
| 1498 |
|
| 1499 |
|
| 1500 | __u32 exec_queue_id;
|
| 1501 |
|
| 1502 | #define DRM_XE_EXEC_QUEUE_GET_PROPERTY_BAN 0
|
| 1503 |
|
| 1504 | __u32 property;
|
| 1505 |
|
| 1506 |
|
| 1507 | __u64 value;
|
| 1508 |
|
| 1509 |
|
| 1510 | __u64 reserved[2];
|
| 1511 | };
|
| 1512 |
|
| 1513 | |
| 1514 | * struct drm_xe_sync - sync object
|
| 1515 | *
|
| 1516 | * The @type can be:
|
| 1517 | * - %DRM_XE_SYNC_TYPE_SYNCOBJ
|
| 1518 | * - %DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ
|
| 1519 | * - %DRM_XE_SYNC_TYPE_USER_FENCE
|
| 1520 | *
|
| 1521 | * and the @flags can be:
|
| 1522 | * - %DRM_XE_SYNC_FLAG_SIGNAL
|
| 1523 | *
|
| 1524 | * A minimal use of &struct drm_xe_sync looks like this:
|
| 1525 | *
|
| 1526 | * .. code-block:: C
|
| 1527 | *
|
| 1528 | * struct drm_xe_sync sync = {
|
| 1529 | * .flags = DRM_XE_SYNC_FLAG_SIGNAL,
|
| 1530 | * .type = DRM_XE_SYNC_TYPE_SYNCOBJ,
|
| 1531 | * };
|
| 1532 | * struct drm_syncobj_create syncobj_create = { 0 };
|
| 1533 | * ioctl(fd, DRM_IOCTL_SYNCOBJ_CREATE, &syncobj_create);
|
| 1534 | * sync.handle = syncobj_create.handle;
|
| 1535 | * ...
|
| 1536 | * use of &sync in drm_xe_exec or drm_xe_vm_bind
|
| 1537 | * ...
|
| 1538 | * struct drm_syncobj_wait wait = {
|
| 1539 | * .handles = &sync.handle,
|
| 1540 | * .timeout_nsec = INT64_MAX,
|
| 1541 | * .count_handles = 1,
|
| 1542 | * .flags = 0,
|
| 1543 | * .first_signaled = 0,
|
| 1544 | * .pad = 0,
|
| 1545 | * };
|
| 1546 | * ioctl(fd, DRM_IOCTL_SYNCOBJ_WAIT, &wait);
|
| 1547 |
|
| 1548 | struct drm_xe_sync {
|
| 1549 |
|
| 1550 | __u64 extensions;
|
| 1551 |
|
| 1552 | #define DRM_XE_SYNC_TYPE_SYNCOBJ 0x0
|
| 1553 | #define DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ 0x1
|
| 1554 | #define DRM_XE_SYNC_TYPE_USER_FENCE 0x2
|
| 1555 |
|
| 1556 | __u32 type;
|
| 1557 |
|
| 1558 | #define DRM_XE_SYNC_FLAG_SIGNAL (1 << 0)
|
| 1559 |
|
| 1560 | __u32 flags;
|
| 1561 |
|
| 1562 | union {
|
| 1563 |
|
| 1564 | __u32 handle;
|
| 1565 |
|
| 1566 | |
| 1567 | * @addr: Address of user fence. When sync is passed in via exec
|
| 1568 | * IOCTL this is a GPU address in the VM. When sync is passed in via
|
| 1569 | * VM bind IOCTL this is a user pointer. In either case, it is
|
| 1570 | * the user's responsibility that this address is present and
|
| 1571 | * mapped when the user fence is signalled. Must be qword
|
| 1572 | * aligned.
|
| 1573 |
|
| 1574 | __u64 addr;
|
| 1575 | };
|
| 1576 |
|
| 1577 | |
| 1578 | * @timeline_value: Input for the timeline sync object. Needs to be
|
| 1579 | * different than 0 when used with %DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ.
|
| 1580 |
|
| 1581 | __u64 timeline_value;
|
| 1582 |
|
| 1583 |
|
| 1584 | __u64 reserved[2];
|
| 1585 | };
|
| 1586 |
|
| 1587 | |
| 1588 | * struct drm_xe_exec - Input of &DRM_IOCTL_XE_EXEC
|
| 1589 | *
|
| 1590 | * This is an example to use &struct drm_xe_exec for execution of the object
|
| 1591 | * at BIND_ADDRESS (see example in &struct drm_xe_vm_bind) by an exec_queue
|
| 1592 | * (see example in &struct drm_xe_exec_queue_create). It can be synchronized
|
| 1593 | * by using the example provided for &struct drm_xe_sync.
|
| 1594 | *
|
| 1595 | * .. code-block:: C
|
| 1596 | *
|
| 1597 | * struct drm_xe_exec exec = {
|
| 1598 | * .exec_queue_id = exec_queue,
|
| 1599 | * .syncs = &sync,
|
| 1600 | * .num_syncs = 1,
|
| 1601 | * .address = BIND_ADDRESS,
|
| 1602 | * .num_batch_buffer = 1,
|
| 1603 | * };
|
| 1604 | * ioctl(fd, DRM_IOCTL_XE_EXEC, &exec);
|
| 1605 | *
|
| 1606 |
|
| 1607 | struct drm_xe_exec {
|
| 1608 |
|
| 1609 | __u64 extensions;
|
| 1610 |
|
| 1611 |
|
| 1612 | __u32 exec_queue_id;
|
| 1613 |
|
| 1614 | #define DRM_XE_MAX_SYNCS 1024
|
| 1615 |
|
| 1616 | __u32 num_syncs;
|
| 1617 |
|
| 1618 |
|
| 1619 | __u64 syncs;
|
| 1620 |
|
| 1621 | |
| 1622 | * @address: address of batch buffer if num_batch_buffer == 1 or an
|
| 1623 | * array of batch buffer addresses
|
| 1624 |
|
| 1625 | __u64 address;
|
| 1626 |
|
| 1627 | |
| 1628 | * @num_batch_buffer: number of batch buffer in this exec, must match
|
| 1629 | * the width of the engine
|
| 1630 |
|
| 1631 | __u16 num_batch_buffer;
|
| 1632 |
|
| 1633 |
|
| 1634 | __u16 pad[3];
|
| 1635 |
|
| 1636 |
|
| 1637 | __u64 reserved[2];
|
| 1638 | };
|
| 1639 |
|
| 1640 | |
| 1641 | * struct drm_xe_wait_user_fence - Input of &DRM_IOCTL_XE_WAIT_USER_FENCE
|
| 1642 | *
|
| 1643 | * Wait on user fence, XE will wake-up on every HW engine interrupt in the
|
| 1644 | * instances list and check if user fence is complete::
|
| 1645 | *
|
| 1646 | * (*addr & MASK) OP (VALUE & MASK)
|
| 1647 | *
|
| 1648 | * Returns to user on user fence completion or timeout.
|
| 1649 | *
|
| 1650 | * The @op can be:
|
| 1651 | * - %DRM_XE_UFENCE_WAIT_OP_EQ
|
| 1652 | * - %DRM_XE_UFENCE_WAIT_OP_NEQ
|
| 1653 | * - %DRM_XE_UFENCE_WAIT_OP_GT
|
| 1654 | * - %DRM_XE_UFENCE_WAIT_OP_GTE
|
| 1655 | * - %DRM_XE_UFENCE_WAIT_OP_LT
|
| 1656 | * - %DRM_XE_UFENCE_WAIT_OP_LTE
|
| 1657 | *
|
| 1658 | * and the @flags can be:
|
| 1659 | * - %DRM_XE_UFENCE_WAIT_FLAG_ABSTIME
|
| 1660 | *
|
| 1661 | * The @mask values can be for example:
|
| 1662 | * - 0xffu for u8
|
| 1663 | * - 0xffffu for u16
|
| 1664 | * - 0xffffffffu for u32
|
| 1665 | * - 0xffffffffffffffffu for u64
|
| 1666 |
|
| 1667 | struct drm_xe_wait_user_fence {
|
| 1668 |
|
| 1669 | __u64 extensions;
|
| 1670 |
|
| 1671 | |
| 1672 | * @addr: user pointer address to wait on, must be qword aligned
|
| 1673 |
|
| 1674 | __u64 addr;
|
| 1675 |
|
| 1676 | #define DRM_XE_UFENCE_WAIT_OP_EQ 0x0
|
| 1677 | #define DRM_XE_UFENCE_WAIT_OP_NEQ 0x1
|
| 1678 | #define DRM_XE_UFENCE_WAIT_OP_GT 0x2
|
| 1679 | #define DRM_XE_UFENCE_WAIT_OP_GTE 0x3
|
| 1680 | #define DRM_XE_UFENCE_WAIT_OP_LT 0x4
|
| 1681 | #define DRM_XE_UFENCE_WAIT_OP_LTE 0x5
|
| 1682 |
|
| 1683 | __u16 op;
|
| 1684 |
|
| 1685 | #define DRM_XE_UFENCE_WAIT_FLAG_ABSTIME (1 << 0)
|
| 1686 |
|
| 1687 | __u16 flags;
|
| 1688 |
|
| 1689 |
|
| 1690 | __u32 pad;
|
| 1691 |
|
| 1692 |
|
| 1693 | __u64 value;
|
| 1694 |
|
| 1695 |
|
| 1696 | __u64 mask;
|
| 1697 |
|
| 1698 | |
| 1699 | * @timeout: how long to wait before bailing, value in nanoseconds.
|
| 1700 | * Without DRM_XE_UFENCE_WAIT_FLAG_ABSTIME flag set (relative timeout)
|
| 1701 | * it contains timeout expressed in nanoseconds to wait (fence will
|
| 1702 | * expire at now() + timeout).
|
| 1703 | * When DRM_XE_UFENCE_WAIT_FLAG_ABSTIME flag is set (absolute timeout) wait
|
| 1704 | * will end at timeout (uses system CLOCK_MONOTONIC).
|
| 1705 | * Passing negative timeout leads to never ending wait.
|
| 1706 | *
|
| 1707 | * On relative timeout this value is updated with timeout left
|
| 1708 | * (for restarting the call in case of signal delivery).
|
| 1709 | * On absolute timeout this value stays intact (restarted call still
|
| 1710 | * expire at the same point of time).
|
| 1711 |
|
| 1712 | __s64 timeout;
|
| 1713 |
|
| 1714 |
|
| 1715 | __u32 exec_queue_id;
|
| 1716 |
|
| 1717 |
|
| 1718 | __u32 pad2;
|
| 1719 |
|
| 1720 |
|
| 1721 | __u64 reserved[2];
|
| 1722 | };
|
| 1723 |
|
| 1724 | |
| 1725 | * enum drm_xe_observation_type - Observation stream types
|
| 1726 |
|
| 1727 | enum drm_xe_observation_type {
|
| 1728 |
|
| 1729 | DRM_XE_OBSERVATION_TYPE_OA,
|
| 1730 |
|
| 1731 | DRM_XE_OBSERVATION_TYPE_EU_STALL,
|
| 1732 | };
|
| 1733 |
|
| 1734 | |
| 1735 | * enum drm_xe_observation_op - Observation stream ops
|
| 1736 |
|
| 1737 | enum drm_xe_observation_op {
|
| 1738 |
|
| 1739 | DRM_XE_OBSERVATION_OP_STREAM_OPEN,
|
| 1740 |
|
| 1741 |
|
| 1742 | DRM_XE_OBSERVATION_OP_ADD_CONFIG,
|
| 1743 |
|
| 1744 |
|
| 1745 | DRM_XE_OBSERVATION_OP_REMOVE_CONFIG,
|
| 1746 | };
|
| 1747 |
|
| 1748 | |
| 1749 | * struct drm_xe_observation_param - Input of &DRM_IOCTL_XE_OBSERVATION
|
| 1750 | *
|
| 1751 | * The observation layer enables multiplexing observation streams of
|
| 1752 | * multiple types. The actual params for a particular stream operation are
|
| 1753 | * supplied via the @param pointer (use __copy_from_user to get these
|
| 1754 | * params).
|
| 1755 |
|
| 1756 | struct drm_xe_observation_param {
|
| 1757 |
|
| 1758 | __u64 extensions;
|
| 1759 |
|
| 1760 | __u64 observation_type;
|
| 1761 |
|
| 1762 | __u64 observation_op;
|
| 1763 |
|
| 1764 | __u64 param;
|
| 1765 | };
|
| 1766 |
|
| 1767 | |
| 1768 | * enum drm_xe_observation_ioctls - Observation stream fd ioctls
|
| 1769 | *
|
| 1770 | * Information exchanged between userspace and kernel for observation fd
|
| 1771 | * ioctls is stream type specific
|
| 1772 |
|
| 1773 | enum drm_xe_observation_ioctls {
|
| 1774 |
|
| 1775 | DRM_XE_OBSERVATION_IOCTL_ENABLE = _IO('i', 0x0),
|
| 1776 |
|
| 1777 |
|
| 1778 | DRM_XE_OBSERVATION_IOCTL_DISABLE = _IO('i', 0x1),
|
| 1779 |
|
| 1780 |
|
| 1781 | DRM_XE_OBSERVATION_IOCTL_CONFIG = _IO('i', 0x2),
|
| 1782 |
|
| 1783 |
|
| 1784 | DRM_XE_OBSERVATION_IOCTL_STATUS = _IO('i', 0x3),
|
| 1785 |
|
| 1786 |
|
| 1787 | DRM_XE_OBSERVATION_IOCTL_INFO = _IO('i', 0x4),
|
| 1788 | };
|
| 1789 |
|
| 1790 | |
| 1791 | * enum drm_xe_oa_unit_type - OA unit types
|
| 1792 |
|
| 1793 | enum drm_xe_oa_unit_type {
|
| 1794 | |
| 1795 | * @DRM_XE_OA_UNIT_TYPE_OAG: OAG OA unit. OAR/OAC are considered
|
| 1796 | * sub-types of OAG. For OAR/OAC, use OAG.
|
| 1797 |
|
| 1798 | DRM_XE_OA_UNIT_TYPE_OAG,
|
| 1799 |
|
| 1800 |
|
| 1801 | DRM_XE_OA_UNIT_TYPE_OAM,
|
| 1802 |
|
| 1803 |
|
| 1804 | DRM_XE_OA_UNIT_TYPE_OAM_SAG,
|
| 1805 |
|
| 1806 |
|
| 1807 | DRM_XE_OA_UNIT_TYPE_MERT,
|
| 1808 | };
|
| 1809 |
|
| 1810 | |
| 1811 | * struct drm_xe_oa_unit - describe OA unit
|
| 1812 |
|
| 1813 | struct drm_xe_oa_unit {
|
| 1814 |
|
| 1815 | __u64 extensions;
|
| 1816 |
|
| 1817 |
|
| 1818 | __u32 oa_unit_id;
|
| 1819 |
|
| 1820 |
|
| 1821 | __u32 oa_unit_type;
|
| 1822 |
|
| 1823 |
|
| 1824 | __u64 capabilities;
|
| 1825 | #define DRM_XE_OA_CAPS_BASE (1 << 0)
|
| 1826 | #define DRM_XE_OA_CAPS_SYNCS (1 << 1)
|
| 1827 | #define DRM_XE_OA_CAPS_OA_BUFFER_SIZE (1 << 2)
|
| 1828 | #define DRM_XE_OA_CAPS_WAIT_NUM_REPORTS (1 << 3)
|
| 1829 | #define DRM_XE_OA_CAPS_OAM (1 << 4)
|
| 1830 | #define DRM_XE_OA_CAPS_OA_UNIT_GT_ID (1 << 5)
|
| 1831 |
|
| 1832 |
|
| 1833 | __u64 oa_timestamp_freq;
|
| 1834 |
|
| 1835 |
|
| 1836 | __u16 gt_id;
|
| 1837 |
|
| 1838 |
|
| 1839 | __u16 reserved1[3];
|
| 1840 |
|
| 1841 |
|
| 1842 | __u64 reserved[3];
|
| 1843 |
|
| 1844 |
|
| 1845 | __u64 num_engines;
|
| 1846 |
|
| 1847 |
|
| 1848 | struct drm_xe_engine_class_instance eci[];
|
| 1849 | };
|
| 1850 |
|
| 1851 | |
| 1852 | * struct drm_xe_query_oa_units - describe OA units
|
| 1853 | *
|
| 1854 | * If a query is made with a struct drm_xe_device_query where .query
|
| 1855 | * is equal to DRM_XE_DEVICE_QUERY_OA_UNITS, then the reply uses struct
|
| 1856 | * drm_xe_query_oa_units in .data.
|
| 1857 | *
|
| 1858 | * OA unit properties for all OA units can be accessed using a code block
|
| 1859 | * such as the one below:
|
| 1860 | *
|
| 1861 | * .. code-block:: C
|
| 1862 | *
|
| 1863 | * struct drm_xe_query_oa_units *qoa;
|
| 1864 | * struct drm_xe_oa_unit *oau;
|
| 1865 | * u8 *poau;
|
| 1866 | *
|
| 1867 | * // malloc qoa and issue DRM_XE_DEVICE_QUERY_OA_UNITS. Then:
|
| 1868 | * poau = (u8 *)&qoa->oa_units[0];
|
| 1869 | * for (int i = 0; i < qoa->num_oa_units; i++) {
|
| 1870 | * oau = (struct drm_xe_oa_unit *)poau;
|
| 1871 | * // Access 'struct drm_xe_oa_unit' fields here
|
| 1872 | * poau += sizeof(*oau) + oau->num_engines * sizeof(oau->eci[0]);
|
| 1873 | * }
|
| 1874 |
|
| 1875 | struct drm_xe_query_oa_units {
|
| 1876 |
|
| 1877 | __u64 extensions;
|
| 1878 |
|
| 1879 | __u32 num_oa_units;
|
| 1880 |
|
| 1881 | __u32 pad;
|
| 1882 | |
| 1883 | * @oa_units: &struct drm_xe_oa_unit array returned for this device.
|
| 1884 | * Written below as a u64 array to avoid problems with nested flexible
|
| 1885 | * arrays with some compilers
|
| 1886 |
|
| 1887 | __u64 oa_units[];
|
| 1888 | };
|
| 1889 |
|
| 1890 | |
| 1891 | * enum drm_xe_oa_format_type - OA format types as specified in PRM/Bspec
|
| 1892 | * 52198/60942
|
| 1893 |
|
| 1894 | enum drm_xe_oa_format_type {
|
| 1895 |
|
| 1896 | DRM_XE_OA_FMT_TYPE_OAG,
|
| 1897 |
|
| 1898 | DRM_XE_OA_FMT_TYPE_OAR,
|
| 1899 |
|
| 1900 | DRM_XE_OA_FMT_TYPE_OAM,
|
| 1901 |
|
| 1902 | DRM_XE_OA_FMT_TYPE_OAC,
|
| 1903 |
|
| 1904 | DRM_XE_OA_FMT_TYPE_OAM_MPEC,
|
| 1905 |
|
| 1906 | DRM_XE_OA_FMT_TYPE_PEC,
|
| 1907 | };
|
| 1908 |
|
| 1909 | |
| 1910 | * enum drm_xe_oa_property_id - OA stream property IDs
|
| 1911 | *
|
| 1912 | * Stream params are specified as a chain of &struct drm_xe_ext_set_property
|
| 1913 | * structs, with property values from &enum drm_xe_oa_property_id and
|
| 1914 | * &struct drm_xe_user_extension base.name set to %DRM_XE_OA_EXTENSION_SET_PROPERTY.
|
| 1915 | * The param field in &struct drm_xe_observation_param points to the first
|
| 1916 | * &struct drm_xe_ext_set_property struct.
|
| 1917 | *
|
| 1918 | * Exactly the same mechanism is also used for stream reconfiguration using the
|
| 1919 | * %DRM_XE_OBSERVATION_IOCTL_CONFIG observation stream fd ioctl, though only a
|
| 1920 | * subset of properties below can be specified for stream reconfiguration.
|
| 1921 |
|
| 1922 | enum drm_xe_oa_property_id {
|
| 1923 | #define DRM_XE_OA_EXTENSION_SET_PROPERTY 0
|
| 1924 | |
| 1925 | * @DRM_XE_OA_PROPERTY_OA_UNIT_ID: ID of the OA unit on which to open
|
| 1926 | * the OA stream, see oa_unit_id in &struct drm_xe_oa_unit.
|
| 1927 | * Defaults to 0 if not provided.
|
| 1928 |
|
| 1929 | DRM_XE_OA_PROPERTY_OA_UNIT_ID = 1,
|
| 1930 |
|
| 1931 | |
| 1932 | * @DRM_XE_OA_PROPERTY_SAMPLE_OA: A value of 1 requests inclusion of raw
|
| 1933 | * OA unit reports or stream samples in a global buffer attached to an
|
| 1934 | * OA unit.
|
| 1935 |
|
| 1936 | DRM_XE_OA_PROPERTY_SAMPLE_OA,
|
| 1937 |
|
| 1938 | |
| 1939 | * @DRM_XE_OA_PROPERTY_OA_METRIC_SET: OA metrics defining contents of OA
|
| 1940 | * reports, previously added via %DRM_XE_OBSERVATION_OP_ADD_CONFIG.
|
| 1941 |
|
| 1942 | DRM_XE_OA_PROPERTY_OA_METRIC_SET,
|
| 1943 |
|
| 1944 |
|
| 1945 | DRM_XE_OA_PROPERTY_OA_FORMAT,
|
| 1946 | |
| 1947 | * OA_FORMAT's are specified the same way as in PRM/Bspec 52198/60942,
|
| 1948 | * in terms of the following quantities: a. &enum drm_xe_oa_format_type
|
| 1949 | * b. Counter select c. Counter size and d. BC report. Also refer to the
|
| 1950 | * oa_formats array in drivers/gpu/drm/xe/xe_oa.c.
|
| 1951 |
|
| 1952 | #define DRM_XE_OA_FORMAT_MASK_FMT_TYPE (0xffu << 0)
|
| 1953 | #define DRM_XE_OA_FORMAT_MASK_COUNTER_SEL (0xffu << 8)
|
| 1954 | #define DRM_XE_OA_FORMAT_MASK_COUNTER_SIZE (0xffu << 16)
|
| 1955 | #define DRM_XE_OA_FORMAT_MASK_BC_REPORT (0xffu << 24)
|
| 1956 |
|
| 1957 | |
| 1958 | * @DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT: Requests periodic OA unit
|
| 1959 | * sampling with sampling frequency proportional to 2^(period_exponent + 1)
|
| 1960 |
|
| 1961 | DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT,
|
| 1962 |
|
| 1963 | |
| 1964 | * @DRM_XE_OA_PROPERTY_OA_DISABLED: A value of 1 will open the OA
|
| 1965 | * stream in a DISABLED state (see %DRM_XE_OBSERVATION_IOCTL_ENABLE).
|
| 1966 |
|
| 1967 | DRM_XE_OA_PROPERTY_OA_DISABLED,
|
| 1968 |
|
| 1969 | |
| 1970 | * @DRM_XE_OA_PROPERTY_EXEC_QUEUE_ID: Open the stream for a specific
|
| 1971 | * exec_queue_id. OA queries can be executed on this exec queue.
|
| 1972 |
|
| 1973 | DRM_XE_OA_PROPERTY_EXEC_QUEUE_ID,
|
| 1974 |
|
| 1975 | |
| 1976 | * @DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE: Optional engine instance to
|
| 1977 | * pass along with %DRM_XE_OA_PROPERTY_EXEC_QUEUE_ID or will default to 0.
|
| 1978 |
|
| 1979 | DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE,
|
| 1980 |
|
| 1981 | |
| 1982 | * @DRM_XE_OA_PROPERTY_NO_PREEMPT: Allow preemption and timeslicing
|
| 1983 | * to be disabled for the stream exec queue.
|
| 1984 |
|
| 1985 | DRM_XE_OA_PROPERTY_NO_PREEMPT,
|
| 1986 |
|
| 1987 | |
| 1988 | * @DRM_XE_OA_PROPERTY_NUM_SYNCS: Number of syncs in the sync array
|
| 1989 | * specified in %DRM_XE_OA_PROPERTY_SYNCS
|
| 1990 |
|
| 1991 | DRM_XE_OA_PROPERTY_NUM_SYNCS,
|
| 1992 |
|
| 1993 | |
| 1994 | * @DRM_XE_OA_PROPERTY_SYNCS: Pointer to &struct drm_xe_sync array
|
| 1995 | * with array size specified via %DRM_XE_OA_PROPERTY_NUM_SYNCS. OA
|
| 1996 | * configuration will wait till input fences signal. Output fences
|
| 1997 | * will signal after the new OA configuration takes effect. For
|
| 1998 | * %DRM_XE_SYNC_TYPE_USER_FENCE, addr is a user pointer, similar
|
| 1999 | * to the VM bind case.
|
| 2000 |
|
| 2001 | DRM_XE_OA_PROPERTY_SYNCS,
|
| 2002 |
|
| 2003 | |
| 2004 | * @DRM_XE_OA_PROPERTY_OA_BUFFER_SIZE: Size of OA buffer to be
|
| 2005 | * allocated by the driver in bytes. Supported sizes are powers of
|
| 2006 | * 2 from 128 KiB to 128 MiB. When not specified, a 16 MiB OA
|
| 2007 | * buffer is allocated by default.
|
| 2008 |
|
| 2009 | DRM_XE_OA_PROPERTY_OA_BUFFER_SIZE,
|
| 2010 |
|
| 2011 | |
| 2012 | * @DRM_XE_OA_PROPERTY_WAIT_NUM_REPORTS: Number of reports to wait
|
| 2013 | * for before unblocking poll or read
|
| 2014 |
|
| 2015 | DRM_XE_OA_PROPERTY_WAIT_NUM_REPORTS,
|
| 2016 | };
|
| 2017 |
|
| 2018 | |
| 2019 | * struct drm_xe_oa_config - OA metric configuration
|
| 2020 | *
|
| 2021 | * Multiple OA configs can be added using %DRM_XE_OBSERVATION_OP_ADD_CONFIG. A
|
| 2022 | * particular config can be specified when opening an OA stream using
|
| 2023 | * %DRM_XE_OA_PROPERTY_OA_METRIC_SET property.
|
| 2024 |
|
| 2025 | struct drm_xe_oa_config {
|
| 2026 |
|
| 2027 | __u64 extensions;
|
| 2028 |
|
| 2029 |
|
| 2030 | char uuid[36];
|
| 2031 |
|
| 2032 |
|
| 2033 | __u32 n_regs;
|
| 2034 |
|
| 2035 | |
| 2036 | * @regs_ptr: Pointer to (register address, value) pairs for OA config
|
| 2037 | * registers. Expected length of buffer is: (2 * sizeof(u32) * @n_regs).
|
| 2038 |
|
| 2039 | __u64 regs_ptr;
|
| 2040 | };
|
| 2041 |
|
| 2042 | |
| 2043 | * struct drm_xe_oa_stream_status - OA stream status returned from
|
| 2044 | * %DRM_XE_OBSERVATION_IOCTL_STATUS observation stream fd ioctl. Userspace can
|
| 2045 | * call the ioctl to query stream status in response to EIO errno from
|
| 2046 | * observation fd read().
|
| 2047 |
|
| 2048 | struct drm_xe_oa_stream_status {
|
| 2049 |
|
| 2050 | __u64 extensions;
|
| 2051 |
|
| 2052 |
|
| 2053 | __u64 oa_status;
|
| 2054 | #define DRM_XE_OASTATUS_MMIO_TRG_Q_FULL (1 << 3)
|
| 2055 | #define DRM_XE_OASTATUS_COUNTER_OVERFLOW (1 << 2)
|
| 2056 | #define DRM_XE_OASTATUS_BUFFER_OVERFLOW (1 << 1)
|
| 2057 | #define DRM_XE_OASTATUS_REPORT_LOST (1 << 0)
|
| 2058 |
|
| 2059 |
|
| 2060 | __u64 reserved[3];
|
| 2061 | };
|
| 2062 |
|
| 2063 | |
| 2064 | * struct drm_xe_oa_stream_info - OA stream info returned from
|
| 2065 | * %DRM_XE_OBSERVATION_IOCTL_INFO observation stream fd ioctl
|
| 2066 |
|
| 2067 | struct drm_xe_oa_stream_info {
|
| 2068 |
|
| 2069 | __u64 extensions;
|
| 2070 |
|
| 2071 |
|
| 2072 | __u64 oa_buf_size;
|
| 2073 |
|
| 2074 |
|
| 2075 | __u64 reserved[3];
|
| 2076 | };
|
| 2077 |
|
| 2078 | |
| 2079 | * enum drm_xe_pxp_session_type - Supported PXP session types.
|
| 2080 | *
|
| 2081 | * We currently only support HWDRM sessions, which are used for protected
|
| 2082 | * content that ends up being displayed, but the HW supports multiple types, so
|
| 2083 | * we might extend support in the future.
|
| 2084 |
|
| 2085 | enum drm_xe_pxp_session_type {
|
| 2086 |
|
| 2087 | DRM_XE_PXP_TYPE_NONE = 0,
|
| 2088 | |
| 2089 | * @DRM_XE_PXP_TYPE_HWDRM: HWDRM sessions are used for content that ends
|
| 2090 | * up on the display.
|
| 2091 |
|
| 2092 | DRM_XE_PXP_TYPE_HWDRM = 1,
|
| 2093 | };
|
| 2094 |
|
| 2095 |
|
| 2096 | #define DRM_XE_PXP_HWDRM_DEFAULT_SESSION 0xf
|
| 2097 |
|
| 2098 | |
| 2099 | * enum drm_xe_eu_stall_property_id - EU stall sampling input property ids.
|
| 2100 | *
|
| 2101 | * These properties are passed to the driver at open as a chain of
|
| 2102 | * &struct drm_xe_ext_set_property structures with property set to these
|
| 2103 | * properties' enums and value set to the corresponding values of these
|
| 2104 | * properties. &struct drm_xe_user_extension base.name should be set to
|
| 2105 | * %DRM_XE_EU_STALL_EXTENSION_SET_PROPERTY.
|
| 2106 | *
|
| 2107 | * With the file descriptor obtained from open, user space must enable
|
| 2108 | * the EU stall stream fd with %DRM_XE_OBSERVATION_IOCTL_ENABLE before
|
| 2109 | * calling read(). EIO errno from read() indicates HW dropped data
|
| 2110 | * due to full buffer.
|
| 2111 |
|
| 2112 | enum drm_xe_eu_stall_property_id {
|
| 2113 | #define DRM_XE_EU_STALL_EXTENSION_SET_PROPERTY 0
|
| 2114 | |
| 2115 | * @DRM_XE_EU_STALL_PROP_GT_ID: gt_id of the GT on which
|
| 2116 | * EU stall data will be captured.
|
| 2117 |
|
| 2118 | DRM_XE_EU_STALL_PROP_GT_ID = 1,
|
| 2119 |
|
| 2120 | |
| 2121 | * @DRM_XE_EU_STALL_PROP_SAMPLE_RATE: Sampling rate in
|
| 2122 | * GPU cycles from sampling_rates in &struct drm_xe_query_eu_stall
|
| 2123 |
|
| 2124 | DRM_XE_EU_STALL_PROP_SAMPLE_RATE,
|
| 2125 |
|
| 2126 | |
| 2127 | * @DRM_XE_EU_STALL_PROP_WAIT_NUM_REPORTS: Minimum number of
|
| 2128 | * EU stall data reports to be present in the kernel buffer
|
| 2129 | * before unblocking a blocked poll or read.
|
| 2130 |
|
| 2131 | DRM_XE_EU_STALL_PROP_WAIT_NUM_REPORTS,
|
| 2132 | };
|
| 2133 |
|
| 2134 | |
| 2135 | * struct drm_xe_query_eu_stall - Information about EU stall sampling.
|
| 2136 | *
|
| 2137 | * If a query is made with a &struct drm_xe_device_query where .query
|
| 2138 | * is equal to %DRM_XE_DEVICE_QUERY_EU_STALL, then the reply uses
|
| 2139 | * &struct drm_xe_query_eu_stall in .data.
|
| 2140 |
|
| 2141 | struct drm_xe_query_eu_stall {
|
| 2142 |
|
| 2143 | __u64 extensions;
|
| 2144 |
|
| 2145 |
|
| 2146 | __u64 capabilities;
|
| 2147 | #define DRM_XE_EU_STALL_CAPS_BASE (1 << 0)
|
| 2148 |
|
| 2149 |
|
| 2150 | __u64 record_size;
|
| 2151 |
|
| 2152 |
|
| 2153 | __u64 per_xecore_buf_size;
|
| 2154 |
|
| 2155 |
|
| 2156 | __u64 reserved[5];
|
| 2157 |
|
| 2158 |
|
| 2159 | __u64 num_sampling_rates;
|
| 2160 |
|
| 2161 | |
| 2162 | * @sampling_rates: Flexible array of sampling rates
|
| 2163 | * sorted in the fastest to slowest order.
|
| 2164 | * Sampling rates are specified in GPU clock cycles.
|
| 2165 |
|
| 2166 | __u64 sampling_rates[];
|
| 2167 | };
|
| 2168 |
|
| 2169 | |
| 2170 | * struct drm_xe_madvise - Input of &DRM_IOCTL_XE_MADVISE
|
| 2171 | *
|
| 2172 | * This structure is used to set memory attributes for a virtual address range
|
| 2173 | * in a VM. The type of attribute is specified by @type, and the corresponding
|
| 2174 | * union member is used to provide additional parameters for @type.
|
| 2175 | *
|
| 2176 | * Supported attribute types:
|
| 2177 | * - DRM_XE_MEM_RANGE_ATTR_PREFERRED_LOC: Set preferred memory location.
|
| 2178 | * - DRM_XE_MEM_RANGE_ATTR_ATOMIC: Set atomic access policy.
|
| 2179 | * - DRM_XE_MEM_RANGE_ATTR_PAT: Set page attribute table index.
|
| 2180 | * - DRM_XE_VMA_ATTR_PURGEABLE_STATE: Set purgeable state for BOs.
|
| 2181 | *
|
| 2182 | * Example:
|
| 2183 | *
|
| 2184 | * .. code-block:: C
|
| 2185 | *
|
| 2186 | * struct drm_xe_madvise madvise = {
|
| 2187 | * .vm_id = vm_id,
|
| 2188 | * .start = 0x100000,
|
| 2189 | * .range = 0x2000,
|
| 2190 | * .type = DRM_XE_MEM_RANGE_ATTR_ATOMIC,
|
| 2191 | * .atomic.val = DRM_XE_ATOMIC_DEVICE,
|
| 2192 | * };
|
| 2193 | *
|
| 2194 | * ioctl(fd, DRM_IOCTL_XE_MADVISE, &madvise);
|
| 2195 | *
|
| 2196 |
|
| 2197 | struct drm_xe_madvise {
|
| 2198 |
|
| 2199 | __u64 extensions;
|
| 2200 |
|
| 2201 |
|
| 2202 | __u64 start;
|
| 2203 |
|
| 2204 |
|
| 2205 | __u64 range;
|
| 2206 |
|
| 2207 |
|
| 2208 | __u32 vm_id;
|
| 2209 |
|
| 2210 | #define DRM_XE_MEM_RANGE_ATTR_PREFERRED_LOC 0
|
| 2211 | #define DRM_XE_MEM_RANGE_ATTR_ATOMIC 1
|
| 2212 | #define DRM_XE_MEM_RANGE_ATTR_PAT 2
|
| 2213 | #define DRM_XE_VMA_ATTR_PURGEABLE_STATE 3
|
| 2214 |
|
| 2215 | __u32 type;
|
| 2216 |
|
| 2217 | union {
|
| 2218 | |
| 2219 | * @preferred_mem_loc: preferred memory location
|
| 2220 | *
|
| 2221 | * Used when @type == DRM_XE_MEM_RANGE_ATTR_PREFERRED_LOC
|
| 2222 | *
|
| 2223 | * Supported values for @preferred_mem_loc.devmem_fd:
|
| 2224 | * - DRM_XE_PREFERRED_LOC_DEFAULT_DEVICE: set vram of fault tile as preferred loc
|
| 2225 | * - DRM_XE_PREFERRED_LOC_DEFAULT_SYSTEM: set smem as preferred loc
|
| 2226 | *
|
| 2227 | * Supported values for @preferred_mem_loc.migration_policy:
|
| 2228 | * - DRM_XE_MIGRATE_ALL_PAGES
|
| 2229 | * - DRM_XE_MIGRATE_ONLY_SYSTEM_PAGES
|
| 2230 |
|
| 2231 | struct {
|
| 2232 | #define DRM_XE_PREFERRED_LOC_DEFAULT_DEVICE 0
|
| 2233 | #define DRM_XE_PREFERRED_LOC_DEFAULT_SYSTEM -1
|
| 2234 | |
| 2235 | * @preferred_mem_loc.devmem_fd:
|
| 2236 | * Device file-descriptor of the device where the
|
| 2237 | * preferred memory is located, or one of the
|
| 2238 | * above special values. Please also see
|
| 2239 | * @preferred_mem_loc.region_instance below.
|
| 2240 |
|
| 2241 | __u32 devmem_fd;
|
| 2242 |
|
| 2243 | #define DRM_XE_MIGRATE_ALL_PAGES 0
|
| 2244 | #define DRM_XE_MIGRATE_ONLY_SYSTEM_PAGES 1
|
| 2245 |
|
| 2246 | __u16 migration_policy;
|
| 2247 |
|
| 2248 | |
| 2249 | * @preferred_mem_loc.region_instance : Region instance.
|
| 2250 | * MBZ if @devmem_fd <= %DRM_XE_PREFERRED_LOC_DEFAULT_DEVICE.
|
| 2251 | * Otherwise should point to the desired device
|
| 2252 | * VRAM instance of the device indicated by
|
| 2253 | * @preferred_mem_loc.devmem_fd.
|
| 2254 |
|
| 2255 | __u16 region_instance;
|
| 2256 |
|
| 2257 |
|
| 2258 | __u64 reserved;
|
| 2259 | } preferred_mem_loc;
|
| 2260 |
|
| 2261 | |
| 2262 | * @atomic: Atomic access policy
|
| 2263 | *
|
| 2264 | * Used when @type == DRM_XE_MEM_RANGE_ATTR_ATOMIC.
|
| 2265 | *
|
| 2266 | * Supported values for @atomic.val:
|
| 2267 | * - DRM_XE_ATOMIC_UNDEFINED: Undefined or default behaviour.
|
| 2268 | * Support both GPU and CPU atomic operations for system allocator.
|
| 2269 | * Support GPU atomic operations for normal(bo) allocator.
|
| 2270 | * - DRM_XE_ATOMIC_DEVICE: Support GPU atomic operations.
|
| 2271 | * - DRM_XE_ATOMIC_GLOBAL: Support both GPU and CPU atomic operations.
|
| 2272 | * - DRM_XE_ATOMIC_CPU: Support CPU atomic only, no GPU atomics supported.
|
| 2273 |
|
| 2274 | struct {
|
| 2275 | #define DRM_XE_ATOMIC_UNDEFINED 0
|
| 2276 | #define DRM_XE_ATOMIC_DEVICE 1
|
| 2277 | #define DRM_XE_ATOMIC_GLOBAL 2
|
| 2278 | #define DRM_XE_ATOMIC_CPU 3
|
| 2279 |
|
| 2280 | __u32 val;
|
| 2281 |
|
| 2282 |
|
| 2283 | __u32 pad;
|
| 2284 |
|
| 2285 |
|
| 2286 | __u64 reserved;
|
| 2287 | } atomic;
|
| 2288 |
|
| 2289 | |
| 2290 | * @pat_index: Page attribute table index
|
| 2291 | *
|
| 2292 | * Used when @type == DRM_XE_MEM_RANGE_ATTR_PAT.
|
| 2293 |
|
| 2294 | struct {
|
| 2295 |
|
| 2296 | __u32 val;
|
| 2297 |
|
| 2298 |
|
| 2299 | __u32 pad;
|
| 2300 |
|
| 2301 |
|
| 2302 | __u64 reserved;
|
| 2303 | } pat_index;
|
| 2304 |
|
| 2305 | |
| 2306 | * @purge_state_val: Purgeable state configuration
|
| 2307 | *
|
| 2308 | * Used when @type == DRM_XE_VMA_ATTR_PURGEABLE_STATE.
|
| 2309 | *
|
| 2310 | * Configures the purgeable state of buffer objects in the specified
|
| 2311 | * virtual address range. This allows applications to hint to the kernel
|
| 2312 | * about bo's usage patterns for better memory management.
|
| 2313 | *
|
| 2314 | * By default all VMAs are in WILLNEED state.
|
| 2315 | *
|
| 2316 | * Supported values for @purge_state_val.val:
|
| 2317 | * - DRM_XE_VMA_PURGEABLE_STATE_WILLNEED (0): Marks BO as needed.
|
| 2318 | * If the BO was previously purged, the kernel sets the __u32 at
|
| 2319 | * @retained_ptr to 0 (backing store lost) so the application knows
|
| 2320 | * it must recreate the BO.
|
| 2321 | *
|
| 2322 | * - DRM_XE_VMA_PURGEABLE_STATE_DONTNEED (1): Marks BO as not currently
|
| 2323 | * needed. Kernel may purge it under memory pressure to reclaim memory.
|
| 2324 | * Only applies to non-shared BOs. The kernel sets the __u32 at
|
| 2325 | * @retained_ptr to 1 if the backing store still exists (not yet purged),
|
| 2326 | * or 0 if it was already purged.
|
| 2327 | *
|
| 2328 | * Important: Once marked as DONTNEED, touching the BO's memory
|
| 2329 | * is undefined behavior. It may succeed temporarily (before the
|
| 2330 | * kernel purges the backing store) but will suddenly fail once
|
| 2331 | * the BO transitions to PURGED state.
|
| 2332 | *
|
| 2333 | * To transition back: use WILLNEED and check @retained_ptr —
|
| 2334 | * if 0, backing store was lost and the BO must be recreated.
|
| 2335 | *
|
| 2336 | * The following operations are blocked in DONTNEED state to
|
| 2337 | * prevent the BO from being re-mapped after madvise:
|
| 2338 | * - New mmap() calls: Fail with -EBUSY
|
| 2339 | * - VM_BIND operations: Fail with -EBUSY
|
| 2340 | * - New dma-buf exports: Fail with -EBUSY
|
| 2341 | * - CPU page faults (existing mmap): Fail with SIGBUS
|
| 2342 | * - GPU page faults (fault-mode VMs): Fail with -EACCES
|
| 2343 |
|
| 2344 | struct {
|
| 2345 | #define DRM_XE_VMA_PURGEABLE_STATE_WILLNEED 0
|
| 2346 | #define DRM_XE_VMA_PURGEABLE_STATE_DONTNEED 1
|
| 2347 |
|
| 2348 | __u32 val;
|
| 2349 |
|
| 2350 |
|
| 2351 | __u32 pad;
|
| 2352 | |
| 2353 | * @purge_state_val.retained_ptr: Pointer to a __u32 output
|
| 2354 | * field for backing store status.
|
| 2355 | *
|
| 2356 | * Userspace must initialize the __u32 value at this address
|
| 2357 | * to 0 before the ioctl. Kernel writes a __u32 after the
|
| 2358 | * operation:
|
| 2359 | * - 1 if backing store exists (not purged)
|
| 2360 | * - 0 if backing store was purged
|
| 2361 | *
|
| 2362 | * If userspace fails to initialize to 0, ioctl returns -EINVAL.
|
| 2363 | * This ensures a safe default (0 = assume purged) if kernel
|
| 2364 | * cannot write the result.
|
| 2365 | *
|
| 2366 | * Similar to i915's drm_i915_gem_madvise.retained field.
|
| 2367 |
|
| 2368 | __u64 retained_ptr;
|
| 2369 | } purge_state_val;
|
| 2370 | };
|
| 2371 |
|
| 2372 |
|
| 2373 | __u64 reserved[2];
|
| 2374 | };
|
| 2375 |
|
| 2376 | |
| 2377 | * struct drm_xe_mem_range_attr - Output of &DRM_IOCTL_XE_VM_QUERY_MEM_RANGE_ATTRS
|
| 2378 | *
|
| 2379 | * This structure is provided by userspace and filled by KMD in response to the
|
| 2380 | * DRM_IOCTL_XE_VM_QUERY_MEM_RANGE_ATTRS ioctl. It describes memory attributes of
|
| 2381 | * memory ranges within a user specified address range in a VM.
|
| 2382 | *
|
| 2383 | * The structure includes information such as atomic access policy,
|
| 2384 | * page attribute table (PAT) index, and preferred memory location.
|
| 2385 | * Userspace allocates an array of these structures and passes a pointer to the
|
| 2386 | * ioctl to retrieve attributes for each memory range.
|
| 2387 |
|
| 2388 | struct drm_xe_mem_range_attr {
|
| 2389 |
|
| 2390 | __u64 extensions;
|
| 2391 |
|
| 2392 |
|
| 2393 | __u64 start;
|
| 2394 |
|
| 2395 |
|
| 2396 | __u64 end;
|
| 2397 |
|
| 2398 |
|
| 2399 | struct {
|
| 2400 |
|
| 2401 | __u32 devmem_fd;
|
| 2402 |
|
| 2403 |
|
| 2404 | __u32 migration_policy;
|
| 2405 | } preferred_mem_loc;
|
| 2406 |
|
| 2407 |
|
| 2408 | struct {
|
| 2409 |
|
| 2410 | __u32 val;
|
| 2411 |
|
| 2412 |
|
| 2413 | __u32 reserved;
|
| 2414 | } atomic;
|
| 2415 |
|
| 2416 |
|
| 2417 | struct {
|
| 2418 |
|
| 2419 | __u32 val;
|
| 2420 |
|
| 2421 |
|
| 2422 | __u32 reserved;
|
| 2423 | } pat_index;
|
| 2424 |
|
| 2425 |
|
| 2426 | __u64 reserved[2];
|
| 2427 | };
|
| 2428 |
|
| 2429 | |
| 2430 | * struct drm_xe_vm_query_mem_range_attr - Input of &DRM_IOCTL_XE_VM_QUERY_MEM_RANGE_ATTRS
|
| 2431 | *
|
| 2432 | * This structure is used to query memory attributes of memory regions
|
| 2433 | * within a user specified address range in a VM. It provides detailed
|
| 2434 | * information about each memory range, including atomic access policy,
|
| 2435 | * page attribute table (PAT) index, and preferred memory location.
|
| 2436 | *
|
| 2437 | * Userspace first calls the ioctl with @num_mem_ranges = 0,
|
| 2438 | * @sizeof_mem_range_attr = 0 and @vector_of_mem_attr = NULL to retrieve
|
| 2439 | * the number of memory regions and size of each memory range attribute.
|
| 2440 | * Then, it allocates a buffer of that size and calls the ioctl again to fill
|
| 2441 | * the buffer with memory range attributes.
|
| 2442 | *
|
| 2443 | * If second call fails with -ENOSPC, it means memory ranges changed between
|
| 2444 | * first call and now, retry IOCTL again with @num_mem_ranges = 0,
|
| 2445 | * @sizeof_mem_range_attr = 0 and @vector_of_mem_attr = NULL followed by
|
| 2446 | * second ioctl call.
|
| 2447 | *
|
| 2448 | * Example:
|
| 2449 | *
|
| 2450 | * .. code-block:: C
|
| 2451 | *
|
| 2452 | * struct drm_xe_vm_query_mem_range_attr query = {
|
| 2453 | * .vm_id = vm_id,
|
| 2454 | * .start = 0x100000,
|
| 2455 | * .range = 0x2000,
|
| 2456 | * };
|
| 2457 | *
|
| 2458 | * // First ioctl call to get num of mem regions and sizeof each attribute
|
| 2459 | * ioctl(fd, DRM_IOCTL_XE_VM_QUERY_MEM_RANGE_ATTRS, &query);
|
| 2460 | *
|
| 2461 | * // Allocate buffer for the memory region attributes
|
| 2462 | * void *ptr = malloc(query.num_mem_ranges * query.sizeof_mem_range_attr);
|
| 2463 | * void *ptr_start = ptr;
|
| 2464 | *
|
| 2465 | * query.vector_of_mem_attr = (uintptr_t)ptr;
|
| 2466 | *
|
| 2467 | * // Second ioctl call to actually fill the memory attributes
|
| 2468 | * ioctl(fd, DRM_IOCTL_XE_VM_QUERY_MEM_RANGE_ATTRS, &query);
|
| 2469 | *
|
| 2470 | * // Iterate over the returned memory region attributes
|
| 2471 | * for (unsigned int i = 0; i < query.num_mem_ranges; ++i) {
|
| 2472 | * struct drm_xe_mem_range_attr *attr = (struct drm_xe_mem_range_attr *)ptr;
|
| 2473 | *
|
| 2474 | * // Do something with attr
|
| 2475 | *
|
| 2476 | * // Move pointer by one entry
|
| 2477 | * ptr += query.sizeof_mem_range_attr;
|
| 2478 | * }
|
| 2479 | *
|
| 2480 | * free(ptr_start);
|
| 2481 |
|
| 2482 | struct drm_xe_vm_query_mem_range_attr {
|
| 2483 |
|
| 2484 | __u64 extensions;
|
| 2485 |
|
| 2486 |
|
| 2487 | __u32 vm_id;
|
| 2488 |
|
| 2489 |
|
| 2490 | __u32 num_mem_ranges;
|
| 2491 |
|
| 2492 |
|
| 2493 | __u64 start;
|
| 2494 |
|
| 2495 |
|
| 2496 | __u64 range;
|
| 2497 |
|
| 2498 |
|
| 2499 | __u64 sizeof_mem_range_attr;
|
| 2500 |
|
| 2501 |
|
| 2502 | __u64 vector_of_mem_attr;
|
| 2503 |
|
| 2504 |
|
| 2505 | __u64 reserved[2];
|
| 2506 |
|
| 2507 | };
|
| 2508 |
|
| 2509 | |
| 2510 | * struct drm_xe_exec_queue_set_property - exec queue set property
|
| 2511 | *
|
| 2512 | * Sets execution queue properties dynamically.
|
| 2513 | * Currently only %DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY
|
| 2514 | * property can be dynamically set.
|
| 2515 |
|
| 2516 | struct drm_xe_exec_queue_set_property {
|
| 2517 |
|
| 2518 | __u64 extensions;
|
| 2519 |
|
| 2520 |
|
| 2521 | __u32 exec_queue_id;
|
| 2522 |
|
| 2523 |
|
| 2524 | __u32 property;
|
| 2525 |
|
| 2526 |
|
| 2527 | __u64 value;
|
| 2528 |
|
| 2529 |
|
| 2530 | __u64 reserved[2];
|
| 2531 | };
|
| 2532 |
|
| 2533 | |
| 2534 | * DOC: Xe DRM RAS
|
| 2535 | *
|
| 2536 | * The enums and strings defined below map to the attributes of the DRM RAS Netlink Interface.
|
| 2537 | * Refer to Documentation/netlink/specs/drm_ras.yaml for complete interface specification.
|
| 2538 | *
|
| 2539 | * Node Registration
|
| 2540 | * -----------------
|
| 2541 | *
|
| 2542 | * The driver registers DRM RAS nodes for each error severity level.
|
| 2543 | * enum drm_xe_ras_error_severity defines the node-id, while DRM_XE_RAS_ERROR_SEVERITY_NAMES maps
|
| 2544 | * node-id to node-name.
|
| 2545 | *
|
| 2546 | * Error Classification
|
| 2547 | * --------------------
|
| 2548 | *
|
| 2549 | * Each node contains a list of error counters. Each error is identified by a error-id and
|
| 2550 | * an error-name. enum drm_xe_ras_error_component defines the error-id, while
|
| 2551 | * DRM_XE_RAS_ERROR_COMPONENT_NAMES maps error-id to error-name.
|
| 2552 | *
|
| 2553 | * User Interface
|
| 2554 | * --------------
|
| 2555 | *
|
| 2556 | * To retrieve error values of a error counter, userspace applications should
|
| 2557 | * follow the below steps:
|
| 2558 | *
|
| 2559 | * 1. Use command LIST_NODES to enumerate all available nodes
|
| 2560 | * 2. Select node by node-id or node-name
|
| 2561 | * 3. Use command GET_ERROR_COUNTERS to list errors of specific node
|
| 2562 | * 4. Query specific error values using either error-id or error-name
|
| 2563 | *
|
| 2564 | * .. code-block:: C
|
| 2565 | *
|
| 2566 | * // Lookup tables for ID-to-name resolution
|
| 2567 | * static const char *nodes[] = DRM_XE_RAS_ERROR_SEVERITY_NAMES;
|
| 2568 | * static const char *errors[] = DRM_XE_RAS_ERROR_COMPONENT_NAMES;
|
| 2569 | *
|
| 2570 |
|
| 2571 |
|
| 2572 | |
| 2573 | * enum drm_xe_ras_error_severity - DRM RAS error severity.
|
| 2574 |
|
| 2575 | enum drm_xe_ras_error_severity {
|
| 2576 |
|
| 2577 | DRM_XE_RAS_ERR_SEV_CORRECTABLE = 0,
|
| 2578 |
|
| 2579 | DRM_XE_RAS_ERR_SEV_UNCORRECTABLE,
|
| 2580 |
|
| 2581 | DRM_XE_RAS_ERR_SEV_MAX
|
| 2582 | };
|
| 2583 |
|
| 2584 | |
| 2585 | * enum drm_xe_ras_error_component - DRM RAS error component.
|
| 2586 |
|
| 2587 | enum drm_xe_ras_error_component {
|
| 2588 |
|
| 2589 | DRM_XE_RAS_ERR_COMP_CORE_COMPUTE = 1,
|
| 2590 |
|
| 2591 | DRM_XE_RAS_ERR_COMP_SOC_INTERNAL,
|
| 2592 |
|
| 2593 | DRM_XE_RAS_ERR_COMP_DEVICE_MEMORY,
|
| 2594 |
|
| 2595 | DRM_XE_RAS_ERR_COMP_PCIE,
|
| 2596 |
|
| 2597 | DRM_XE_RAS_ERR_COMP_FABRIC,
|
| 2598 |
|
| 2599 | DRM_XE_RAS_ERR_COMP_MAX
|
| 2600 | };
|
| 2601 |
|
| 2602 | |
| 2603 | * Error severity to name mapping.
|
| 2604 |
|
| 2605 | #define DRM_XE_RAS_ERROR_SEVERITY_NAMES { \
|
| 2606 | [DRM_XE_RAS_ERR_SEV_CORRECTABLE] = "correctable-errors", \
|
| 2607 | [DRM_XE_RAS_ERR_SEV_UNCORRECTABLE] = "uncorrectable-errors", \
|
| 2608 | }
|
| 2609 |
|
| 2610 | |
| 2611 | * Error component to name mapping.
|
| 2612 |
|
| 2613 | #define DRM_XE_RAS_ERROR_COMPONENT_NAMES { \
|
| 2614 | [DRM_XE_RAS_ERR_COMP_CORE_COMPUTE] = "core-compute", \
|
| 2615 | [DRM_XE_RAS_ERR_COMP_SOC_INTERNAL] = "soc-internal", \
|
| 2616 | [DRM_XE_RAS_ERR_COMP_DEVICE_MEMORY] = "device-memory", \
|
| 2617 | [DRM_XE_RAS_ERR_COMP_PCIE] = "pcie", \
|
| 2618 | [DRM_XE_RAS_ERR_COMP_FABRIC] = "fabric", \
|
| 2619 | }
|
| 2620 |
|
| 2621 | #if defined(__cplusplus)
|
| 2622 | }
|
| 2623 | #endif
|
| 2624 |
|
| 2625 | #endif
|