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1/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2/*
3 * Copyright (C) 2021-2024 Advanced Micro Devices, Inc.
4 */
5#ifndef _AMD_APML_H_
6#define _AMD_APML_H_
7
8#include <linux/types.h>
9
10/* Mailbox data size for data_in and data_out */
11#define AMD_SBI_MB_DATA_SIZE 4
12
13struct apml_mbox_msg {
14 /*
15 * Mailbox Message ID
16 */
17 __u32 cmd;
18 /*
19 * [0]...[3] mailbox 32bit input/output data
20 */
21 __u32 mb_in_out;
22 /*
23 * Error code is returned in case of soft mailbox error
24 */
25 __u32 fw_ret_code;
26};
27
28struct apml_cpuid_msg {
29 /*
30 * CPUID input
31 * [0]...[3] cpuid func,
32 * [4][5] cpuid: thread
33 * [6] cpuid: ext function & read eax/ebx or ecx/edx
34 * [7:0] -> bits [7:4] -> ext function &
35 * bit [0] read eax/ebx or ecx/edx
36 * CPUID output
37 */
38 __u64 cpu_in_out;
39 /*
40 * Status code for CPUID read
41 */
42 __u32 fw_ret_code;
43 __u32 pad;
44};
45
46struct apml_mcamsr_msg {
47 /*
48 * MCAMSR input
49 * [0]...[3] mca msr func,
50 * [4][5] thread
51 * MCAMSR output
52 */
53 __u64 mcamsr_in_out;
54 /*
55 * Status code for MCA/MSR access
56 */
57 __u32 fw_ret_code;
58 __u32 pad;
59};
60
61struct apml_reg_xfer_msg {
62 /*
63 * RMI register address offset
64 */
65 __u16 reg_addr;
66 /*
67 * Register data for read/write
68 */
69 __u8 data_in_out;
70 /*
71 * Register read or write
72 */
73 __u8 rflag;
74};
75
76struct apml_tsi_xfer_msg {
77 __u8 reg_addr; /* TSI register address offset */
78 __u8 data_in_out; /* Register data for read/write */
79 __u8 rflag; /* Register read or write */
80 __u8 pad; /* Explicit padding */
81};
82
83/*
84 * AMD sideband interface base IOCTL
85 */
86#define SB_BASE_IOCTL_NR 0xF9
87
88/**
89 * DOC: SBRMI_IOCTL_MBOX_CMD
90 *
91 * @Parameters
92 *
93 * @struct apml_mbox_msg
94 * Pointer to the &struct apml_mbox_msg that will contain the protocol
95 * information
96 *
97 * @Description
98 * IOCTL command for APML messages using generic _IOWR
99 * The IOCTL provides userspace access to AMD sideband mailbox protocol
100 * - Mailbox message read/write(0x0~0xFF)
101 * - returning "-EFAULT" if none of the above
102 * "-EPROTOTYPE" error is returned to provide additional error details
103 */
104#define SBRMI_IOCTL_MBOX_CMD _IOWR(SB_BASE_IOCTL_NR, 0, struct apml_mbox_msg)
105
106/**
107 * DOC: SBRMI_IOCTL_CPUID_CMD
108 *
109 * @Parameters
110 *
111 * @struct apml_cpuid_msg
112 * Pointer to the &struct apml_cpuid_msg that will contain the protocol
113 * information
114 *
115 * @Description
116 * IOCTL command for APML messages using generic _IOWR
117 * The IOCTL provides userspace access to AMD sideband cpuid protocol
118 * - CPUID protocol to get CPU details for Function/Ext Function
119 * at thread level
120 * - returning "-EFAULT" if none of the above
121 * "-EPROTOTYPE" error is returned to provide additional error details
122 */
123#define SBRMI_IOCTL_CPUID_CMD _IOWR(SB_BASE_IOCTL_NR, 1, struct apml_cpuid_msg)
124
125/**
126 * DOC: SBRMI_IOCTL_MCAMSR_CMD
127 *
128 * @Parameters
129 *
130 * @struct apml_mcamsr_msg
131 * Pointer to the &struct apml_mcamsr_msg that will contain the protocol
132 * information
133 *
134 * @Description
135 * IOCTL command for APML messages using generic _IOWR
136 * The IOCTL provides userspace access to AMD sideband MCAMSR protocol
137 * - MCAMSR protocol to get MCA bank details for Function at thread level
138 * - returning "-EFAULT" if none of the above
139 * "-EPROTOTYPE" error is returned to provide additional error details
140 */
141#define SBRMI_IOCTL_MCAMSR_CMD _IOWR(SB_BASE_IOCTL_NR, 2, struct apml_mcamsr_msg)
142
143/**
144 * DOC: SBRMI_IOCTL_REG_XFER_CMD
145 *
146 * @Parameters
147 *
148 * @struct apml_reg_xfer_msg
149 * Pointer to the &struct apml_reg_xfer_msg that will contain the protocol
150 * information
151 *
152 * @Description
153 * IOCTL command for APML messages using generic _IOWR
154 * The IOCTL provides userspace access to AMD sideband register xfer protocol
155 * - Register xfer protocol to get/set hardware register for given offset
156 */
157#define SBRMI_IOCTL_REG_XFER_CMD _IOWR(SB_BASE_IOCTL_NR, 3, struct apml_reg_xfer_msg)
158
159/**
160 * DOC: SBTSI_IOCTL_REG_XFER_CMD
161 *
162 * @Parameters
163 *
164 * @struct apml_tsi_xfer_msg
165 * Pointer to the &struct apml_tsi_xfer_msg that will contain the protocol
166 * information
167 *
168 * @Description
169 * IOCTL command for APML TSI messages using generic _IOWR
170 * The IOCTL provides userspace access to AMD sideband TSI register xfer protocol
171 * - TSI protocol to read/write temperature sensor registers
172 */
173#define SBTSI_IOCTL_REG_XFER_CMD _IOWR(SB_BASE_IOCTL_NR, 4, struct apml_tsi_xfer_msg)
174
175#endif /*_AMD_APML_H_*/