projects/linux·blob master · refs

1687 lines · 55.6 KiB

1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Universal Flash Storage Host controller driver
4 * Copyright (C) 2011-2013 Samsung India Software Operations
5 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
6 *
7 * Authors:
8 * Santosh Yaraganavi <[email protected]>
9 * Vinayak Holikatti <[email protected]>
10 */
11
12#ifndef _UFSHCD_H
13#define _UFSHCD_H
14
15#include <linux/bitfield.h>
16#include <linux/blk-crypto-profile.h>
17#include <linux/blk-mq.h>
18#include <linux/devfreq.h>
19#include <linux/fault-inject.h>
20#include <linux/debugfs.h>
21#include <linux/msi.h>
22#include <linux/pm_runtime.h>
23#include <linux/dma-direction.h>
24#include <scsi/scsi_device.h>
25#include <scsi/scsi_host.h>
26#include <ufs/unipro.h>
27#include <ufs/ufs.h>
28#include <ufs/ufs_quirks.h>
29#include <ufs/ufshci.h>
30
31#define UFSHCD "ufshcd"
32
33struct scsi_device;
34struct ufs_hba;
35
36enum dev_cmd_type {
37 DEV_CMD_TYPE_NOP = 0x0,
38 DEV_CMD_TYPE_QUERY = 0x1,
39 DEV_CMD_TYPE_RPMB = 0x2,
40};
41
42enum ufs_event_type {
43 /* uic specific errors */
44 UFS_EVT_PA_ERR = 0,
45 UFS_EVT_DL_ERR,
46 UFS_EVT_NL_ERR,
47 UFS_EVT_TL_ERR,
48 UFS_EVT_DME_ERR,
49
50 /* fatal errors */
51 UFS_EVT_AUTO_HIBERN8_ERR,
52 UFS_EVT_FATAL_ERR,
53 UFS_EVT_LINK_STARTUP_FAIL,
54 UFS_EVT_RESUME_ERR,
55 UFS_EVT_SUSPEND_ERR,
56 UFS_EVT_WL_SUSP_ERR,
57 UFS_EVT_WL_RES_ERR,
58
59 /* abnormal events */
60 UFS_EVT_DEV_RESET,
61 UFS_EVT_HOST_RESET,
62 UFS_EVT_ABORT,
63
64 UFS_EVT_CNT,
65};
66
67/**
68 * struct uic_command - UIC command structure
69 * @command: UIC command
70 * @argument1: UIC command argument 1
71 * @argument2: UIC command argument 2
72 * @argument3: UIC command argument 3
73 * @cmd_active: Indicate if UIC command is outstanding
74 * @done: UIC command completion
75 */
76struct uic_command {
77 const u32 command;
78 const u32 argument1;
79 u32 argument2;
80 u32 argument3;
81 bool cmd_active;
82 struct completion done;
83};
84
85/* Used to differentiate the power management options */
86enum ufs_pm_op {
87 UFS_RUNTIME_PM,
88 UFS_SYSTEM_PM,
89 UFS_SHUTDOWN_PM,
90};
91
92/* Host <-> Device UniPro Link state */
93enum uic_link_state {
94 UIC_LINK_OFF_STATE = 0, /* Link powered down or disabled */
95 UIC_LINK_ACTIVE_STATE = 1, /* Link is in Fast/Slow/Sleep state */
96 UIC_LINK_HIBERN8_STATE = 2, /* Link is in Hibernate state */
97 UIC_LINK_BROKEN_STATE = 3, /* Link is in broken state */
98};
99
100#define ufshcd_is_link_off(hba) ((hba)->uic_link_state == UIC_LINK_OFF_STATE)
101#define ufshcd_is_link_active(hba) ((hba)->uic_link_state == \
102 UIC_LINK_ACTIVE_STATE)
103#define ufshcd_is_link_hibern8(hba) ((hba)->uic_link_state == \
104 UIC_LINK_HIBERN8_STATE)
105#define ufshcd_is_link_broken(hba) ((hba)->uic_link_state == \
106 UIC_LINK_BROKEN_STATE)
107#define ufshcd_set_link_off(hba) ((hba)->uic_link_state = UIC_LINK_OFF_STATE)
108#define ufshcd_set_link_active(hba) ((hba)->uic_link_state = \
109 UIC_LINK_ACTIVE_STATE)
110#define ufshcd_set_link_hibern8(hba) ((hba)->uic_link_state = \
111 UIC_LINK_HIBERN8_STATE)
112#define ufshcd_set_link_broken(hba) ((hba)->uic_link_state = \
113 UIC_LINK_BROKEN_STATE)
114
115#define ufshcd_set_ufs_dev_active(h) \
116 ((h)->curr_dev_pwr_mode = UFS_ACTIVE_PWR_MODE)
117#define ufshcd_set_ufs_dev_sleep(h) \
118 ((h)->curr_dev_pwr_mode = UFS_SLEEP_PWR_MODE)
119#define ufshcd_set_ufs_dev_poweroff(h) \
120 ((h)->curr_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE)
121#define ufshcd_set_ufs_dev_deepsleep(h) \
122 ((h)->curr_dev_pwr_mode = UFS_DEEPSLEEP_PWR_MODE)
123#define ufshcd_is_ufs_dev_active(h) \
124 ((h)->curr_dev_pwr_mode == UFS_ACTIVE_PWR_MODE)
125#define ufshcd_is_ufs_dev_sleep(h) \
126 ((h)->curr_dev_pwr_mode == UFS_SLEEP_PWR_MODE)
127#define ufshcd_is_ufs_dev_poweroff(h) \
128 ((h)->curr_dev_pwr_mode == UFS_POWERDOWN_PWR_MODE)
129#define ufshcd_is_ufs_dev_deepsleep(h) \
130 ((h)->curr_dev_pwr_mode == UFS_DEEPSLEEP_PWR_MODE)
131
132/*
133 * UFS Power management levels.
134 * Each level is in increasing order of power savings, except DeepSleep
135 * which is lower than PowerDown with power on but not PowerDown with
136 * power off.
137 */
138enum ufs_pm_level {
139 UFS_PM_LVL_0,
140 UFS_PM_LVL_1,
141 UFS_PM_LVL_2,
142 UFS_PM_LVL_3,
143 UFS_PM_LVL_4,
144 UFS_PM_LVL_5,
145 UFS_PM_LVL_6,
146 UFS_PM_LVL_MAX
147};
148
149struct ufs_pm_lvl_states {
150 enum ufs_dev_pwr_mode dev_state;
151 enum uic_link_state link_state;
152};
153
154/**
155 * struct ufshcd_lrb - local reference block
156 * @utr_descriptor_ptr: UTRD address of the command
157 * @ucd_req_ptr: UCD address of the command
158 * @ucd_rsp_ptr: Response UPIU address for this command
159 * @ucd_prdt_ptr: PRDT address of the command
160 * @utrd_dma_addr: UTRD dma address for debug
161 * @ucd_prdt_dma_addr: PRDT dma address for debug
162 * @ucd_rsp_dma_addr: UPIU response dma address for debug
163 * @ucd_req_dma_addr: UPIU request dma address for debug
164 * @scsi_status: SCSI status of the command
165 * @command_type: SCSI, UFS, Query.
166 * @lun: LUN of the command
167 * @intr_cmd: Interrupt command (doesn't participate in interrupt aggregation)
168 * @req_abort_skip: skip request abort task flag
169 * @issue_time_stamp: time stamp for debug purposes (CLOCK_MONOTONIC)
170 * @issue_time_stamp_local_clock: time stamp for debug purposes (local_clock)
171 * @compl_time_stamp: time stamp for statistics (CLOCK_MONOTONIC)
172 * @compl_time_stamp_local_clock: time stamp for debug purposes (local_clock)
173 * @crypto_key_slot: the key slot to use for inline crypto (-1 if none)
174 * @data_unit_num: the data unit number for the first block for inline crypto
175 */
176struct ufshcd_lrb {
177 struct utp_transfer_req_desc *utr_descriptor_ptr;
178 struct utp_upiu_req *ucd_req_ptr;
179 struct utp_upiu_rsp *ucd_rsp_ptr;
180 struct ufshcd_sg_entry *ucd_prdt_ptr;
181
182 dma_addr_t utrd_dma_addr;
183 dma_addr_t ucd_req_dma_addr;
184 dma_addr_t ucd_rsp_dma_addr;
185 dma_addr_t ucd_prdt_dma_addr;
186
187 int scsi_status;
188
189 int command_type;
190 u8 lun; /* UPIU LUN id field is only 8-bit wide */
191 bool intr_cmd;
192 bool req_abort_skip;
193 ktime_t issue_time_stamp;
194 u64 issue_time_stamp_local_clock;
195 ktime_t compl_time_stamp;
196 u64 compl_time_stamp_local_clock;
197#ifdef CONFIG_SCSI_UFS_CRYPTO
198 int crypto_key_slot;
199 u64 data_unit_num;
200#endif
201};
202
203/**
204 * struct ufs_query_req - parameters for building a query request
205 * @query_func: UPIU header query function
206 * @upiu_req: the query request data
207 */
208struct ufs_query_req {
209 u8 query_func;
210 struct utp_upiu_query upiu_req;
211};
212
213/**
214 * struct ufs_query_res - UPIU QUERY
215 * @upiu_res: query response data
216 */
217struct ufs_query_res {
218 struct utp_upiu_query upiu_res;
219};
220
221/**
222 * struct ufs_query - holds relevant data structures for query request
223 * @request: request upiu and function
224 * @descriptor: buffer for sending/receiving descriptor
225 * @response: response upiu and response
226 */
227struct ufs_query {
228 struct ufs_query_req request;
229 u8 *descriptor;
230 struct ufs_query_res response;
231};
232
233/**
234 * struct ufs_dev_cmd - all assosiated fields with device management commands
235 * @type: device management command type - Query, NOP OUT
236 * @lock: lock to allow one command at a time
237 * @query: Device management query information
238 * @tag: tag of the reserved request in use
239 */
240struct ufs_dev_cmd {
241 enum dev_cmd_type type;
242 struct mutex lock;
243 struct ufs_query query;
244 u8 tag;
245};
246
247/**
248 * struct ufs_clk_info - UFS clock related info
249 * @list: list headed by hba->clk_list_head
250 * @clk: clock node
251 * @name: clock name
252 * @max_freq: maximum frequency supported by the clock
253 * @min_freq: min frequency that can be used for clock scaling
254 * @curr_freq: indicates the current frequency that it is set to
255 * @keep_link_active: indicates that the clk should not be disabled if
256 * link is active
257 * @enabled: variable to check against multiple enable/disable
258 */
259struct ufs_clk_info {
260 struct list_head list;
261 struct clk *clk;
262 const char *name;
263 u32 max_freq;
264 u32 min_freq;
265 u32 curr_freq;
266 bool keep_link_active;
267 bool enabled;
268};
269
270enum ufs_notify_change_status {
271 PRE_CHANGE,
272 POST_CHANGE,
273};
274
275struct ufs_pa_layer_attr {
276 u32 gear_rx;
277 u32 gear_tx;
278 u32 lane_rx;
279 u32 lane_tx;
280 u32 pwr_rx;
281 u32 pwr_tx;
282 u32 hs_rate;
283};
284
285struct ufs_pwr_mode_info {
286 bool is_valid;
287 struct ufs_pa_layer_attr info;
288};
289
290#define UFS_MAX_LANES 2
291
292/**
293 * struct tx_eqtr_iter - TX Equalization Training iterator
294 * @preshoot_bitmap: PreShoot bitmap
295 * @deemphasis_bitmap: DeEmphasis bitmap
296 * @preshoot: PreShoot value
297 * @deemphasis: DeEmphasis value
298 * @fom: Figure-of-Merit read out from RX_FOM
299 * @is_updated: Flag to indicate if updated since previous iteration
300 */
301struct tx_eqtr_iter {
302 unsigned long preshoot_bitmap;
303 unsigned long deemphasis_bitmap;
304 u8 preshoot;
305 u8 deemphasis;
306 u8 fom[UFS_MAX_LANES];
307 bool is_updated;
308};
309
310/**
311 * struct ufshcd_tx_eq_settings - TX Equalization settings
312 * @preshoot: PreShoot value
313 * @deemphasis: DeEmphasis value
314 * @fom_val: Figure-of-Merit value read out from RX_FOM (Bit[6:0])
315 * @precode_en: Flag to indicate whether need to enable pre-coding
316 */
317struct ufshcd_tx_eq_settings {
318 u8 preshoot;
319 u8 deemphasis;
320 u8 fom_val;
321 bool precode_en;
322};
323
324/**
325 * struct ufshcd_tx_eqtr_data - Data used during TX Equalization Training procedure
326 * @host: Optimal TX EQ settings identified for host TX Lanes during TX EQTR
327 * @device: Optimal TX EQ settings identified for device TX Lanes during TX EQTR
328 * @host_fom: Host TX EQTR FOM record
329 * @device_fom: Device TX EQTR FOM record
330 */
331struct ufshcd_tx_eqtr_data {
332 struct ufshcd_tx_eq_settings host[UFS_MAX_LANES];
333 struct ufshcd_tx_eq_settings device[UFS_MAX_LANES];
334 u8 host_fom[UFS_MAX_LANES][TX_HS_NUM_PRESHOOT][TX_HS_NUM_DEEMPHASIS];
335 u8 device_fom[UFS_MAX_LANES][TX_HS_NUM_PRESHOOT][TX_HS_NUM_DEEMPHASIS];
336};
337
338/**
339 * struct ufshcd_tx_eqtr_record - TX Equalization Training record
340 * @host_fom: Host TX EQTR FOM record
341 * @device_fom: Device TX EQTR FOM record
342 * @last_record_ts: Timestamp of the most recent TX EQTR record
343 * @last_record_index: Index of the most recent TX EQTR record
344 * @saved_adapt_eqtr: Saved Adaptation length setting for TX EQTR
345 */
346struct ufshcd_tx_eqtr_record {
347 u8 host_fom[UFS_MAX_LANES][TX_HS_NUM_PRESHOOT][TX_HS_NUM_DEEMPHASIS];
348 u8 device_fom[UFS_MAX_LANES][TX_HS_NUM_PRESHOOT][TX_HS_NUM_DEEMPHASIS];
349 ktime_t last_record_ts;
350 u16 last_record_index;
351 u16 saved_adapt_eqtr;
352};
353
354/**
355 * struct ufshcd_tx_eq_params - TX Equalization parameters structure
356 * @host: TX EQ settings for host TX Lanes
357 * @device: TX EQ settings for device TX Lanes
358 * @eqtr_record: Pointer to TX EQTR record
359 * @is_valid: True if parameter contains valid TX Equalization settings
360 * @is_applied: True if settings have been applied to UniPro of both sides
361 * @is_trained: True if parameters obtained from TX EQTR procedure
362 * @from_dt: True if settings are from Device Tree
363 */
364struct ufshcd_tx_eq_params {
365 struct ufshcd_tx_eq_settings host[UFS_MAX_LANES];
366 struct ufshcd_tx_eq_settings device[UFS_MAX_LANES];
367 struct ufshcd_tx_eqtr_record *eqtr_record;
368 bool is_valid;
369 bool is_applied;
370 bool is_trained;
371 bool from_dt;
372};
373
374/**
375 * struct ufs_hba_variant_ops - variant specific callbacks
376 * @name: variant name
377 * @init: called when the driver is initialized
378 * @exit: called to cleanup everything done in init
379 * @set_dma_mask: For setting another DMA mask than indicated by the 64AS
380 * capability bit.
381 * @get_ufs_hci_version: called to get UFS HCI version
382 * @clk_scale_notify: notifies that clks are scaled up/down
383 * @setup_clocks: called before touching any of the controller registers
384 * @hce_enable_notify: called before and after HCE enable bit is set to allow
385 * variant specific Uni-Pro initialization.
386 * @link_startup_notify: called before and after Link startup is carried out
387 * to allow variant specific Uni-Pro initialization.
388 * @negotiate_pwr_mode: called to negotiate power mode.
389 * @pwr_change_notify: called before and after a power mode change
390 * is carried out to allow vendor spesific capabilities
391 * to be set.
392 * @setup_xfer_req: called before any transfer request is issued
393 * to set some things
394 * @setup_task_mgmt: called before any task management request is issued
395 * to set some things
396 * @hibern8_notify: called around hibern8 enter/exit
397 * @apply_dev_quirks: called to apply device specific quirks
398 * @fixup_dev_quirks: called to modify device specific quirks
399 * @suspend: called during host controller PM callback
400 * @resume: called during host controller PM callback
401 * @dbg_register_dump: used to dump controller debug information
402 * @phy_initialization: used to initialize phys
403 * @device_reset: called to issue a reset pulse on the UFS device
404 * @config_scaling_param: called to configure clock scaling parameters
405 * @fill_crypto_prdt: initialize crypto-related fields in the PRDT
406 * @event_notify: called to notify important events
407 * @mcq_config_resource: called to configure MCQ platform resources
408 * @get_hba_mac: reports maximum number of outstanding commands supported by
409 * the controller. Should be implemented for UFSHCI 4.0 or later
410 * controllers that are not compliant with the UFSHCI 4.0 specification.
411 * @op_runtime_config: called to config Operation and runtime regs Pointers
412 * @get_outstanding_cqs: called to get outstanding completion queues
413 * @config_esi: called to config Event Specific Interrupt
414 * @config_scsi_dev: called to configure SCSI device parameters
415 * @freq_to_gear_speed: called to map clock frequency to the max supported gear speed
416 * @apply_tx_eqtr_settings: called to apply settings for TX Equalization
417 * Training settings.
418 * @get_rx_fom: called to get Figure of Merit (FOM) value.
419 * @tx_eqtr_notify: called before and after TX Equalization Training procedure
420 * to allow platform vendor specific configs to take place.
421 * @get_hba_nortt: called to get maximum number of outstanding RTTs supported by
422 * the controller.
423 */
424struct ufs_hba_variant_ops {
425 const char *name;
426 int (*init)(struct ufs_hba *);
427 void (*exit)(struct ufs_hba *);
428 u32 (*get_ufs_hci_version)(struct ufs_hba *);
429 int (*set_dma_mask)(struct ufs_hba *);
430 int (*clk_scale_notify)(struct ufs_hba *, bool, unsigned long,
431 enum ufs_notify_change_status);
432 int (*setup_clocks)(struct ufs_hba *, bool,
433 enum ufs_notify_change_status);
434 int (*hce_enable_notify)(struct ufs_hba *,
435 enum ufs_notify_change_status);
436 int (*link_startup_notify)(struct ufs_hba *,
437 enum ufs_notify_change_status);
438 int (*negotiate_pwr_mode)(struct ufs_hba *hba,
439 const struct ufs_pa_layer_attr *desired_pwr_mode,
440 struct ufs_pa_layer_attr *final_params);
441 int (*pwr_change_notify)(struct ufs_hba *hba,
442 enum ufs_notify_change_status status,
443 struct ufs_pa_layer_attr *final_params);
444 void (*setup_xfer_req)(struct ufs_hba *hba, int tag,
445 bool is_scsi_cmd);
446 void (*setup_task_mgmt)(struct ufs_hba *, int, u8);
447 void (*hibern8_notify)(struct ufs_hba *, enum uic_cmd_dme,
448 enum ufs_notify_change_status);
449 int (*apply_dev_quirks)(struct ufs_hba *hba);
450 void (*fixup_dev_quirks)(struct ufs_hba *hba);
451 int (*suspend)(struct ufs_hba *, enum ufs_pm_op,
452 enum ufs_notify_change_status);
453 int (*resume)(struct ufs_hba *, enum ufs_pm_op);
454 void (*dbg_register_dump)(struct ufs_hba *hba);
455 int (*phy_initialization)(struct ufs_hba *);
456 int (*device_reset)(struct ufs_hba *hba);
457 void (*config_scaling_param)(struct ufs_hba *hba,
458 struct devfreq_dev_profile *profile,
459 struct devfreq_simple_ondemand_data *data);
460 int (*fill_crypto_prdt)(struct ufs_hba *hba,
461 const struct bio_crypt_ctx *crypt_ctx,
462 void *prdt, unsigned int num_segments);
463 void (*event_notify)(struct ufs_hba *hba,
464 enum ufs_event_type evt, void *data);
465 int (*mcq_config_resource)(struct ufs_hba *hba);
466 int (*get_hba_mac)(struct ufs_hba *hba);
467 int (*op_runtime_config)(struct ufs_hba *hba);
468 int (*get_outstanding_cqs)(struct ufs_hba *hba,
469 unsigned long *ocqs);
470 int (*config_esi)(struct ufs_hba *hba);
471 void (*config_scsi_dev)(struct scsi_device *sdev);
472 u32 (*freq_to_gear_speed)(struct ufs_hba *hba, unsigned long freq);
473 int (*get_rx_fom)(struct ufs_hba *hba,
474 struct ufs_pa_layer_attr *pwr_mode,
475 struct tx_eqtr_iter *h_iter,
476 struct tx_eqtr_iter *d_iter);
477 int (*apply_tx_eqtr_settings)(struct ufs_hba *hba,
478 struct ufs_pa_layer_attr *pwr_mode,
479 struct tx_eqtr_iter *h_iter,
480 struct tx_eqtr_iter *d_iter);
481 int (*tx_eqtr_notify)(struct ufs_hba *hba,
482 enum ufs_notify_change_status status,
483 struct ufs_pa_layer_attr *pwr_mode);
484 int (*get_hba_nortt)(struct ufs_hba *hba);
485};
486
487/* clock gating state */
488enum clk_gating_state {
489 CLKS_OFF,
490 CLKS_ON,
491 REQ_CLKS_OFF,
492 REQ_CLKS_ON,
493};
494
495/**
496 * struct ufs_clk_gating - UFS clock gating related info
497 * @gate_work: worker to turn off clocks after some delay as specified in
498 * delay_ms
499 * @ungate_work: worker to turn on clocks that will be used in case of
500 * interrupt context
501 * @clk_gating_workq: workqueue for clock gating work.
502 * @lock: serialize access to some struct ufs_clk_gating members. An outer lock
503 * relative to the host lock
504 * @state: the current clocks state
505 * @delay_ms: gating delay in ms
506 * @is_suspended: clk gating is suspended when set to 1 which can be used
507 * during suspend/resume
508 * @delay_attr: sysfs attribute to control delay_attr
509 * @enable_attr: sysfs attribute to enable/disable clock gating
510 * @is_enabled: Indicates the current status of clock gating
511 * @is_initialized: Indicates whether clock gating is initialized or not
512 * @active_reqs: number of requests that are pending and should be waited for
513 * completion before gating clocks.
514 */
515struct ufs_clk_gating {
516 struct delayed_work gate_work;
517 struct work_struct ungate_work;
518 struct workqueue_struct *clk_gating_workq;
519
520 spinlock_t lock;
521
522 enum clk_gating_state state;
523 unsigned long delay_ms;
524 bool is_suspended;
525 struct device_attribute delay_attr;
526 struct device_attribute enable_attr;
527 bool is_enabled;
528 bool is_initialized;
529 int active_reqs;
530};
531
532/**
533 * struct ufs_clk_scaling - UFS clock scaling related data
534 * @workq: workqueue to schedule devfreq suspend/resume work
535 * @suspend_work: worker to suspend devfreq
536 * @resume_work: worker to resume devfreq
537 * @lock: serialize access to some struct ufs_clk_scaling members
538 * @active_reqs: number of requests that are pending. If this is zero when
539 * devfreq ->target() function is called then schedule "suspend_work" to
540 * suspend devfreq.
541 * @tot_busy_t: Total busy time in current polling window
542 * @window_start_t: Start time (in jiffies) of the current polling window
543 * @busy_start_t: Start time of current busy period
544 * @enable_attr: sysfs attribute to enable/disable clock scaling
545 * @saved_pwr_info: UFS power mode may also be changed during scaling and this
546 * one keeps track of previous power mode.
547 * @target_freq: frequency requested by devfreq framework
548 * @min_gear: lowest HS gear to scale down to
549 * @wb_gear: enable Write Booster when HS gear scales above or equal to it, else
550 * disable Write Booster
551 * @is_enabled: tracks if scaling is currently enabled or not, controlled by
552 * clkscale_enable sysfs node
553 * @is_allowed: tracks if scaling is currently allowed or not, used to block
554 * clock scaling which is not invoked from devfreq governor
555 * @is_initialized: Indicates whether clock scaling is initialized or not
556 * @is_busy_started: tracks if busy period has started or not
557 * @is_suspended: tracks if devfreq is suspended or not
558 * @suspend_on_no_request: suspend clock scaling only when no request
559 */
560struct ufs_clk_scaling {
561 struct workqueue_struct *workq;
562 struct work_struct suspend_work;
563 struct work_struct resume_work;
564
565 spinlock_t lock;
566
567 int active_reqs;
568 unsigned long tot_busy_t;
569 ktime_t window_start_t;
570 ktime_t busy_start_t;
571 struct device_attribute enable_attr;
572 struct ufs_pa_layer_attr saved_pwr_info;
573 unsigned long target_freq;
574 u32 min_gear;
575 u32 wb_gear;
576 bool is_enabled;
577 bool is_allowed;
578 bool is_initialized;
579 bool is_busy_started;
580 bool is_suspended;
581 bool suspend_on_no_request;
582};
583
584#define UFS_EVENT_HIST_LENGTH 8
585/**
586 * struct ufs_event_hist - keeps history of errors
587 * @pos: index to indicate cyclic buffer position
588 * @val: cyclic buffer for registers value
589 * @tstamp: cyclic buffer for time stamp
590 * @cnt: error counter
591 */
592struct ufs_event_hist {
593 int pos;
594 u32 val[UFS_EVENT_HIST_LENGTH];
595 u64 tstamp[UFS_EVENT_HIST_LENGTH];
596 unsigned long long cnt;
597};
598
599/**
600 * struct ufs_stats - keeps usage/err statistics
601 * @hibern8_exit_cnt: Counter to keep track of number of exits,
602 * reset this after link-startup.
603 * @last_hibern8_exit_tstamp: Set time after the hibern8 exit.
604 * Clear after the first successful command completion.
605 * @event: array with event history.
606 */
607struct ufs_stats {
608 u32 hibern8_exit_cnt;
609 u64 last_hibern8_exit_tstamp;
610 struct ufs_event_hist event[UFS_EVT_CNT];
611};
612
613/**
614 * enum ufshcd_state - UFS host controller state
615 * @UFSHCD_STATE_RESET: Link is not operational. Postpone SCSI command
616 * processing.
617 * @UFSHCD_STATE_OPERATIONAL: The host controller is operational and can process
618 * SCSI commands.
619 * @UFSHCD_STATE_EH_SCHEDULED_NON_FATAL: The error handler has been scheduled.
620 * SCSI commands may be submitted to the controller.
621 * @UFSHCD_STATE_EH_SCHEDULED_FATAL: The error handler has been scheduled. Fail
622 * newly submitted SCSI commands with error code DID_BAD_TARGET.
623 * @UFSHCD_STATE_ERROR: An unrecoverable error occurred, e.g. link recovery
624 * failed. Fail all SCSI commands with error code DID_ERROR.
625 */
626enum ufshcd_state {
627 UFSHCD_STATE_RESET,
628 UFSHCD_STATE_OPERATIONAL,
629 UFSHCD_STATE_EH_SCHEDULED_NON_FATAL,
630 UFSHCD_STATE_EH_SCHEDULED_FATAL,
631 UFSHCD_STATE_ERROR,
632};
633
634/**
635 * enum ufshcd_pmc_policy - Power Mode change policy
636 * @UFSHCD_PMC_POLICY_DONT_FORCE: Do not force a Power Mode change.
637 * @UFSHCD_PMC_POLICY_FORCE: Force a Power Mode change even if current Power
638 * Mode is same as target Power Mode.
639 */
640enum ufshcd_pmc_policy {
641 UFSHCD_PMC_POLICY_DONT_FORCE,
642 UFSHCD_PMC_POLICY_FORCE,
643};
644
645enum ufshcd_quirks {
646 /* Interrupt aggregation support is broken */
647 UFSHCD_QUIRK_BROKEN_INTR_AGGR = 1 << 0,
648
649 /*
650 * delay before each dme command is required as the unipro
651 * layer has shown instabilities
652 */
653 UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS = 1 << 1,
654
655 /*
656 * If UFS host controller is having issue in processing LCC (Line
657 * Control Command) coming from device then enable this quirk.
658 * When this quirk is enabled, host controller driver should disable
659 * the LCC transmission on UFS device (by clearing TX_LCC_ENABLE
660 * attribute of device to 0).
661 */
662 UFSHCD_QUIRK_BROKEN_LCC = 1 << 2,
663
664 /*
665 * The attribute PA_RXHSUNTERMCAP specifies whether or not the
666 * inbound Link supports unterminated line in HS mode. Setting this
667 * attribute to 1 fixes moving to HS gear.
668 */
669 UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP = 1 << 3,
670
671 /*
672 * This quirk needs to be enabled if the host controller only allows
673 * accessing the peer dme attributes in AUTO mode (FAST AUTO or
674 * SLOW AUTO).
675 */
676 UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE = 1 << 4,
677
678 /*
679 * This quirk needs to be enabled if the host controller doesn't
680 * advertise the correct version in UFS_VER register. If this quirk
681 * is enabled, standard UFS host driver will call the vendor specific
682 * ops (get_ufs_hci_version) to get the correct version.
683 */
684 UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION = 1 << 5,
685
686 /*
687 * Clear handling for transfer/task request list is just opposite.
688 */
689 UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR = 1 << 6,
690
691 /*
692 * This quirk needs to be enabled if host controller doesn't allow
693 * that the interrupt aggregation timer and counter are reset by s/w.
694 */
695 UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR = 1 << 7,
696
697 /*
698 * This quirks needs to be enabled if host controller cannot be
699 * enabled via HCE register.
700 */
701 UFSHCI_QUIRK_BROKEN_HCE = 1 << 8,
702
703 /*
704 * This quirk needs to be enabled if the host controller regards
705 * resolution of the values of PRDTO and PRDTL in UTRD as byte.
706 */
707 UFSHCD_QUIRK_PRDT_BYTE_GRAN = 1 << 9,
708
709 /*
710 * This quirk needs to be enabled if the host controller reports
711 * OCS FATAL ERROR with device error through sense data
712 */
713 UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR = 1 << 10,
714
715 /*
716 * This quirk needs to be enabled if the host controller has
717 * auto-hibernate capability but it doesn't work.
718 */
719 UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8 = 1 << 11,
720
721 /*
722 * This quirk needs to disable manual flush for write booster
723 */
724 UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL = 1 << 12,
725
726 /*
727 * This quirk needs to disable unipro timeout values
728 * before power mode change
729 */
730 UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING = 1 << 13,
731
732 /*
733 * This quirk needs to be enabled if the host controller does not
734 * support UIC command
735 */
736 UFSHCD_QUIRK_BROKEN_UIC_CMD = 1 << 15,
737
738 /*
739 * This quirk needs to be enabled if the host controller cannot
740 * support physical host configuration.
741 */
742 UFSHCD_QUIRK_SKIP_PH_CONFIGURATION = 1 << 16,
743
744 /*
745 * This quirk needs to be enabled if the host controller has
746 * auto-hibernate capability but it's FASTAUTO only.
747 */
748 UFSHCD_QUIRK_HIBERN_FASTAUTO = 1 << 18,
749
750 /*
751 * This quirk needs to be enabled if the host controller needs
752 * to reinit the device after switching to maximum gear.
753 */
754 UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH = 1 << 19,
755
756 /*
757 * Some host raises interrupt (per queue) in addition to
758 * CQES (traditional) when ESI is disabled.
759 * Enable this quirk will disable CQES and use per queue interrupt.
760 */
761 UFSHCD_QUIRK_MCQ_BROKEN_INTR = 1 << 20,
762
763 /*
764 * Some host does not implement SQ Run Time Command (SQRTC) register
765 * thus need this quirk to skip related flow.
766 */
767 UFSHCD_QUIRK_MCQ_BROKEN_RTC = 1 << 21,
768
769 /*
770 * This quirk needs to be enabled if the host controller supports inline
771 * encryption but it needs to initialize the crypto capabilities in a
772 * nonstandard way and/or needs to override blk_crypto_ll_ops. If
773 * enabled, the standard code won't initialize the blk_crypto_profile;
774 * ufs_hba_variant_ops::init() must do it instead.
775 */
776 UFSHCD_QUIRK_CUSTOM_CRYPTO_PROFILE = 1 << 22,
777
778 /*
779 * This quirk needs to be enabled if the host controller supports inline
780 * encryption but does not support the CRYPTO_GENERAL_ENABLE bit, i.e.
781 * host controller initialization fails if that bit is set.
782 */
783 UFSHCD_QUIRK_BROKEN_CRYPTO_ENABLE = 1 << 23,
784
785 /*
786 * This quirk needs to be enabled if the host controller driver copies
787 * cryptographic keys into the PRDT in order to send them to hardware,
788 * and therefore the PRDT should be zeroized after each request (as per
789 * the standard best practice for managing keys).
790 */
791 UFSHCD_QUIRK_KEYS_IN_PRDT = 1 << 24,
792
793 /*
794 * This quirk indicates that the controller reports the value 1 (not
795 * supported) in the Legacy Single DoorBell Support (LSDBS) bit of the
796 * Controller Capabilities register although it supports the legacy
797 * single doorbell mode.
798 */
799 UFSHCD_QUIRK_BROKEN_LSDBS_CAP = 1 << 25,
800
801 /*
802 * This quirk indicates that DME_LINKSTARTUP should not be issued a 2nd
803 * time (refer link_startup_again) after the 1st time was successful,
804 * because it causes link startup to become unreliable.
805 */
806 UFSHCD_QUIRK_PERFORM_LINK_STARTUP_ONCE = 1 << 26,
807
808 /*
809 * On some platforms, the VCC regulator has a slow ramp-up time. Add a
810 * delay after enabling VCC to ensure it's stable.
811 */
812 UFSHCD_QUIRK_VCC_ON_DELAY = 1 << 27,
813
814 /*
815 * This quirk indicates that Host supports TX Equalization Training
816 * (EQTR) using Adapt L0L1L2L3 length which is larger than what is
817 * allowed by M-PHY spec ver 6.0.
818 */
819 UFSHCD_QUIRK_EXTENDED_TX_EQTR_ADAPT_LENGTH_L0L1L2L3 = 1 << 28,
820};
821
822enum ufshcd_caps {
823 /* Allow dynamic clk gating */
824 UFSHCD_CAP_CLK_GATING = 1 << 0,
825
826 /* Allow hiberb8 with clk gating */
827 UFSHCD_CAP_HIBERN8_WITH_CLK_GATING = 1 << 1,
828
829 /* Allow dynamic clk scaling */
830 UFSHCD_CAP_CLK_SCALING = 1 << 2,
831
832 /* Allow auto bkops to enabled during runtime suspend */
833 UFSHCD_CAP_AUTO_BKOPS_SUSPEND = 1 << 3,
834
835 /*
836 * This capability allows host controller driver to use the UFS HCI's
837 * interrupt aggregation capability.
838 * CAUTION: Enabling this might reduce overall UFS throughput.
839 */
840 UFSHCD_CAP_INTR_AGGR = 1 << 4,
841
842 /*
843 * This capability allows the device auto-bkops to be always enabled
844 * except during suspend (both runtime and suspend).
845 * Enabling this capability means that device will always be allowed
846 * to do background operation when it's active but it might degrade
847 * the performance of ongoing read/write operations.
848 */
849 UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND = 1 << 5,
850
851 /*
852 * This capability allows host controller driver to automatically
853 * enable runtime power management by itself instead of waiting
854 * for userspace to control the power management.
855 */
856 UFSHCD_CAP_RPM_AUTOSUSPEND = 1 << 6,
857
858 /*
859 * This capability allows the host controller driver to turn-on
860 * WriteBooster, if the underlying device supports it and is
861 * provisioned to be used. This would increase the write performance.
862 */
863 UFSHCD_CAP_WB_EN = 1 << 7,
864
865 /*
866 * This capability allows the host controller driver to use the
867 * inline crypto engine, if it is present
868 */
869 UFSHCD_CAP_CRYPTO = 1 << 8,
870
871 /*
872 * This capability allows the controller regulators to be put into
873 * lpm mode aggressively during clock gating.
874 * This would increase power savings.
875 */
876 UFSHCD_CAP_AGGR_POWER_COLLAPSE = 1 << 9,
877
878 /*
879 * This capability allows the host controller driver to use DeepSleep,
880 * if it is supported by the UFS device. The host controller driver must
881 * support device hardware reset via the hba->device_reset() callback,
882 * in order to exit DeepSleep state.
883 */
884 UFSHCD_CAP_DEEPSLEEP = 1 << 10,
885
886 /*
887 * This capability allows the host controller driver to use temperature
888 * notification if it is supported by the UFS device.
889 */
890 UFSHCD_CAP_TEMP_NOTIF = 1 << 11,
891
892 /*
893 * Enable WriteBooster when scaling up the clock and disable
894 * WriteBooster when scaling the clock down.
895 */
896 UFSHCD_CAP_WB_WITH_CLK_SCALING = 1 << 12,
897
898 /*
899 * This capability allows the host controller driver to apply TX
900 * Equalization settings discovered from UFS attributes, variant
901 * specific operations and TX Equaliztion Training procedure.
902 */
903 UFSHCD_CAP_TX_EQUALIZATION = 1 << 13,
904};
905
906struct ufs_hba_variant_params {
907 struct devfreq_dev_profile devfreq_profile;
908 struct devfreq_simple_ondemand_data ondemand_data;
909 u16 hba_enable_delay_us;
910 u32 wb_flush_threshold;
911};
912
913struct ufs_hba_monitor {
914 unsigned long chunk_size;
915
916 unsigned long nr_sec_rw[2];
917 ktime_t total_busy[2];
918
919 unsigned long nr_req[2];
920 /* latencies*/
921 ktime_t lat_sum[2];
922 ktime_t lat_max[2];
923 ktime_t lat_min[2];
924
925 u32 nr_queued[2];
926 ktime_t busy_start_ts[2];
927
928 ktime_t enabled_ts;
929 bool enabled;
930};
931
932/**
933 * struct ufshcd_mcq_opr_info_t - Operation and Runtime registers
934 *
935 * @offset: Doorbell Address Offset
936 * @stride: Steps proportional to queue [0...31]
937 * @base: base address
938 */
939struct ufshcd_mcq_opr_info_t {
940 unsigned long offset;
941 unsigned long stride;
942 void __iomem *base;
943};
944
945enum ufshcd_mcq_opr {
946 OPR_SQD,
947 OPR_SQIS,
948 OPR_CQD,
949 OPR_CQIS,
950 OPR_MAX,
951};
952
953/**
954 * struct ufs_hba - per adapter private structure
955 * @mmio_base: UFSHCI base register address
956 * @ucdl_base_addr: UFS Command Descriptor base address
957 * @utrdl_base_addr: UTP Transfer Request Descriptor base address
958 * @utmrdl_base_addr: UTP Task Management Descriptor base address
959 * @devman_ucd_base_addr: UFS Command Descriptor base address for the reserved
960 * device management tag (has a larger response area)
961 * @ucdl_dma_addr: UFS Command Descriptor DMA address
962 * @utrdl_dma_addr: UTRDL DMA address
963 * @utmrdl_dma_addr: UTMRDL DMA address
964 * @devman_ucd_dma_addr: UFS Command Descriptor DMA address for the reserved
965 * device management tag
966 * @host: Scsi_Host instance of the driver
967 * @dev: device handle
968 * @ufs_device_wlun: WLUN that controls the entire UFS device.
969 * @ufs_rpmb_wlun: RPMB WLUN SCSI device
970 * @hwmon_device: device instance registered with the hwmon core.
971 * @curr_dev_pwr_mode: active UFS device power mode.
972 * @uic_link_state: active state of the link to the UFS device.
973 * @rpm_lvl: desired UFS power management level during runtime PM.
974 * @spm_lvl: desired UFS power management level during system PM.
975 * @pm_lvl_min: minimum supported power management level.
976 * @pm_op_in_progress: whether or not a PM operation is in progress.
977 * @ahit: value of Auto-Hibernate Idle Timer register.
978 * @outstanding_tasks: Bits representing outstanding task requests
979 * @outstanding_lock: Protects @outstanding_reqs.
980 * @outstanding_reqs: Bits representing outstanding transfer requests
981 * @capabilities: UFS Controller Capabilities
982 * @mcq_capabilities: UFS Multi Circular Queue capabilities
983 * @nutrs: Transfer Request Queue depth supported by controller
984 * @nortt: Max outstanding RTTs supported by controller
985 * @nutmrs: Task Management Queue depth supported by controller
986 * @ufs_version: UFS Version to which controller complies
987 * @vops: pointer to variant specific operations
988 * @vps: pointer to variant specific parameters
989 * @priv: pointer to variant specific private data
990 * @sg_entry_size: size of struct ufshcd_sg_entry (may include variant fields)
991 * @irq: Irq number of the controller
992 * @is_irq_enabled: whether or not the UFS controller interrupt is enabled.
993 * @dev_ref_clk_freq: reference clock frequency
994 * @quirks: bitmask with information about deviations from the UFSHCI standard.
995 * @dev_quirks: bitmask with information about deviations from the UFS standard.
996 * @tmf_tag_set: TMF tag set.
997 * @tmf_queue: Used to allocate TMF tags.
998 * @tmf_rqs: array with pointers to TMF requests while these are in progress.
999 * @active_uic_cmd: pointer to active UIC command.
1000 * @uic_cmd_mutex: mutex used for serializing UIC command processing.
1001 * @uic_async_done: completion used to wait for power mode or hibernation state
1002 * changes.
1003 * @ufshcd_state: UFSHCD state
1004 * @eh_flags: Error handling flags
1005 * @intr_mask: Interrupt Mask Bits
1006 * @ee_ctrl_mask: Exception event control mask
1007 * @ee_drv_mask: Exception event mask for driver
1008 * @ee_usr_mask: Exception event mask for user (set via debugfs)
1009 * @ee_ctrl_mutex: Used to serialize exception event information.
1010 * @is_powered: flag to check if HBA is powered
1011 * @shutting_down: flag to check if shutdown has been invoked
1012 * @host_sem: semaphore used to serialize concurrent contexts
1013 * @eh_wq: Workqueue that eh_work works on
1014 * @eh_work: Worker to handle UFS errors that require s/w attention
1015 * @eeh_work: Worker to handle exception events
1016 * @errors: HBA errors
1017 * @uic_error: UFS interconnect layer error status
1018 * @saved_err: sticky error mask
1019 * @saved_uic_err: sticky UIC error mask
1020 * @ufs_stats: various error counters
1021 * @force_reset: flag to force eh_work perform a full reset
1022 * @silence_err_logs: flag to silence error logs
1023 * @dev_cmd: ufs device management command information
1024 * @last_dme_cmd_tstamp: time stamp of the last completed DME command
1025 * @nop_out_timeout: NOP OUT timeout value
1026 * @dev_info: information about the UFS device
1027 * @auto_bkops_enabled: to track whether bkops is enabled in device
1028 * @vreg_info: UFS device voltage regulator information
1029 * @clk_list_head: UFS host controller clocks list node head
1030 * @use_pm_opp: Indicates whether OPP based scaling is used or not
1031 * @req_abort_count: number of times ufshcd_abort() has been called
1032 * @lanes_per_direction: number of lanes per data direction between the UFS
1033 * controller and the UFS device.
1034 * @pwr_info: holds current power mode
1035 * @max_pwr_info: keeps the device max valid pwm
1036 * @clk_gating: information related to clock gating
1037 * @caps: bitmask with information about UFS controller capabilities
1038 * @devfreq: frequency scaling information owned by the devfreq core
1039 * @clk_scaling: frequency scaling information owned by the UFS driver
1040 * @is_sys_suspended: UFS device has been suspended because of system suspend
1041 * @urgent_bkops_lvl: keeps track of urgent bkops level for device
1042 * @is_urgent_bkops_lvl_checked: keeps track if the urgent bkops level for
1043 * device is known or not.
1044 * @wb_mutex: used to serialize devfreq and sysfs write booster toggling
1045 * @clk_scaling_lock: used to serialize device commands and clock scaling
1046 * @bsg_dev: struct device associated with the BSG queue
1047 * @bsg_queue: BSG queue associated with the UFS controller
1048 * @rpm_dev_flush_recheck_work: used to suspend from RPM (runtime power
1049 * management) after the UFS device has finished a WriteBooster buffer
1050 * flush or auto BKOP.
1051 * @monitor: statistics about UFS commands
1052 * @crypto_capabilities: Content of crypto capabilities register (0x100)
1053 * @crypto_cap_array: Array of crypto capabilities
1054 * @crypto_cfg_register: Start of the crypto cfg array
1055 * @crypto_profile: the crypto profile of this hba (if applicable)
1056 * @debugfs_root: UFS controller debugfs root directory
1057 * @debugfs_ee_work: used to restore ee_ctrl_mask after a delay
1058 * @debugfs_ee_rate_limit_ms: user configurable delay after which to restore
1059 * ee_ctrl_mask
1060 * @trigger_eh_attr: fault attributes for the fault injection trigger EH
1061 * @timeout_attr: fault attributes for the timeout fault injection trigger
1062 * @luns_avail: number of regular and well known LUNs supported by the UFS
1063 * device
1064 * @nr_hw_queues: number of hardware queues configured
1065 * @nr_queues: number of Queues of different queue types
1066 * @complete_put: whether or not to call ufshcd_rpm_put() from inside
1067 * ufshcd_resume_complete()
1068 * @scsi_host_added: indicates that scsi_add_host() has been called
1069 * @mcq_sup: is mcq supported by UFSHC
1070 * @lsdb_sup: LSDBS capability
1071 * @mcq_enabled: is mcq ready to accept requests
1072 * @mcq_esi_enabled: is mcq ESI configured
1073 * @mcq_base: Multi circular queue registers base address
1074 * @uhq: array of supported hardware queues
1075 * @mcq_opr: MCQ operation and runtime registers
1076 * @ufs_rtc_update_work: A work for UFS RTC periodic update
1077 * @pm_qos_req: PM QoS request handle
1078 * @pm_qos_enabled: flag to check if pm qos is enabled
1079 * @pm_qos_mutex: synchronizes PM QoS request and status updates
1080 * @critical_health_count: count of critical health exceptions
1081 * @dev_lvl_exception_count: count of device level exceptions since last reset
1082 * @dev_lvl_exception_id: vendor specific information about the device level exception event.
1083 * @dme_qos_notification: Bitfield of pending DME Quality of Service (QoS)
1084 * events. Bits[3:1] reflect the corresponding bits of UIC DME Error Code
1085 * field within the Host Controller's UECDME register. Bit[0] is a flag
1086 * indicating that the DME QoS Monitor has been reset by the host.
1087 * @dme_qos_sysfs_handle: handle for 'dme_qos_notification' sysfs entry
1088 * @vcc_off_delay_us: length of delay after VCC is powered off
1089 * @rpmbs: list of OP-TEE RPMB devices (one per RPMB region)
1090 * @host_preshoot_cap: a bitfield to indicate supported PreShoot dBs of host's TX lanes, cache of
1091 * host M-PHY TX_HS_PreShoot_Setting_Capability Attribute (ID 0x15)
1092 * @host_deemphasis_cap: a bitfield to indicate supported DeEmphasis dBs of host's TX lanes, cache
1093 * of host M-PHY TX_HS_DeEmphasis_Setting_Capability Attribute (ID 0x12)
1094 * @device_preshoot_cap: a bitfield to indicate supported PreShoot dBs of device's TX lanes, cache
1095 * of device M-PHY TX_HS_PreShoot_Setting_Capability Attribute (ID 0x15)
1096 * @device_deemphasis_cap: a bitfield to indicate supported DeEmphasis dBs of device's TX lanes,
1097 * cache of device M-PHY TX_HS_DeEmphasis_Setting_Capability Attribute (ID 0x12)
1098 * @tx_eq_params: TX Equalization settings
1099 */
1100struct ufs_hba {
1101 void __iomem *mmio_base;
1102
1103 /* Virtual memory reference */
1104 struct utp_transfer_cmd_desc *ucdl_base_addr;
1105 struct utp_transfer_req_desc *utrdl_base_addr;
1106 struct utp_task_req_desc *utmrdl_base_addr;
1107 struct utp_devman_cmd_desc *devman_ucd_base_addr;
1108
1109 /* DMA memory reference */
1110 dma_addr_t ucdl_dma_addr;
1111 dma_addr_t utrdl_dma_addr;
1112 dma_addr_t utmrdl_dma_addr;
1113 dma_addr_t devman_ucd_dma_addr;
1114
1115 struct Scsi_Host *host;
1116 struct device *dev;
1117 struct scsi_device *ufs_device_wlun;
1118 struct scsi_device *ufs_rpmb_wlun;
1119
1120#ifdef CONFIG_SCSI_UFS_HWMON
1121 struct device *hwmon_device;
1122#endif
1123
1124 enum ufs_dev_pwr_mode curr_dev_pwr_mode;
1125 enum uic_link_state uic_link_state;
1126 /* Desired UFS power management level during runtime PM */
1127 enum ufs_pm_level rpm_lvl;
1128 /* Desired UFS power management level during system PM */
1129 enum ufs_pm_level spm_lvl;
1130 enum ufs_pm_level pm_lvl_min;
1131 int pm_op_in_progress;
1132
1133 /* Auto-Hibernate Idle Timer register value */
1134 u32 ahit;
1135
1136 unsigned long outstanding_tasks;
1137 spinlock_t outstanding_lock;
1138 unsigned long outstanding_reqs;
1139
1140 u32 capabilities;
1141 int nutrs;
1142 int nortt;
1143 u32 mcq_capabilities;
1144 int nutmrs;
1145 u32 ufs_version;
1146 const struct ufs_hba_variant_ops *vops;
1147 struct ufs_hba_variant_params *vps;
1148 void *priv;
1149#ifdef CONFIG_SCSI_UFS_VARIABLE_SG_ENTRY_SIZE
1150 size_t sg_entry_size;
1151#endif
1152 unsigned int irq;
1153 bool is_irq_enabled;
1154 enum ufs_ref_clk_freq dev_ref_clk_freq;
1155
1156 unsigned int quirks; /* Deviations from standard UFSHCI spec. */
1157
1158 /* Device deviations from standard UFS device spec. */
1159 unsigned int dev_quirks;
1160
1161 struct blk_mq_tag_set tmf_tag_set;
1162 struct request_queue *tmf_queue;
1163 struct request **tmf_rqs;
1164
1165 struct uic_command *active_uic_cmd;
1166 struct mutex uic_cmd_mutex;
1167 struct completion *uic_async_done;
1168
1169 enum ufshcd_state ufshcd_state;
1170 u32 eh_flags;
1171 u32 intr_mask;
1172 u16 ee_ctrl_mask;
1173 u16 ee_drv_mask;
1174 u16 ee_usr_mask;
1175 struct mutex ee_ctrl_mutex;
1176 bool is_powered;
1177 bool shutting_down;
1178 struct semaphore host_sem;
1179
1180 /* Work Queues */
1181 struct workqueue_struct *eh_wq;
1182 struct work_struct eh_work;
1183 struct work_struct eeh_work;
1184
1185 /* HBA Errors */
1186 u32 errors;
1187 u32 uic_error;
1188 u32 saved_err;
1189 u32 saved_uic_err;
1190 struct ufs_stats ufs_stats;
1191 bool force_reset;
1192 bool silence_err_logs;
1193
1194 /* Device management request data */
1195 struct ufs_dev_cmd dev_cmd;
1196 ktime_t last_dme_cmd_tstamp;
1197 int nop_out_timeout;
1198
1199 /* Keeps information of the UFS device connected to this host */
1200 struct ufs_dev_info dev_info;
1201 bool auto_bkops_enabled;
1202 struct ufs_vreg_info vreg_info;
1203 struct list_head clk_list_head;
1204 bool use_pm_opp;
1205
1206 /* Number of requests aborts */
1207 int req_abort_count;
1208
1209 /* Number of lanes available (1 or 2) for Rx/Tx */
1210 u32 lanes_per_direction;
1211 struct ufs_pa_layer_attr pwr_info;
1212 struct ufs_pwr_mode_info max_pwr_info;
1213
1214 struct ufs_clk_gating clk_gating;
1215 /* Control to enable/disable host capabilities */
1216 u32 caps;
1217
1218 struct devfreq *devfreq;
1219 struct ufs_clk_scaling clk_scaling;
1220 bool is_sys_suspended;
1221
1222 enum bkops_status urgent_bkops_lvl;
1223 bool is_urgent_bkops_lvl_checked;
1224
1225 struct mutex wb_mutex;
1226 struct rw_semaphore clk_scaling_lock;
1227
1228 struct device bsg_dev;
1229 struct request_queue *bsg_queue;
1230 struct delayed_work rpm_dev_flush_recheck_work;
1231
1232 struct ufs_hba_monitor monitor;
1233
1234#ifdef CONFIG_SCSI_UFS_CRYPTO
1235 union ufs_crypto_capabilities crypto_capabilities;
1236 union ufs_crypto_cap_entry *crypto_cap_array;
1237 u32 crypto_cfg_register;
1238 struct blk_crypto_profile crypto_profile;
1239#endif
1240#ifdef CONFIG_DEBUG_FS
1241 struct dentry *debugfs_root;
1242 struct delayed_work debugfs_ee_work;
1243 u32 debugfs_ee_rate_limit_ms;
1244#endif
1245#ifdef CONFIG_SCSI_UFS_FAULT_INJECTION
1246 struct fault_attr trigger_eh_attr;
1247 struct fault_attr timeout_attr;
1248#endif
1249 u32 luns_avail;
1250 unsigned int nr_hw_queues;
1251 unsigned int nr_queues[HCTX_MAX_TYPES];
1252 bool complete_put;
1253 bool scsi_host_added;
1254 bool mcq_sup;
1255 bool lsdb_sup;
1256 bool mcq_enabled;
1257 bool mcq_esi_enabled;
1258 void __iomem *mcq_base;
1259 struct ufs_hw_queue *uhq;
1260 struct ufshcd_mcq_opr_info_t mcq_opr[OPR_MAX];
1261
1262 struct delayed_work ufs_rtc_update_work;
1263 struct pm_qos_request pm_qos_req;
1264 bool pm_qos_enabled;
1265 /* synchronizes PM QoS request and status updates */
1266 struct mutex pm_qos_mutex;
1267
1268 int critical_health_count;
1269 atomic_t dev_lvl_exception_count;
1270 u64 dev_lvl_exception_id;
1271
1272 atomic_t dme_qos_notification;
1273 struct kernfs_node *dme_qos_sysfs_handle;
1274
1275 u32 vcc_off_delay_us;
1276 struct list_head rpmbs;
1277
1278 u8 host_preshoot_cap;
1279 u8 host_deemphasis_cap;
1280 u8 device_preshoot_cap;
1281 u8 device_deemphasis_cap;
1282 struct ufshcd_tx_eq_params tx_eq_params[UFS_HS_GEAR_MAX];
1283};
1284
1285/**
1286 * struct ufs_hw_queue - per hardware queue structure
1287 * @mcq_sq_head: base address of submission queue head pointer
1288 * @mcq_sq_tail: base address of submission queue tail pointer
1289 * @mcq_cq_head: base address of completion queue head pointer
1290 * @mcq_cq_tail: base address of completion queue tail pointer
1291 * @sqe_base_addr: submission queue entry base address
1292 * @sqe_dma_addr: submission queue dma address
1293 * @cqe_base_addr: completion queue base address
1294 * @cqe_dma_addr: completion queue dma address
1295 * @max_entries: max number of slots in this hardware queue
1296 * @id: hardware queue ID
1297 * @sq_tail_slot: current slot to which SQ tail pointer is pointing
1298 * @sq_lock: serialize submission queue access
1299 * @cq_tail_slot: current slot to which CQ tail pointer is pointing
1300 * @cq_head_slot: current slot to which CQ head pointer is pointing
1301 * @cq_lock: Synchronize between multiple polling instances
1302 * @sq_mutex: prevent submission queue concurrent access
1303 */
1304struct ufs_hw_queue {
1305 void __iomem *mcq_sq_head;
1306 void __iomem *mcq_sq_tail;
1307 void __iomem *mcq_cq_head;
1308 void __iomem *mcq_cq_tail;
1309
1310 struct utp_transfer_req_desc *sqe_base_addr;
1311 dma_addr_t sqe_dma_addr;
1312 struct cq_entry *cqe_base_addr;
1313 dma_addr_t cqe_dma_addr;
1314 u32 max_entries;
1315 u32 id;
1316 u32 sq_tail_slot;
1317 spinlock_t sq_lock;
1318 u32 cq_tail_slot;
1319 u32 cq_head_slot;
1320 spinlock_t cq_lock;
1321 /* prevent concurrent access to submission queue */
1322 struct mutex sq_mutex;
1323};
1324
1325#define MCQ_QCFG_SIZE 0x40
1326
1327static inline unsigned int ufshcd_mcq_opr_offset(struct ufs_hba *hba,
1328 enum ufshcd_mcq_opr opr, int idx)
1329{
1330 return hba->mcq_opr[opr].offset + hba->mcq_opr[opr].stride * idx;
1331}
1332
1333static inline unsigned int ufshcd_mcq_cfg_offset(unsigned int reg, int idx)
1334{
1335 return reg + MCQ_QCFG_SIZE * idx;
1336}
1337
1338#ifdef CONFIG_SCSI_UFS_VARIABLE_SG_ENTRY_SIZE
1339static inline size_t ufshcd_sg_entry_size(const struct ufs_hba *hba)
1340{
1341 return hba->sg_entry_size;
1342}
1343
1344static inline void ufshcd_set_sg_entry_size(struct ufs_hba *hba, size_t sg_entry_size)
1345{
1346 WARN_ON_ONCE(sg_entry_size < sizeof(struct ufshcd_sg_entry));
1347 hba->sg_entry_size = sg_entry_size;
1348}
1349#else
1350static inline size_t ufshcd_sg_entry_size(const struct ufs_hba *hba)
1351{
1352 return sizeof(struct ufshcd_sg_entry);
1353}
1354
1355#define ufshcd_set_sg_entry_size(hba, sg_entry_size) \
1356 ({ (void)(hba); BUILD_BUG_ON(sg_entry_size != sizeof(struct ufshcd_sg_entry)); })
1357#endif
1358
1359#ifdef CONFIG_SCSI_UFS_CRYPTO
1360static inline struct ufs_hba *
1361ufs_hba_from_crypto_profile(struct blk_crypto_profile *profile)
1362{
1363 return container_of(profile, struct ufs_hba, crypto_profile);
1364}
1365#endif
1366
1367static inline size_t ufshcd_get_ucd_size(const struct ufs_hba *hba)
1368{
1369 return sizeof(struct utp_transfer_cmd_desc) + SG_ALL * ufshcd_sg_entry_size(hba);
1370}
1371
1372/*
1373 * Two entries should be enough for the largest devman PRDT transfer (4 KiB),
1374 * like advanced RPMB.
1375 */
1376#define UFSHCD_DEVMAN_SG_ENTRIES 2
1377
1378static inline size_t ufshcd_get_devman_ucd_size(const struct ufs_hba *hba)
1379{
1380 return sizeof(struct utp_devman_cmd_desc) +
1381 UFSHCD_DEVMAN_SG_ENTRIES * ufshcd_sg_entry_size(hba);
1382}
1383
1384/* Returns true if clocks can be gated. Otherwise false */
1385static inline bool ufshcd_is_clkgating_allowed(struct ufs_hba *hba)
1386{
1387 return hba->caps & UFSHCD_CAP_CLK_GATING;
1388}
1389static inline bool ufshcd_can_hibern8_during_gating(struct ufs_hba *hba)
1390{
1391 return hba->caps & UFSHCD_CAP_HIBERN8_WITH_CLK_GATING;
1392}
1393static inline int ufshcd_is_clkscaling_supported(struct ufs_hba *hba)
1394{
1395 return hba->caps & UFSHCD_CAP_CLK_SCALING;
1396}
1397static inline bool ufshcd_can_autobkops_during_suspend(struct ufs_hba *hba)
1398{
1399 return hba->caps & UFSHCD_CAP_AUTO_BKOPS_SUSPEND;
1400}
1401static inline bool ufshcd_is_rpm_autosuspend_allowed(struct ufs_hba *hba)
1402{
1403 return hba->caps & UFSHCD_CAP_RPM_AUTOSUSPEND;
1404}
1405
1406static inline bool ufshcd_is_intr_aggr_allowed(struct ufs_hba *hba)
1407{
1408 return (hba->caps & UFSHCD_CAP_INTR_AGGR) &&
1409 !(hba->quirks & UFSHCD_QUIRK_BROKEN_INTR_AGGR);
1410}
1411
1412static inline bool ufshcd_can_aggressive_pc(struct ufs_hba *hba)
1413{
1414 return !!(ufshcd_is_link_hibern8(hba) &&
1415 (hba->caps & UFSHCD_CAP_AGGR_POWER_COLLAPSE));
1416}
1417
1418static inline bool ufshcd_is_auto_hibern8_supported(struct ufs_hba *hba)
1419{
1420 return (hba->capabilities & MASK_AUTO_HIBERN8_SUPPORT) &&
1421 !(hba->quirks & UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8);
1422}
1423
1424static inline bool ufshcd_is_auto_hibern8_enabled(struct ufs_hba *hba)
1425{
1426 return FIELD_GET(UFSHCI_AHIBERN8_TIMER_MASK, hba->ahit);
1427}
1428
1429static inline bool ufshcd_is_wb_allowed(struct ufs_hba *hba)
1430{
1431 return hba->caps & UFSHCD_CAP_WB_EN;
1432}
1433
1434static inline bool ufshcd_enable_wb_if_scaling_up(struct ufs_hba *hba)
1435{
1436 return hba->caps & UFSHCD_CAP_WB_WITH_CLK_SCALING;
1437}
1438
1439static inline bool ufshcd_is_tx_eq_supported(struct ufs_hba *hba)
1440{
1441 return hba->caps & UFSHCD_CAP_TX_EQUALIZATION &&
1442 hba->ufs_version >= ufshci_version(5, 0) &&
1443 hba->dev_info.wspecversion >= 0x500;
1444}
1445
1446#define ufsmcq_writel(hba, val, reg) \
1447 writel((val), (hba)->mcq_base + (reg))
1448#define ufsmcq_readl(hba, reg) \
1449 readl((hba)->mcq_base + (reg))
1450
1451#define ufsmcq_writelx(hba, val, reg) \
1452 writel_relaxed((val), (hba)->mcq_base + (reg))
1453#define ufsmcq_readlx(hba, reg) \
1454 readl_relaxed((hba)->mcq_base + (reg))
1455
1456#define ufshcd_writel(hba, val, reg) \
1457 writel((val), (hba)->mmio_base + (reg))
1458#define ufshcd_readl(hba, reg) \
1459 readl((hba)->mmio_base + (reg))
1460
1461static inline const char *ufs_hs_rate_to_str(enum ufs_hs_gear_rate rate)
1462{
1463 switch (rate) {
1464 case PA_HS_MODE_A:
1465 return "A";
1466 case PA_HS_MODE_B:
1467 return "B";
1468 default:
1469 return "Unknown";
1470 }
1471}
1472
1473/**
1474 * ufshcd_rmwl - perform read/modify/write for a controller register
1475 * @hba: per adapter instance
1476 * @mask: mask to apply on read value
1477 * @val: actual value to write
1478 * @reg: register address
1479 */
1480static inline void ufshcd_rmwl(struct ufs_hba *hba, u32 mask, u32 val, u32 reg)
1481{
1482 u32 tmp;
1483
1484 tmp = ufshcd_readl(hba, reg);
1485 tmp &= ~mask;
1486 tmp |= (val & mask);
1487 ufshcd_writel(hba, tmp, reg);
1488}
1489
1490void ufshcd_enable_irq(struct ufs_hba *hba);
1491void ufshcd_disable_irq(struct ufs_hba *hba);
1492int ufshcd_alloc_host(struct device *, struct ufs_hba **);
1493int ufshcd_hba_enable(struct ufs_hba *hba);
1494int ufshcd_init(struct ufs_hba *, void __iomem *, unsigned int);
1495int ufshcd_link_recovery(struct ufs_hba *hba);
1496int ufshcd_make_hba_operational(struct ufs_hba *hba);
1497void ufshcd_remove(struct ufs_hba *);
1498int ufshcd_uic_hibern8_enter(struct ufs_hba *hba);
1499int ufshcd_uic_hibern8_exit(struct ufs_hba *hba);
1500void ufshcd_delay_us(unsigned long us, unsigned long tolerance);
1501void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba, struct clk *refclk);
1502void ufshcd_update_evt_hist(struct ufs_hba *hba, u32 id, u32 val);
1503void ufshcd_hba_stop(struct ufs_hba *hba);
1504void ufshcd_schedule_eh_work(struct ufs_hba *hba);
1505void ufshcd_mcq_config_mac(struct ufs_hba *hba, u32 max_active_cmds);
1506unsigned int ufshcd_mcq_queue_cfg_addr(struct ufs_hba *hba);
1507u32 ufshcd_mcq_read_cqis(struct ufs_hba *hba, int i);
1508void ufshcd_mcq_write_cqis(struct ufs_hba *hba, u32 val, int i);
1509unsigned long ufshcd_mcq_poll_cqe_lock(struct ufs_hba *hba,
1510 struct ufs_hw_queue *hwq);
1511void ufshcd_mcq_make_queues_operational(struct ufs_hba *hba);
1512void ufshcd_mcq_enable(struct ufs_hba *hba);
1513void ufshcd_mcq_enable_esi(struct ufs_hba *hba);
1514void ufshcd_mcq_config_esi(struct ufs_hba *hba, struct msi_msg *msg);
1515
1516int ufshcd_opp_config_clks(struct device *dev, struct opp_table *opp_table,
1517 struct dev_pm_opp *opp, void *data,
1518 bool scaling_down);
1519/**
1520 * ufshcd_set_variant - set variant specific data to the hba
1521 * @hba: per adapter instance
1522 * @variant: pointer to variant specific data
1523 */
1524static inline void ufshcd_set_variant(struct ufs_hba *hba, void *variant)
1525{
1526 BUG_ON(!hba);
1527 hba->priv = variant;
1528}
1529
1530/**
1531 * ufshcd_get_variant - get variant specific data from the hba
1532 * @hba: per adapter instance
1533 *
1534 * Returns: pointer to the hba's private data area
1535 */
1536static inline void *ufshcd_get_variant(struct ufs_hba *hba)
1537{
1538 BUG_ON(!hba);
1539 return hba->priv;
1540}
1541
1542extern int ufshcd_runtime_suspend(struct device *dev);
1543extern int ufshcd_runtime_resume(struct device *dev);
1544extern int ufshcd_system_suspend(struct device *dev);
1545extern int ufshcd_system_resume(struct device *dev);
1546extern int ufshcd_system_freeze(struct device *dev);
1547extern int ufshcd_system_thaw(struct device *dev);
1548extern int ufshcd_system_restore(struct device *dev);
1549
1550extern int ufshcd_dme_reset(struct ufs_hba *hba);
1551extern int ufshcd_dme_enable(struct ufs_hba *hba);
1552extern int ufshcd_dme_configure_adapt(struct ufs_hba *hba,
1553 int agreed_gear,
1554 int adapt_val);
1555extern int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
1556 u8 attr_set, u32 mib_val, u8 peer);
1557extern int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
1558 u32 *mib_val, u8 peer);
1559extern int ufshcd_change_power_mode(struct ufs_hba *hba,
1560 struct ufs_pa_layer_attr *pwr_mode,
1561 enum ufshcd_pmc_policy pmc_policy);
1562extern int ufshcd_config_pwr_mode(struct ufs_hba *hba,
1563 struct ufs_pa_layer_attr *desired_pwr_mode,
1564 enum ufshcd_pmc_policy pmc_policy);
1565extern int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode);
1566extern int ufshcd_apply_tx_eq_settings(struct ufs_hba *hba,
1567 struct ufshcd_tx_eq_params *params,
1568 u32 gear);
1569
1570/* UIC command interfaces for DME primitives */
1571#define DME_LOCAL 0
1572#define DME_PEER 1
1573#define ATTR_SET_NOR 0 /* NORMAL */
1574#define ATTR_SET_ST 1 /* STATIC */
1575
1576static inline int ufshcd_dme_set(struct ufs_hba *hba, u32 attr_sel,
1577 u32 mib_val)
1578{
1579 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR,
1580 mib_val, DME_LOCAL);
1581}
1582
1583static inline int ufshcd_dme_st_set(struct ufs_hba *hba, u32 attr_sel,
1584 u32 mib_val)
1585{
1586 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_ST,
1587 mib_val, DME_LOCAL);
1588}
1589
1590static inline int ufshcd_dme_peer_set(struct ufs_hba *hba, u32 attr_sel,
1591 u32 mib_val)
1592{
1593 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR,
1594 mib_val, DME_PEER);
1595}
1596
1597static inline int ufshcd_dme_peer_st_set(struct ufs_hba *hba, u32 attr_sel,
1598 u32 mib_val)
1599{
1600 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_ST,
1601 mib_val, DME_PEER);
1602}
1603
1604static inline int ufshcd_dme_get(struct ufs_hba *hba,
1605 u32 attr_sel, u32 *mib_val)
1606{
1607 return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_LOCAL);
1608}
1609
1610static inline int ufshcd_dme_peer_get(struct ufs_hba *hba,
1611 u32 attr_sel, u32 *mib_val)
1612{
1613 return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_PEER);
1614}
1615
1616static inline bool ufshcd_is_hs_mode(const struct ufs_pa_layer_attr *pwr_info)
1617{
1618 return (pwr_info->pwr_rx == FAST_MODE ||
1619 pwr_info->pwr_rx == FASTAUTO_MODE) &&
1620 (pwr_info->pwr_tx == FAST_MODE ||
1621 pwr_info->pwr_tx == FASTAUTO_MODE);
1622}
1623
1624static inline int ufshcd_disable_host_tx_lcc(struct ufs_hba *hba)
1625{
1626 return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0);
1627}
1628
1629void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit);
1630void ufshcd_fixup_dev_quirks(struct ufs_hba *hba,
1631 const struct ufs_dev_quirk *fixups);
1632
1633void ufshcd_hold(struct ufs_hba *hba);
1634void ufshcd_release(struct ufs_hba *hba);
1635
1636void ufshcd_clkgate_delay_set(struct device *dev, unsigned long value);
1637
1638int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg);
1639
1640int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd);
1641
1642int ufshcd_advanced_rpmb_req_handler(struct ufs_hba *hba, struct utp_upiu_req *req_upiu,
1643 struct utp_upiu_req *rsp_upiu, struct ufs_ehs *ehs_req,
1644 struct ufs_ehs *ehs_rsp, int sg_cnt,
1645 struct scatterlist *sg_list, enum dma_data_direction dir);
1646int ufshcd_wb_toggle(struct ufs_hba *hba, bool enable);
1647int ufshcd_wb_toggle_buf_flush(struct ufs_hba *hba, bool enable);
1648int ufshcd_wb_set_resize_en(struct ufs_hba *hba, enum wb_resize_en en_mode);
1649int ufshcd_suspend_prepare(struct device *dev);
1650int __ufshcd_suspend_prepare(struct device *dev, bool rpm_ok_for_spm);
1651void ufshcd_resume_complete(struct device *dev);
1652bool ufshcd_is_hba_active(struct ufs_hba *hba);
1653void ufshcd_pm_qos_init(struct ufs_hba *hba);
1654void ufshcd_pm_qos_exit(struct ufs_hba *hba);
1655int ufshcd_dme_rmw(struct ufs_hba *hba, u32 mask, u32 val, u32 attr);
1656
1657/* Wrapper functions for safely calling variant operations */
1658static inline int ufshcd_vops_init(struct ufs_hba *hba)
1659{
1660 if (hba->vops && hba->vops->init)
1661 return hba->vops->init(hba);
1662
1663 return 0;
1664}
1665
1666static inline int ufshcd_vops_phy_initialization(struct ufs_hba *hba)
1667{
1668 if (hba->vops && hba->vops->phy_initialization)
1669 return hba->vops->phy_initialization(hba);
1670
1671 return 0;
1672}
1673
1674extern const struct ufs_pm_lvl_states ufs_pm_lvl_states[];
1675
1676int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len,
1677 const char *prefix);
1678
1679int __ufshcd_write_ee_control(struct ufs_hba *hba, u32 ee_ctrl_mask);
1680int ufshcd_write_ee_control(struct ufs_hba *hba);
1681int ufshcd_update_ee_control(struct ufs_hba *hba, u16 *mask,
1682 const u16 *other_mask, u16 set, u16 clr);
1683void ufshcd_force_error_recovery(struct ufs_hba *hba);
1684void ufshcd_pm_qos_update(struct ufs_hba *hba, bool on);
1685u32 ufshcd_us_to_ahit(unsigned int timer);
1686
1687#endif /* End of Header */