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1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * ATI Mach64 Register Definitions
4 *
5 * Copyright (C) 1997 Michael AK Tesch
6 * written with much help from Jon Howell
7 *
8 * Updated for 3D RAGE PRO and 3D RAGE Mobility by Geert Uytterhoeven
9 */
10
11/*
12 * most of the rest of this file comes from ATI sample code
13 */
14#ifndef REGMACH64_H
15#define REGMACH64_H
16
17/* NON-GUI MEMORY MAPPED Registers - expressed in BYTE offsets */
18
19/* Accelerator CRTC */
20#define CRTC_H_TOTAL_DISP 0x0000 /* Dword offset 0_00 */
21#define CRTC2_H_TOTAL_DISP 0x0000 /* Dword offset 0_00 */
22#define CRTC_H_SYNC_STRT_WID 0x0004 /* Dword offset 0_01 */
23#define CRTC2_H_SYNC_STRT_WID 0x0004 /* Dword offset 0_01 */
24#define CRTC_H_SYNC_STRT 0x0004
25#define CRTC2_H_SYNC_STRT 0x0004
26#define CRTC_H_SYNC_DLY 0x0005
27#define CRTC2_H_SYNC_DLY 0x0005
28#define CRTC_H_SYNC_WID 0x0006
29#define CRTC2_H_SYNC_WID 0x0006
30#define CRTC_V_TOTAL_DISP 0x0008 /* Dword offset 0_02 */
31#define CRTC2_V_TOTAL_DISP 0x0008 /* Dword offset 0_02 */
32#define CRTC_V_TOTAL 0x0008
33#define CRTC2_V_TOTAL 0x0008
34#define CRTC_V_DISP 0x000A
35#define CRTC2_V_DISP 0x000A
36#define CRTC_V_SYNC_STRT_WID 0x000C /* Dword offset 0_03 */
37#define CRTC2_V_SYNC_STRT_WID 0x000C /* Dword offset 0_03 */
38#define CRTC_V_SYNC_STRT 0x000C
39#define CRTC2_V_SYNC_STRT 0x000C
40#define CRTC_V_SYNC_WID 0x000E
41#define CRTC2_V_SYNC_WID 0x000E
42#define CRTC_VLINE_CRNT_VLINE 0x0010 /* Dword offset 0_04 */
43#define CRTC2_VLINE_CRNT_VLINE 0x0010 /* Dword offset 0_04 */
44#define CRTC_OFF_PITCH 0x0014 /* Dword offset 0_05 */
45#define CRTC_OFFSET 0x0014
46#define CRTC_PITCH 0x0016
47#define CRTC_INT_CNTL 0x0018 /* Dword offset 0_06 */
48#define CRTC_GEN_CNTL 0x001C /* Dword offset 0_07 */
49#define CRTC_PIX_WIDTH 0x001D
50#define CRTC_FIFO 0x001E
51#define CRTC_EXT_DISP 0x001F
52
53/* Memory Buffer Control */
54#define DSP_CONFIG 0x0020 /* Dword offset 0_08 */
55#define PM_DSP_CONFIG 0x0020 /* Dword offset 0_08 (Mobility Only) */
56#define DSP_ON_OFF 0x0024 /* Dword offset 0_09 */
57#define PM_DSP_ON_OFF 0x0024 /* Dword offset 0_09 (Mobility Only) */
58#define TIMER_CONFIG 0x0028 /* Dword offset 0_0A */
59#define MEM_BUF_CNTL 0x002C /* Dword offset 0_0B */
60#define MEM_ADDR_CONFIG 0x0034 /* Dword offset 0_0D */
61
62/* Accelerator CRTC */
63#define CRT_TRAP 0x0038 /* Dword offset 0_0E */
64
65#define I2C_CNTL_0 0x003C /* Dword offset 0_0F */
66
67#define DSTN_CONTROL_LG 0x003C /* Dword offset 0_0F (LG) */
68
69/* Overscan */
70#define OVR_CLR 0x0040 /* Dword offset 0_10 */
71#define OVR2_CLR 0x0040 /* Dword offset 0_10 */
72#define OVR_WID_LEFT_RIGHT 0x0044 /* Dword offset 0_11 */
73#define OVR2_WID_LEFT_RIGHT 0x0044 /* Dword offset 0_11 */
74#define OVR_WID_TOP_BOTTOM 0x0048 /* Dword offset 0_12 */
75#define OVR2_WID_TOP_BOTTOM 0x0048 /* Dword offset 0_12 */
76
77/* Memory Buffer Control */
78#define VGA_DSP_CONFIG 0x004C /* Dword offset 0_13 */
79#define PM_VGA_DSP_CONFIG 0x004C /* Dword offset 0_13 (Mobility Only) */
80#define VGA_DSP_ON_OFF 0x0050 /* Dword offset 0_14 */
81#define PM_VGA_DSP_ON_OFF 0x0050 /* Dword offset 0_14 (Mobility Only) */
82#define DSP2_CONFIG 0x0054 /* Dword offset 0_15 */
83#define PM_DSP2_CONFIG 0x0054 /* Dword offset 0_15 (Mobility Only) */
84#define DSP2_ON_OFF 0x0058 /* Dword offset 0_16 */
85#define PM_DSP2_ON_OFF 0x0058 /* Dword offset 0_16 (Mobility Only) */
86
87/* Accelerator CRTC */
88#define CRTC2_OFF_PITCH 0x005C /* Dword offset 0_17 */
89
90/* Hardware Cursor */
91#define CUR_CLR0 0x0060 /* Dword offset 0_18 */
92#define CUR2_CLR0 0x0060 /* Dword offset 0_18 */
93#define CUR_CLR1 0x0064 /* Dword offset 0_19 */
94#define CUR2_CLR1 0x0064 /* Dword offset 0_19 */
95#define CUR_OFFSET 0x0068 /* Dword offset 0_1A */
96#define CUR2_OFFSET 0x0068 /* Dword offset 0_1A */
97#define CUR_HORZ_VERT_POSN 0x006C /* Dword offset 0_1B */
98#define CUR2_HORZ_VERT_POSN 0x006C /* Dword offset 0_1B */
99#define CUR_HORZ_VERT_OFF 0x0070 /* Dword offset 0_1C */
100#define CUR2_HORZ_VERT_OFF 0x0070 /* Dword offset 0_1C */
101
102#define CNFG_PANEL_LG 0x0074 /* Dword offset 0_1D (LG) */
103
104/* General I/O Control */
105#define GP_IO 0x0078 /* Dword offset 0_1E */
106
107/* Test and Debug */
108#define HW_DEBUG 0x007C /* Dword offset 0_1F */
109
110/* Scratch Pad and Test */
111#define SCRATCH_REG0 0x0080 /* Dword offset 0_20 */
112#define SCRATCH_REG1 0x0084 /* Dword offset 0_21 */
113#define SCRATCH_REG2 0x0088 /* Dword offset 0_22 */
114#define SCRATCH_REG3 0x008C /* Dword offset 0_23 */
115
116/* Clock Control */
117#define CLOCK_CNTL 0x0090 /* Dword offset 0_24 */
118/* CLOCK_CNTL register constants CT LAYOUT */
119#define CLOCK_SEL 0x0f
120#define CLOCK_SEL_INTERNAL 0x03
121#define CLOCK_SEL_EXTERNAL 0x0c
122#define CLOCK_DIV 0x30
123#define CLOCK_DIV1 0x00
124#define CLOCK_DIV2 0x10
125#define CLOCK_DIV4 0x20
126#define CLOCK_STROBE 0x40
127/* ? 0x80 */
128/* CLOCK_CNTL register constants GX LAYOUT */
129#define CLOCK_BIT 0x04 /* For ICS2595 */
130#define CLOCK_PULSE 0x08 /* For ICS2595 */
131/*#define CLOCK_STROBE 0x40 dito as CT */
132#define CLOCK_DATA 0x80
133
134/* For internal PLL(CT) start */
135#define CLOCK_CNTL_ADDR CLOCK_CNTL + 1
136#define PLL_WR_EN 0x02
137#define PLL_ADDR 0xfc
138#define CLOCK_CNTL_DATA CLOCK_CNTL + 2
139#define PLL_DATA 0xff
140/* For internal PLL(CT) end */
141
142#define CLOCK_SEL_CNTL 0x0090 /* Dword offset 0_24 */
143
144/* Configuration */
145#define CNFG_STAT1 0x0094 /* Dword offset 0_25 */
146#define CNFG_STAT2 0x0098 /* Dword offset 0_26 */
147
148/* Bus Control */
149#define BUS_CNTL 0x00A0 /* Dword offset 0_28 */
150
151#define LCD_INDEX 0x00A4 /* Dword offset 0_29 */
152#define LCD_DATA 0x00A8 /* Dword offset 0_2A */
153
154#define HFB_PITCH_ADDR_LG 0x00A8 /* Dword offset 0_2A (LG) */
155
156/* Memory Control */
157#define EXT_MEM_CNTL 0x00AC /* Dword offset 0_2B */
158#define MEM_CNTL 0x00B0 /* Dword offset 0_2C */
159#define MEM_VGA_WP_SEL 0x00B4 /* Dword offset 0_2D */
160#define MEM_VGA_RP_SEL 0x00B8 /* Dword offset 0_2E */
161
162#define I2C_CNTL_1 0x00BC /* Dword offset 0_2F */
163
164#define LT_GIO_LG 0x00BC /* Dword offset 0_2F (LG) */
165
166/* DAC Control */
167#define DAC_REGS 0x00C0 /* Dword offset 0_30 */
168#define DAC_W_INDEX 0x00C0 /* Dword offset 0_30 */
169#define DAC_DATA 0x00C1 /* Dword offset 0_30 */
170#define DAC_MASK 0x00C2 /* Dword offset 0_30 */
171#define DAC_R_INDEX 0x00C3 /* Dword offset 0_30 */
172#define DAC_CNTL 0x00C4 /* Dword offset 0_31 */
173
174#define EXT_DAC_REGS 0x00C8 /* Dword offset 0_32 */
175
176#define HORZ_STRETCHING_LG 0x00C8 /* Dword offset 0_32 (LG) */
177#define VERT_STRETCHING_LG 0x00CC /* Dword offset 0_33 (LG) */
178
179/* Test and Debug */
180#define GEN_TEST_CNTL 0x00D0 /* Dword offset 0_34 */
181
182/* Custom Macros */
183#define CUSTOM_MACRO_CNTL 0x00D4 /* Dword offset 0_35 */
184
185#define LCD_GEN_CNTL_LG 0x00D4 /* Dword offset 0_35 (LG) */
186#define POWER_MANAGEMENT_LG 0x00D8 /* Dword offset 0_36 (LG) */
187
188/* Configuration */
189#define CNFG_CNTL 0x00DC /* Dword offset 0_37 (CT, ET, VT) */
190#define CNFG_CHIP_ID 0x00E0 /* Dword offset 0_38 */
191#define CNFG_STAT0 0x00E4 /* Dword offset 0_39 */
192
193/* Test and Debug */
194#define CRC_SIG 0x00E8 /* Dword offset 0_3A */
195#define CRC2_SIG 0x00E8 /* Dword offset 0_3A */
196
197
198/* GUI MEMORY MAPPED Registers */
199
200/* Draw Engine Destination Trajectory */
201#define DST_OFF_PITCH 0x0100 /* Dword offset 0_40 */
202#define DST_X 0x0104 /* Dword offset 0_41 */
203#define DST_Y 0x0108 /* Dword offset 0_42 */
204#define DST_Y_X 0x010C /* Dword offset 0_43 */
205#define DST_WIDTH 0x0110 /* Dword offset 0_44 */
206#define DST_HEIGHT 0x0114 /* Dword offset 0_45 */
207#define DST_HEIGHT_WIDTH 0x0118 /* Dword offset 0_46 */
208#define DST_X_WIDTH 0x011C /* Dword offset 0_47 */
209#define DST_BRES_LNTH 0x0120 /* Dword offset 0_48 */
210#define DST_BRES_ERR 0x0124 /* Dword offset 0_49 */
211#define DST_BRES_INC 0x0128 /* Dword offset 0_4A */
212#define DST_BRES_DEC 0x012C /* Dword offset 0_4B */
213#define DST_CNTL 0x0130 /* Dword offset 0_4C */
214#define DST_Y_X__ALIAS__ 0x0134 /* Dword offset 0_4D */
215#define TRAIL_BRES_ERR 0x0138 /* Dword offset 0_4E */
216#define TRAIL_BRES_INC 0x013C /* Dword offset 0_4F */
217#define TRAIL_BRES_DEC 0x0140 /* Dword offset 0_50 */
218#define LEAD_BRES_LNTH 0x0144 /* Dword offset 0_51 */
219#define Z_OFF_PITCH 0x0148 /* Dword offset 0_52 */
220#define Z_CNTL 0x014C /* Dword offset 0_53 */
221#define ALPHA_TST_CNTL 0x0150 /* Dword offset 0_54 */
222#define SECONDARY_STW_EXP 0x0158 /* Dword offset 0_56 */
223#define SECONDARY_S_X_INC 0x015C /* Dword offset 0_57 */
224#define SECONDARY_S_Y_INC 0x0160 /* Dword offset 0_58 */
225#define SECONDARY_S_START 0x0164 /* Dword offset 0_59 */
226#define SECONDARY_W_X_INC 0x0168 /* Dword offset 0_5A */
227#define SECONDARY_W_Y_INC 0x016C /* Dword offset 0_5B */
228#define SECONDARY_W_START 0x0170 /* Dword offset 0_5C */
229#define SECONDARY_T_X_INC 0x0174 /* Dword offset 0_5D */
230#define SECONDARY_T_Y_INC 0x0178 /* Dword offset 0_5E */
231#define SECONDARY_T_START 0x017C /* Dword offset 0_5F */
232
233/* Draw Engine Source Trajectory */
234#define SRC_OFF_PITCH 0x0180 /* Dword offset 0_60 */
235#define SRC_X 0x0184 /* Dword offset 0_61 */
236#define SRC_Y 0x0188 /* Dword offset 0_62 */
237#define SRC_Y_X 0x018C /* Dword offset 0_63 */
238#define SRC_WIDTH1 0x0190 /* Dword offset 0_64 */
239#define SRC_HEIGHT1 0x0194 /* Dword offset 0_65 */
240#define SRC_HEIGHT1_WIDTH1 0x0198 /* Dword offset 0_66 */
241#define SRC_X_START 0x019C /* Dword offset 0_67 */
242#define SRC_Y_START 0x01A0 /* Dword offset 0_68 */
243#define SRC_Y_X_START 0x01A4 /* Dword offset 0_69 */
244#define SRC_WIDTH2 0x01A8 /* Dword offset 0_6A */
245#define SRC_HEIGHT2 0x01AC /* Dword offset 0_6B */
246#define SRC_HEIGHT2_WIDTH2 0x01B0 /* Dword offset 0_6C */
247#define SRC_CNTL 0x01B4 /* Dword offset 0_6D */
248
249#define SCALE_OFF 0x01C0 /* Dword offset 0_70 */
250#define SECONDARY_SCALE_OFF 0x01C4 /* Dword offset 0_71 */
251
252#define TEX_0_OFF 0x01C0 /* Dword offset 0_70 */
253#define TEX_1_OFF 0x01C4 /* Dword offset 0_71 */
254#define TEX_2_OFF 0x01C8 /* Dword offset 0_72 */
255#define TEX_3_OFF 0x01CC /* Dword offset 0_73 */
256#define TEX_4_OFF 0x01D0 /* Dword offset 0_74 */
257#define TEX_5_OFF 0x01D4 /* Dword offset 0_75 */
258#define TEX_6_OFF 0x01D8 /* Dword offset 0_76 */
259#define TEX_7_OFF 0x01DC /* Dword offset 0_77 */
260
261#define SCALE_WIDTH 0x01DC /* Dword offset 0_77 */
262#define SCALE_HEIGHT 0x01E0 /* Dword offset 0_78 */
263
264#define TEX_8_OFF 0x01E0 /* Dword offset 0_78 */
265#define TEX_9_OFF 0x01E4 /* Dword offset 0_79 */
266#define TEX_10_OFF 0x01E8 /* Dword offset 0_7A */
267#define S_Y_INC 0x01EC /* Dword offset 0_7B */
268
269#define SCALE_PITCH 0x01EC /* Dword offset 0_7B */
270#define SCALE_X_INC 0x01F0 /* Dword offset 0_7C */
271
272#define RED_X_INC 0x01F0 /* Dword offset 0_7C */
273#define GREEN_X_INC 0x01F4 /* Dword offset 0_7D */
274
275#define SCALE_Y_INC 0x01F4 /* Dword offset 0_7D */
276#define SCALE_VACC 0x01F8 /* Dword offset 0_7E */
277#define SCALE_3D_CNTL 0x01FC /* Dword offset 0_7F */
278
279/* Host Data */
280#define HOST_DATA0 0x0200 /* Dword offset 0_80 */
281#define HOST_DATA1 0x0204 /* Dword offset 0_81 */
282#define HOST_DATA2 0x0208 /* Dword offset 0_82 */
283#define HOST_DATA3 0x020C /* Dword offset 0_83 */
284#define HOST_DATA4 0x0210 /* Dword offset 0_84 */
285#define HOST_DATA5 0x0214 /* Dword offset 0_85 */
286#define HOST_DATA6 0x0218 /* Dword offset 0_86 */
287#define HOST_DATA7 0x021C /* Dword offset 0_87 */
288#define HOST_DATA8 0x0220 /* Dword offset 0_88 */
289#define HOST_DATA9 0x0224 /* Dword offset 0_89 */
290#define HOST_DATAA 0x0228 /* Dword offset 0_8A */
291#define HOST_DATAB 0x022C /* Dword offset 0_8B */
292#define HOST_DATAC 0x0230 /* Dword offset 0_8C */
293#define HOST_DATAD 0x0234 /* Dword offset 0_8D */
294#define HOST_DATAE 0x0238 /* Dword offset 0_8E */
295#define HOST_DATAF 0x023C /* Dword offset 0_8F */
296#define HOST_CNTL 0x0240 /* Dword offset 0_90 */
297
298/* GUI Bus Mastering */
299#define BM_HOSTDATA 0x0244 /* Dword offset 0_91 */
300#define BM_ADDR 0x0248 /* Dword offset 0_92 */
301#define BM_DATA 0x0248 /* Dword offset 0_92 */
302#define BM_GUI_TABLE_CMD 0x024C /* Dword offset 0_93 */
303
304/* Pattern */
305#define PAT_REG0 0x0280 /* Dword offset 0_A0 */
306#define PAT_REG1 0x0284 /* Dword offset 0_A1 */
307#define PAT_CNTL 0x0288 /* Dword offset 0_A2 */
308
309/* Scissors */
310#define SC_LEFT 0x02A0 /* Dword offset 0_A8 */
311#define SC_RIGHT 0x02A4 /* Dword offset 0_A9 */
312#define SC_LEFT_RIGHT 0x02A8 /* Dword offset 0_AA */
313#define SC_TOP 0x02AC /* Dword offset 0_AB */
314#define SC_BOTTOM 0x02B0 /* Dword offset 0_AC */
315#define SC_TOP_BOTTOM 0x02B4 /* Dword offset 0_AD */
316
317/* Data Path */
318#define USR1_DST_OFF_PITCH 0x02B8 /* Dword offset 0_AE */
319#define USR2_DST_OFF_PITCH 0x02BC /* Dword offset 0_AF */
320#define DP_BKGD_CLR 0x02C0 /* Dword offset 0_B0 */
321#define DP_FOG_CLR 0x02C4 /* Dword offset 0_B1 */
322#define DP_FRGD_CLR 0x02C4 /* Dword offset 0_B1 */
323#define DP_WRITE_MASK 0x02C8 /* Dword offset 0_B2 */
324#define DP_CHAIN_MASK 0x02CC /* Dword offset 0_B3 */
325#define DP_PIX_WIDTH 0x02D0 /* Dword offset 0_B4 */
326#define DP_MIX 0x02D4 /* Dword offset 0_B5 */
327#define DP_SRC 0x02D8 /* Dword offset 0_B6 */
328#define DP_FRGD_CLR_MIX 0x02DC /* Dword offset 0_B7 */
329#define DP_FRGD_BKGD_CLR 0x02E0 /* Dword offset 0_B8 */
330
331/* Draw Engine Destination Trajectory */
332#define DST_X_Y 0x02E8 /* Dword offset 0_BA */
333#define DST_WIDTH_HEIGHT 0x02EC /* Dword offset 0_BB */
334
335/* Data Path */
336#define USR_DST_PICTH 0x02F0 /* Dword offset 0_BC */
337#define DP_SET_GUI_ENGINE2 0x02F8 /* Dword offset 0_BE */
338#define DP_SET_GUI_ENGINE 0x02FC /* Dword offset 0_BF */
339
340/* Color Compare */
341#define CLR_CMP_CLR 0x0300 /* Dword offset 0_C0 */
342#define CLR_CMP_MASK 0x0304 /* Dword offset 0_C1 */
343#define CLR_CMP_CNTL 0x0308 /* Dword offset 0_C2 */
344
345/* Command FIFO */
346#define FIFO_STAT 0x0310 /* Dword offset 0_C4 */
347
348#define CONTEXT_MASK 0x0320 /* Dword offset 0_C8 */
349#define CONTEXT_LOAD_CNTL 0x032C /* Dword offset 0_CB */
350
351/* Engine Control */
352#define GUI_TRAJ_CNTL 0x0330 /* Dword offset 0_CC */
353
354/* Engine Status/FIFO */
355#define GUI_STAT 0x0338 /* Dword offset 0_CE */
356
357#define TEX_PALETTE_INDEX 0x0340 /* Dword offset 0_D0 */
358#define STW_EXP 0x0344 /* Dword offset 0_D1 */
359#define LOG_MAX_INC 0x0348 /* Dword offset 0_D2 */
360#define S_X_INC 0x034C /* Dword offset 0_D3 */
361#define S_Y_INC__ALIAS__ 0x0350 /* Dword offset 0_D4 */
362
363#define SCALE_PITCH__ALIAS__ 0x0350 /* Dword offset 0_D4 */
364
365#define S_START 0x0354 /* Dword offset 0_D5 */
366#define W_X_INC 0x0358 /* Dword offset 0_D6 */
367#define W_Y_INC 0x035C /* Dword offset 0_D7 */
368#define W_START 0x0360 /* Dword offset 0_D8 */
369#define T_X_INC 0x0364 /* Dword offset 0_D9 */
370#define T_Y_INC 0x0368 /* Dword offset 0_DA */
371
372#define SECONDARY_SCALE_PITCH 0x0368 /* Dword offset 0_DA */
373
374#define T_START 0x036C /* Dword offset 0_DB */
375#define TEX_SIZE_PITCH 0x0370 /* Dword offset 0_DC */
376#define TEX_CNTL 0x0374 /* Dword offset 0_DD */
377#define SECONDARY_TEX_OFFSET 0x0378 /* Dword offset 0_DE */
378#define TEX_PALETTE 0x037C /* Dword offset 0_DF */
379
380#define SCALE_PITCH_BOTH 0x0380 /* Dword offset 0_E0 */
381#define SECONDARY_SCALE_OFF_ACC 0x0384 /* Dword offset 0_E1 */
382#define SCALE_OFF_ACC 0x0388 /* Dword offset 0_E2 */
383#define SCALE_DST_Y_X 0x038C /* Dword offset 0_E3 */
384
385/* Draw Engine Destination Trajectory */
386#define COMPOSITE_SHADOW_ID 0x0398 /* Dword offset 0_E6 */
387
388#define SECONDARY_SCALE_X_INC 0x039C /* Dword offset 0_E7 */
389
390#define SPECULAR_RED_X_INC 0x039C /* Dword offset 0_E7 */
391#define SPECULAR_RED_Y_INC 0x03A0 /* Dword offset 0_E8 */
392#define SPECULAR_RED_START 0x03A4 /* Dword offset 0_E9 */
393
394#define SECONDARY_SCALE_HACC 0x03A4 /* Dword offset 0_E9 */
395
396#define SPECULAR_GREEN_X_INC 0x03A8 /* Dword offset 0_EA */
397#define SPECULAR_GREEN_Y_INC 0x03AC /* Dword offset 0_EB */
398#define SPECULAR_GREEN_START 0x03B0 /* Dword offset 0_EC */
399#define SPECULAR_BLUE_X_INC 0x03B4 /* Dword offset 0_ED */
400#define SPECULAR_BLUE_Y_INC 0x03B8 /* Dword offset 0_EE */
401#define SPECULAR_BLUE_START 0x03BC /* Dword offset 0_EF */
402
403#define SCALE_X_INC__ALIAS__ 0x03C0 /* Dword offset 0_F0 */
404
405#define RED_X_INC__ALIAS__ 0x03C0 /* Dword offset 0_F0 */
406#define RED_Y_INC 0x03C4 /* Dword offset 0_F1 */
407#define RED_START 0x03C8 /* Dword offset 0_F2 */
408
409#define SCALE_HACC 0x03C8 /* Dword offset 0_F2 */
410#define SCALE_Y_INC__ALIAS__ 0x03CC /* Dword offset 0_F3 */
411
412#define GREEN_X_INC__ALIAS__ 0x03CC /* Dword offset 0_F3 */
413#define GREEN_Y_INC 0x03D0 /* Dword offset 0_F4 */
414
415#define SECONDARY_SCALE_Y_INC 0x03D0 /* Dword offset 0_F4 */
416#define SECONDARY_SCALE_VACC 0x03D4 /* Dword offset 0_F5 */
417
418#define GREEN_START 0x03D4 /* Dword offset 0_F5 */
419#define BLUE_X_INC 0x03D8 /* Dword offset 0_F6 */
420#define BLUE_Y_INC 0x03DC /* Dword offset 0_F7 */
421#define BLUE_START 0x03E0 /* Dword offset 0_F8 */
422#define Z_X_INC 0x03E4 /* Dword offset 0_F9 */
423#define Z_Y_INC 0x03E8 /* Dword offset 0_FA */
424#define Z_START 0x03EC /* Dword offset 0_FB */
425#define ALPHA_X_INC 0x03F0 /* Dword offset 0_FC */
426#define FOG_X_INC 0x03F0 /* Dword offset 0_FC */
427#define ALPHA_Y_INC 0x03F4 /* Dword offset 0_FD */
428#define FOG_Y_INC 0x03F4 /* Dword offset 0_FD */
429#define ALPHA_START 0x03F8 /* Dword offset 0_FE */
430#define FOG_START 0x03F8 /* Dword offset 0_FE */
431
432#define OVERLAY_Y_X_START 0x0400 /* Dword offset 1_00 */
433#define OVERLAY_Y_X_END 0x0404 /* Dword offset 1_01 */
434#define OVERLAY_VIDEO_KEY_CLR 0x0408 /* Dword offset 1_02 */
435#define OVERLAY_VIDEO_KEY_MSK 0x040C /* Dword offset 1_03 */
436#define OVERLAY_GRAPHICS_KEY_CLR 0x0410 /* Dword offset 1_04 */
437#define OVERLAY_GRAPHICS_KEY_MSK 0x0414 /* Dword offset 1_05 */
438#define OVERLAY_KEY_CNTL 0x0418 /* Dword offset 1_06 */
439
440#define OVERLAY_SCALE_INC 0x0420 /* Dword offset 1_08 */
441#define OVERLAY_SCALE_CNTL 0x0424 /* Dword offset 1_09 */
442#define SCALER_HEIGHT_WIDTH 0x0428 /* Dword offset 1_0A */
443#define SCALER_TEST 0x042C /* Dword offset 1_0B */
444#define SCALER_BUF0_OFFSET 0x0434 /* Dword offset 1_0D */
445#define SCALER_BUF1_OFFSET 0x0438 /* Dword offset 1_0E */
446#define SCALE_BUF_PITCH 0x043C /* Dword offset 1_0F */
447
448#define CAPTURE_START_END 0x0440 /* Dword offset 1_10 */
449#define CAPTURE_X_WIDTH 0x0444 /* Dword offset 1_11 */
450#define VIDEO_FORMAT 0x0448 /* Dword offset 1_12 */
451#define VBI_START_END 0x044C /* Dword offset 1_13 */
452#define CAPTURE_CONFIG 0x0450 /* Dword offset 1_14 */
453#define TRIG_CNTL 0x0454 /* Dword offset 1_15 */
454
455#define OVERLAY_EXCLUSIVE_HORZ 0x0458 /* Dword offset 1_16 */
456#define OVERLAY_EXCLUSIVE_VERT 0x045C /* Dword offset 1_17 */
457
458#define VAL_WIDTH 0x0460 /* Dword offset 1_18 */
459#define CAPTURE_DEBUG 0x0464 /* Dword offset 1_19 */
460#define VIDEO_SYNC_TEST 0x0468 /* Dword offset 1_1A */
461
462/* GenLocking */
463#define SNAPSHOT_VH_COUNTS 0x0470 /* Dword offset 1_1C */
464#define SNAPSHOT_F_COUNT 0x0474 /* Dword offset 1_1D */
465#define N_VIF_COUNT 0x0478 /* Dword offset 1_1E */
466#define SNAPSHOT_VIF_COUNT 0x047C /* Dword offset 1_1F */
467
468#define CAPTURE_BUF0_OFFSET 0x0480 /* Dword offset 1_20 */
469#define CAPTURE_BUF1_OFFSET 0x0484 /* Dword offset 1_21 */
470#define CAPTURE_BUF_PITCH 0x0488 /* Dword offset 1_22 */
471
472/* GenLocking */
473#define SNAPSHOT2_VH_COUNTS 0x04B0 /* Dword offset 1_2C */
474#define SNAPSHOT2_F_COUNT 0x04B4 /* Dword offset 1_2D */
475#define N_VIF2_COUNT 0x04B8 /* Dword offset 1_2E */
476#define SNAPSHOT2_VIF_COUNT 0x04BC /* Dword offset 1_2F */
477
478#define MPP_CONFIG 0x04C0 /* Dword offset 1_30 */
479#define MPP_STROBE_SEQ 0x04C4 /* Dword offset 1_31 */
480#define MPP_ADDR 0x04C8 /* Dword offset 1_32 */
481#define MPP_DATA 0x04CC /* Dword offset 1_33 */
482#define TVO_CNTL 0x0500 /* Dword offset 1_40 */
483
484/* Test and Debug */
485#define CRT_HORZ_VERT_LOAD 0x0544 /* Dword offset 1_51 */
486
487/* AGP */
488#define AGP_BASE 0x0548 /* Dword offset 1_52 */
489#define AGP_CNTL 0x054C /* Dword offset 1_53 */
490
491#define SCALER_COLOUR_CNTL 0x0550 /* Dword offset 1_54 */
492#define SCALER_H_COEFF0 0x0554 /* Dword offset 1_55 */
493#define SCALER_H_COEFF1 0x0558 /* Dword offset 1_56 */
494#define SCALER_H_COEFF2 0x055C /* Dword offset 1_57 */
495#define SCALER_H_COEFF3 0x0560 /* Dword offset 1_58 */
496#define SCALER_H_COEFF4 0x0564 /* Dword offset 1_59 */
497
498/* Command FIFO */
499#define GUI_CMDFIFO_DEBUG 0x0570 /* Dword offset 1_5C */
500#define GUI_CMDFIFO_DATA 0x0574 /* Dword offset 1_5D */
501#define GUI_CNTL 0x0578 /* Dword offset 1_5E */
502
503/* Bus Mastering */
504#define BM_FRAME_BUF_OFFSET 0x0580 /* Dword offset 1_60 */
505#define BM_SYSTEM_MEM_ADDR 0x0584 /* Dword offset 1_61 */
506#define BM_COMMAND 0x0588 /* Dword offset 1_62 */
507#define BM_STATUS 0x058C /* Dword offset 1_63 */
508#define BM_GUI_TABLE 0x05B8 /* Dword offset 1_6E */
509#define BM_SYSTEM_TABLE 0x05BC /* Dword offset 1_6F */
510
511#define SCALER_BUF0_OFFSET_U 0x05D4 /* Dword offset 1_75 */
512#define SCALER_BUF0_OFFSET_V 0x05D8 /* Dword offset 1_76 */
513#define SCALER_BUF1_OFFSET_U 0x05DC /* Dword offset 1_77 */
514#define SCALER_BUF1_OFFSET_V 0x05E0 /* Dword offset 1_78 */
515
516/* Setup Engine */
517#define VERTEX_1_S 0x0640 /* Dword offset 1_90 */
518#define VERTEX_1_T 0x0644 /* Dword offset 1_91 */
519#define VERTEX_1_W 0x0648 /* Dword offset 1_92 */
520#define VERTEX_1_SPEC_ARGB 0x064C /* Dword offset 1_93 */
521#define VERTEX_1_Z 0x0650 /* Dword offset 1_94 */
522#define VERTEX_1_ARGB 0x0654 /* Dword offset 1_95 */
523#define VERTEX_1_X_Y 0x0658 /* Dword offset 1_96 */
524#define ONE_OVER_AREA 0x065C /* Dword offset 1_97 */
525#define VERTEX_2_S 0x0660 /* Dword offset 1_98 */
526#define VERTEX_2_T 0x0664 /* Dword offset 1_99 */
527#define VERTEX_2_W 0x0668 /* Dword offset 1_9A */
528#define VERTEX_2_SPEC_ARGB 0x066C /* Dword offset 1_9B */
529#define VERTEX_2_Z 0x0670 /* Dword offset 1_9C */
530#define VERTEX_2_ARGB 0x0674 /* Dword offset 1_9D */
531#define VERTEX_2_X_Y 0x0678 /* Dword offset 1_9E */
532#define ONE_OVER_AREA 0x065C /* Dword offset 1_9F */
533#define VERTEX_3_S 0x0680 /* Dword offset 1_A0 */
534#define VERTEX_3_T 0x0684 /* Dword offset 1_A1 */
535#define VERTEX_3_W 0x0688 /* Dword offset 1_A2 */
536#define VERTEX_3_SPEC_ARGB 0x068C /* Dword offset 1_A3 */
537#define VERTEX_3_Z 0x0690 /* Dword offset 1_A4 */
538#define VERTEX_3_ARGB 0x0694 /* Dword offset 1_A5 */
539#define VERTEX_3_X_Y 0x0698 /* Dword offset 1_A6 */
540#define ONE_OVER_AREA 0x065C /* Dword offset 1_A7 */
541#define VERTEX_1_S 0x0640 /* Dword offset 1_AB */
542#define VERTEX_1_T 0x0644 /* Dword offset 1_AC */
543#define VERTEX_1_W 0x0648 /* Dword offset 1_AD */
544#define VERTEX_2_S 0x0660 /* Dword offset 1_AE */
545#define VERTEX_2_T 0x0664 /* Dword offset 1_AF */
546#define VERTEX_2_W 0x0668 /* Dword offset 1_B0 */
547#define VERTEX_3_SECONDARY_S 0x06C0 /* Dword offset 1_B0 */
548#define VERTEX_3_S 0x0680 /* Dword offset 1_B1 */
549#define VERTEX_3_SECONDARY_T 0x06C4 /* Dword offset 1_B1 */
550#define VERTEX_3_T 0x0684 /* Dword offset 1_B2 */
551#define VERTEX_3_SECONDARY_W 0x06C8 /* Dword offset 1_B2 */
552#define VERTEX_3_W 0x0688 /* Dword offset 1_B3 */
553#define VERTEX_1_SPEC_ARGB 0x064C /* Dword offset 1_B4 */
554#define VERTEX_2_SPEC_ARGB 0x066C /* Dword offset 1_B5 */
555#define VERTEX_3_SPEC_ARGB 0x068C /* Dword offset 1_B6 */
556#define VERTEX_1_Z 0x0650 /* Dword offset 1_B7 */
557#define VERTEX_2_Z 0x0670 /* Dword offset 1_B8 */
558#define VERTEX_3_Z 0x0690 /* Dword offset 1_B9 */
559#define VERTEX_1_ARGB 0x0654 /* Dword offset 1_BA */
560#define VERTEX_2_ARGB 0x0674 /* Dword offset 1_BB */
561#define VERTEX_3_ARGB 0x0694 /* Dword offset 1_BC */
562#define VERTEX_1_X_Y 0x0658 /* Dword offset 1_BD */
563#define VERTEX_2_X_Y 0x0678 /* Dword offset 1_BE */
564#define VERTEX_3_X_Y 0x0698 /* Dword offset 1_BF */
565#define ONE_OVER_AREA_UC 0x0700 /* Dword offset 1_C0 */
566#define SETUP_CNTL 0x0704 /* Dword offset 1_C1 */
567#define VERTEX_1_SECONDARY_S 0x0728 /* Dword offset 1_CA */
568#define VERTEX_1_SECONDARY_T 0x072C /* Dword offset 1_CB */
569#define VERTEX_1_SECONDARY_W 0x0730 /* Dword offset 1_CC */
570#define VERTEX_2_SECONDARY_S 0x0734 /* Dword offset 1_CD */
571#define VERTEX_2_SECONDARY_T 0x0738 /* Dword offset 1_CE */
572#define VERTEX_2_SECONDARY_W 0x073C /* Dword offset 1_CF */
573
574
575#define GTC_3D_RESET_DELAY 3 /* 3D engine reset delay in ms */
576
577/* CRTC control values (mostly CRTC_GEN_CNTL) */
578
579#define CRTC_H_SYNC_NEG 0x00200000
580#define CRTC_V_SYNC_NEG 0x00200000
581
582#define CRTC_DBL_SCAN_EN 0x00000001
583#define CRTC_INTERLACE_EN 0x00000002
584#define CRTC_HSYNC_DIS 0x00000004
585#define CRTC_VSYNC_DIS 0x00000008
586#define CRTC_CSYNC_EN 0x00000010
587#define CRTC_PIX_BY_2_EN 0x00000020 /* unused on RAGE */
588#define CRTC_DISPLAY_DIS 0x00000040
589#define CRTC_VGA_XOVERSCAN 0x00000080
590
591#define CRTC_PIX_WIDTH_MASK 0x00000700
592#define CRTC_PIX_WIDTH_4BPP 0x00000100
593#define CRTC_PIX_WIDTH_8BPP 0x00000200
594#define CRTC_PIX_WIDTH_15BPP 0x00000300
595#define CRTC_PIX_WIDTH_16BPP 0x00000400
596#define CRTC_PIX_WIDTH_24BPP 0x00000500
597#define CRTC_PIX_WIDTH_32BPP 0x00000600
598
599#define CRTC_BYTE_PIX_ORDER 0x00000800
600#define CRTC_PIX_ORDER_MSN_LSN 0x00000000
601#define CRTC_PIX_ORDER_LSN_MSN 0x00000800
602
603#define CRTC_VSYNC_INT_EN 0x00001000ul /* XC/XL */
604#define CRTC_VSYNC_INT 0x00002000ul /* XC/XL */
605#define CRTC_FIFO_OVERFILL 0x0000c000ul /* VT/GT */
606#define CRTC2_VSYNC_INT_EN 0x00004000ul /* XC/XL */
607#define CRTC2_VSYNC_INT 0x00008000ul /* XC/XL */
608
609#define CRTC_FIFO_LWM 0x000f0000
610#define CRTC_HVSYNC_IO_DRIVE 0x00010000 /* XC/XL */
611#define CRTC2_PIX_WIDTH 0x000e0000 /* LTPro */
612
613#define CRTC_VGA_128KAP_PAGING 0x00100000
614#define CRTC_VFC_SYNC_TRISTATE 0x00200000 /* VTB/GTB/LT */
615#define CRTC2_EN 0x00200000 /* LTPro */
616#define CRTC_LOCK_REGS 0x00400000
617#define CRTC_SYNC_TRISTATE 0x00800000
618
619#define CRTC_EXT_DISP_EN 0x01000000
620#define CRTC_EN 0x02000000
621#define CRTC_DISP_REQ_EN 0x04000000
622#define CRTC_VGA_LINEAR 0x08000000
623#define CRTC_VSYNC_FALL_EDGE 0x10000000
624#define CRTC_VGA_TEXT_132 0x20000000
625#define CRTC_CNT_EN 0x40000000
626#define CRTC_CUR_B_TEST 0x80000000
627
628#define CRTC_CRNT_VLINE 0x07f00000
629
630#define CRTC_PRESERVED_MASK 0x0001f000
631
632#define CRTC_VBLANK 0x00000001
633#define CRTC_VBLANK_INT_EN 0x00000002
634#define CRTC_VBLANK_INT 0x00000004
635#define CRTC_VBLANK_INT_AK CRTC_VBLANK_INT
636#define CRTC_VLINE_INT_EN 0x00000008
637#define CRTC_VLINE_INT 0x00000010
638#define CRTC_VLINE_INT_AK CRTC_VLINE_INT
639#define CRTC_VLINE_SYNC 0x00000020
640#define CRTC_FRAME 0x00000040
641#define SNAPSHOT_INT_EN 0x00000080
642#define SNAPSHOT_INT 0x00000100
643#define SNAPSHOT_INT_AK SNAPSHOT_INT
644#define I2C_INT_EN 0x00000200
645#define I2C_INT 0x00000400
646#define I2C_INT_AK I2C_INT
647#define CRTC2_VBLANK 0x00000800
648#define CRTC2_VBLANK_INT_EN 0x00001000
649#define CRTC2_VBLANK_INT 0x00002000
650#define CRTC2_VBLANK_INT_AK CRTC2_VBLANK_INT
651#define CRTC2_VLINE_INT_EN 0x00004000
652#define CRTC2_VLINE_INT 0x00008000
653#define CRTC2_VLINE_INT_AK CRTC2_VLINE_INT
654#define CAPBUF0_INT_EN 0x00010000
655#define CAPBUF0_INT 0x00020000
656#define CAPBUF0_INT_AK CAPBUF0_INT
657#define CAPBUF1_INT_EN 0x00040000
658#define CAPBUF1_INT 0x00080000
659#define CAPBUF1_INT_AK CAPBUF1_INT
660#define OVERLAY_EOF_INT_EN 0x00100000
661#define OVERLAY_EOF_INT 0x00200000
662#define OVERLAY_EOF_INT_AK OVERLAY_EOF_INT
663#define ONESHOT_CAP_INT_EN 0x00400000
664#define ONESHOT_CAP_INT 0x00800000
665#define ONESHOT_CAP_INT_AK ONESHOT_CAP_INT
666#define BUSMASTER_EOL_INT_EN 0x01000000
667#define BUSMASTER_EOL_INT 0x02000000
668#define BUSMASTER_EOL_INT_AK BUSMASTER_EOL_INT
669#define GP_INT_EN 0x04000000
670#define GP_INT 0x08000000
671#define GP_INT_AK GP_INT
672#define CRTC2_VLINE_SYNC 0x10000000
673#define SNAPSHOT2_INT_EN 0x20000000
674#define SNAPSHOT2_INT 0x40000000
675#define SNAPSHOT2_INT_AK SNAPSHOT2_INT
676#define VBLANK_BIT2_INT 0x80000000
677#define VBLANK_BIT2_INT_AK VBLANK_BIT2_INT
678
679#define CRTC_INT_EN_MASK (CRTC_VBLANK_INT_EN | \
680 CRTC_VLINE_INT_EN | \
681 SNAPSHOT_INT_EN | \
682 I2C_INT_EN | \
683 CRTC2_VBLANK_INT_EN | \
684 CRTC2_VLINE_INT_EN | \
685 CAPBUF0_INT_EN | \
686 CAPBUF1_INT_EN | \
687 OVERLAY_EOF_INT_EN | \
688 ONESHOT_CAP_INT_EN | \
689 BUSMASTER_EOL_INT_EN | \
690 GP_INT_EN | \
691 SNAPSHOT2_INT_EN)
692
693/* DAC control values */
694
695#define DAC_EXT_SEL_RS2 0x01
696#define DAC_EXT_SEL_RS3 0x02
697#define DAC_8BIT_EN 0x00000100
698#define DAC_PIX_DLY_MASK 0x00000600
699#define DAC_PIX_DLY_0NS 0x00000000
700#define DAC_PIX_DLY_2NS 0x00000200
701#define DAC_PIX_DLY_4NS 0x00000400
702#define DAC_BLANK_ADJ_MASK 0x00001800
703#define DAC_BLANK_ADJ_0 0x00000000
704#define DAC_BLANK_ADJ_1 0x00000800
705#define DAC_BLANK_ADJ_2 0x00001000
706
707/* DAC control values (my source XL/XC Register reference) */
708#define DAC_OUTPUT_MASK 0x00000001 /* 0 - PAL, 1 - NTSC */
709#define DAC_MISTERY_BIT 0x00000002 /* PS2 ? RS343 ?, EXTRA_BRIGHT for GT */
710#define DAC_BLANKING 0x00000004
711#define DAC_CMP_DISABLE 0x00000008
712#define DAC1_CLK_SEL 0x00000010
713#define PALETTE_ACCESS_CNTL 0x00000020
714#define PALETTE2_SNOOP_EN 0x00000040
715#define DAC_CMP_OUTPUT 0x00000080 /* read only */
716/* #define DAC_8BIT_EN is ok */
717#define CRT_SENSE 0x00000800 /* read only */
718#define CRT_DETECTION_ON 0x00001000
719#define DAC_VGA_ADR_EN 0x00002000
720#define DAC_FEA_CON_EN 0x00004000
721#define DAC_PDWN 0x00008000
722#define DAC_TYPE_MASK 0x00070000 /* read only */
723
724
725
726/* Mix control values */
727
728#define MIX_NOT_DST 0x0000
729#define MIX_0 0x0001
730#define MIX_1 0x0002
731#define MIX_DST 0x0003
732#define MIX_NOT_SRC 0x0004
733#define MIX_XOR 0x0005
734#define MIX_XNOR 0x0006
735#define MIX_SRC 0x0007
736#define MIX_NAND 0x0008
737#define MIX_NOT_SRC_OR_DST 0x0009
738#define MIX_SRC_OR_NOT_DST 0x000a
739#define MIX_OR 0x000b
740#define MIX_AND 0x000c
741#define MIX_SRC_AND_NOT_DST 0x000d
742#define MIX_NOT_SRC_AND_DST 0x000e
743#define MIX_NOR 0x000f
744
745/* Maximum engine dimensions */
746#define ENGINE_MIN_X 0
747#define ENGINE_MIN_Y 0
748#define ENGINE_MAX_X 4095
749#define ENGINE_MAX_Y 16383
750
751/* Mach64 engine bit constants - these are typically ORed together */
752
753/* BUS_CNTL register constants */
754#define BUS_APER_REG_DIS 0x00000010
755#define BUS_FIFO_ERR_ACK 0x00200000
756#define BUS_HOST_ERR_ACK 0x00800000
757
758/* GEN_TEST_CNTL register constants */
759#define GEN_OVR_OUTPUT_EN 0x20
760#define HWCURSOR_ENABLE 0x80
761#define GUI_ENGINE_ENABLE 0x100
762#define BLOCK_WRITE_ENABLE 0x200
763
764/* DSP_CONFIG register constants */
765#define DSP_XCLKS_PER_QW 0x00003fff
766#define DSP_LOOP_LATENCY 0x000f0000
767#define DSP_PRECISION 0x00700000
768
769/* DSP_ON_OFF register constants */
770#define DSP_OFF 0x000007ff
771#define DSP_ON 0x07ff0000
772#define VGA_DSP_OFF DSP_OFF
773#define VGA_DSP_ON DSP_ON
774#define VGA_DSP_XCLKS_PER_QW DSP_XCLKS_PER_QW
775
776/* PLL register indices and fields */
777#define MPLL_CNTL 0x00
778#define PLL_PC_GAIN 0x07
779#define PLL_VC_GAIN 0x18
780#define PLL_DUTY_CYC 0xE0
781#define VPLL_CNTL 0x01
782#define PLL_REF_DIV 0x02
783#define PLL_GEN_CNTL 0x03
784#define PLL_OVERRIDE 0x01 /* PLL_SLEEP */
785#define PLL_MCLK_RST 0x02 /* PLL_MRESET */
786#define OSC_EN 0x04
787#define EXT_CLK_EN 0x08
788#define FORCE_DCLK_TRI_STATE 0x08 /* VT4 -> */
789#define MCLK_SRC_SEL 0x70
790#define EXT_CLK_CNTL 0x80
791#define DLL_PWDN 0x80 /* VT4 -> */
792#define MCLK_FB_DIV 0x04
793#define PLL_VCLK_CNTL 0x05
794#define PLL_VCLK_SRC_SEL 0x03
795#define PLL_VCLK_RST 0x04
796#define PLL_VCLK_INVERT 0x08
797#define VCLK_POST_DIV 0x06
798#define VCLK0_POST 0x03
799#define VCLK1_POST 0x0C
800#define VCLK2_POST 0x30
801#define VCLK3_POST 0xC0
802#define VCLK0_FB_DIV 0x07
803#define VCLK1_FB_DIV 0x08
804#define VCLK2_FB_DIV 0x09
805#define VCLK3_FB_DIV 0x0A
806#define PLL_EXT_CNTL 0x0B
807#define PLL_XCLK_MCLK_RATIO 0x03
808#define PLL_XCLK_SRC_SEL 0x07
809#define PLL_MFB_TIMES_4_2B 0x08
810#define PLL_VCLK0_XDIV 0x10
811#define PLL_VCLK1_XDIV 0x20
812#define PLL_VCLK2_XDIV 0x40
813#define PLL_VCLK3_XDIV 0x80
814#define DLL_CNTL 0x0C
815#define DLL1_CNTL 0x0C
816#define VFC_CNTL 0x0D
817#define PLL_TEST_CNTL 0x0E
818#define PLL_TEST_COUNT 0x0F
819#define LVDS_CNTL0 0x10
820#define LVDS_CNTL1 0x11
821#define AGP1_CNTL 0x12
822#define AGP2_CNTL 0x13
823#define DLL2_CNTL 0x14
824#define SCLK_FB_DIV 0x15
825#define SPLL_CNTL1 0x16
826#define SPLL_CNTL2 0x17
827#define APLL_STRAPS 0x18
828#define EXT_VPLL_CNTL 0x19
829#define EXT_VPLL_EN 0x04
830#define EXT_VPLL_VGA_EN 0x08
831#define EXT_VPLL_INSYNC 0x10
832#define EXT_VPLL_REF_DIV 0x1A
833#define EXT_VPLL_FB_DIV 0x1B
834#define EXT_VPLL_MSB 0x1C
835#define HTOTAL_CNTL 0x1D
836#define BYTE_CLK_CNTL 0x1E
837#define TV_PLL_CNTL1 0x1F
838#define TV_PLL_CNTL2 0x20
839#define TV_PLL_CNTL 0x21
840#define EXT_TV_PLL 0x22
841#define V2PLL_CNTL 0x23
842#define PLL_V2CLK_CNTL 0x24
843#define EXT_V2PLL_REF_DIV 0x25
844#define EXT_V2PLL_FB_DIV 0x26
845#define EXT_V2PLL_MSB 0x27
846#define HTOTAL2_CNTL 0x28
847#define PLL_YCLK_CNTL 0x29
848#define PM_DYN_CLK_CNTL 0x2A
849
850/* CNFG_CNTL register constants */
851#define APERTURE_4M_ENABLE 1
852#define APERTURE_8M_ENABLE 2
853#define VGA_APERTURE_ENABLE 4
854
855/* CNFG_STAT0 register constants (GX, CX) */
856#define CFG_BUS_TYPE 0x00000007
857#define CFG_MEM_TYPE 0x00000038
858#define CFG_INIT_DAC_TYPE 0x00000e00
859
860/* CNFG_STAT0 register constants (CT, ET, VT) */
861#define CFG_MEM_TYPE_xT 0x00000007
862
863#define ISA 0
864#define EISA 1
865#define LOCAL_BUS 6
866#define PCI 7
867
868/* Memory types for GX, CX */
869#define DRAMx4 0
870#define VRAMx16 1
871#define VRAMx16ssr 2
872#define DRAMx16 3
873#define GraphicsDRAMx16 4
874#define EnhancedVRAMx16 5
875#define EnhancedVRAMx16ssr 6
876
877/* Memory types for CT, ET, VT, GT */
878#define DRAM 1
879#define EDO 2
880#define PSEUDO_EDO 3
881#define SDRAM 4
882#define SGRAM 5
883#define WRAM 6
884#define SDRAM32 6
885
886#define DAC_INTERNAL 0x00
887#define DAC_IBMRGB514 0x01
888#define DAC_ATI68875 0x02
889#define DAC_TVP3026_A 0x72
890#define DAC_BT476 0x03
891#define DAC_BT481 0x04
892#define DAC_ATT20C491 0x14
893#define DAC_SC15026 0x24
894#define DAC_MU9C1880 0x34
895#define DAC_IMSG174 0x44
896#define DAC_ATI68860_B 0x05
897#define DAC_ATI68860_C 0x15
898#define DAC_TVP3026_B 0x75
899#define DAC_STG1700 0x06
900#define DAC_ATT498 0x16
901#define DAC_STG1702 0x07
902#define DAC_SC15021 0x17
903#define DAC_ATT21C498 0x27
904#define DAC_STG1703 0x37
905#define DAC_CH8398 0x47
906#define DAC_ATT20C408 0x57
907
908#define CLK_ATI18818_0 0
909#define CLK_ATI18818_1 1
910#define CLK_STG1703 2
911#define CLK_CH8398 3
912#define CLK_INTERNAL 4
913#define CLK_ATT20C408 5
914#define CLK_IBMRGB514 6
915
916/* MEM_CNTL register constants */
917#define MEM_SIZE_ALIAS 0x00000007
918#define MEM_SIZE_512K 0x00000000
919#define MEM_SIZE_1M 0x00000001
920#define MEM_SIZE_2M 0x00000002
921#define MEM_SIZE_4M 0x00000003
922#define MEM_SIZE_6M 0x00000004
923#define MEM_SIZE_8M 0x00000005
924#define MEM_SIZE_ALIAS_GTB 0x0000000F
925#define MEM_SIZE_2M_GTB 0x00000003
926#define MEM_SIZE_4M_GTB 0x00000007
927#define MEM_SIZE_6M_GTB 0x00000009
928#define MEM_SIZE_8M_GTB 0x0000000B
929#define MEM_BNDRY 0x00030000
930#define MEM_BNDRY_0K 0x00000000
931#define MEM_BNDRY_256K 0x00010000
932#define MEM_BNDRY_512K 0x00020000
933#define MEM_BNDRY_1M 0x00030000
934#define MEM_BNDRY_EN 0x00040000
935
936#define ONE_MB 0x100000
937
938/* CNFG_CHIP_ID register constants */
939#define CFG_CHIP_TYPE 0x0000FFFF
940#define CFG_CHIP_CLASS 0x00FF0000
941#define CFG_CHIP_REV 0xFF000000
942#define CFG_CHIP_MAJOR 0x07000000
943#define CFG_CHIP_FND_ID 0x38000000
944#define CFG_CHIP_MINOR 0xC0000000
945
946
947/* Chip IDs read from CNFG_CHIP_ID */
948
949/* mach64GX family */
950#define GX_CHIP_ID 0xD7 /* mach64GX (ATI888GX00) */
951#define CX_CHIP_ID 0x57 /* mach64CX (ATI888CX00) */
952
953#define GX_PCI_ID 0x4758 /* mach64GX (ATI888GX00) */
954#define CX_PCI_ID 0x4358 /* mach64CX (ATI888CX00) */
955
956/* mach64CT family */
957#define CT_CHIP_ID 0x4354 /* mach64CT (ATI264CT) */
958#define ET_CHIP_ID 0x4554 /* mach64ET (ATI264ET) */
959
960/* mach64CT family / mach64VT class */
961#define VT_CHIP_ID 0x5654 /* mach64VT (ATI264VT) */
962#define VU_CHIP_ID 0x5655 /* mach64VTB (ATI264VTB) */
963#define VV_CHIP_ID 0x5656 /* mach64VT4 (ATI264VT4) */
964
965/* mach64CT family / mach64GT (3D RAGE) class */
966#define LB_CHIP_ID 0x4c42 /* RAGE LT PRO, AGP */
967#define LD_CHIP_ID 0x4c44 /* RAGE LT PRO */
968#define LG_CHIP_ID 0x4c47 /* RAGE LT */
969#define LI_CHIP_ID 0x4c49 /* RAGE LT PRO */
970#define LP_CHIP_ID 0x4c50 /* RAGE LT PRO */
971#define LT_CHIP_ID 0x4c54 /* RAGE LT */
972
973/* mach64CT family / (Rage XL) class */
974#define GR_CHIP_ID 0x4752 /* RAGE XL, BGA, PCI33 */
975#define GS_CHIP_ID 0x4753 /* RAGE XL, PQFP, PCI33 */
976#define GM_CHIP_ID 0x474d /* RAGE XL, BGA, AGP 1x,2x */
977#define GN_CHIP_ID 0x474e /* RAGE XL, PQFP,AGP 1x,2x */
978#define GO_CHIP_ID 0x474f /* RAGE XL, BGA, PCI66 */
979#define GL_CHIP_ID 0x474c /* RAGE XL, PQFP, PCI66 */
980
981#define IS_XL(id) ((id)==GR_CHIP_ID || (id)==GS_CHIP_ID || \
982 (id)==GM_CHIP_ID || (id)==GN_CHIP_ID || \
983 (id)==GO_CHIP_ID || (id)==GL_CHIP_ID)
984
985#define GT_CHIP_ID 0x4754 /* RAGE (GT) */
986#define GU_CHIP_ID 0x4755 /* RAGE II/II+ (GTB) */
987#define GV_CHIP_ID 0x4756 /* RAGE IIC, PCI */
988#define GW_CHIP_ID 0x4757 /* RAGE IIC, AGP */
989#define GZ_CHIP_ID 0x475a /* RAGE IIC, AGP */
990#define GB_CHIP_ID 0x4742 /* RAGE PRO, BGA, AGP 1x and 2x */
991#define GD_CHIP_ID 0x4744 /* RAGE PRO, BGA, AGP 1x only */
992#define GI_CHIP_ID 0x4749 /* RAGE PRO, BGA, PCI33 only */
993#define GP_CHIP_ID 0x4750 /* RAGE PRO, PQFP, PCI33, full 3D */
994#define GQ_CHIP_ID 0x4751 /* RAGE PRO, PQFP, PCI33, limited 3D */
995
996#define LM_CHIP_ID 0x4c4d /* RAGE Mobility AGP, full function */
997#define LN_CHIP_ID 0x4c4e /* RAGE Mobility AGP */
998#define LR_CHIP_ID 0x4c52 /* RAGE Mobility PCI, full function */
999#define LS_CHIP_ID 0x4c53 /* RAGE Mobility PCI */
1000
1001#define IS_MOBILITY(id) ((id)==LM_CHIP_ID || (id)==LN_CHIP_ID || \
1002 (id)==LR_CHIP_ID || (id)==LS_CHIP_ID)
1003/* Mach64 major ASIC revisions */
1004#define MACH64_ASIC_NEC_VT_A3 0x08
1005#define MACH64_ASIC_NEC_VT_A4 0x48
1006#define MACH64_ASIC_SGS_VT_A4 0x40
1007#define MACH64_ASIC_SGS_VT_B1S1 0x01
1008#define MACH64_ASIC_SGS_GT_B1S1 0x01
1009#define MACH64_ASIC_SGS_GT_B1S2 0x41
1010#define MACH64_ASIC_UMC_GT_B2U1 0x1a
1011#define MACH64_ASIC_UMC_GT_B2U2 0x5a
1012#define MACH64_ASIC_UMC_VT_B2U3 0x9a
1013#define MACH64_ASIC_UMC_GT_B2U3 0x9a
1014#define MACH64_ASIC_UMC_R3B_D_P_A1 0x1b
1015#define MACH64_ASIC_UMC_R3B_D_P_A2 0x5b
1016#define MACH64_ASIC_UMC_R3B_D_P_A3 0x1c
1017#define MACH64_ASIC_UMC_R3B_D_P_A4 0x5c
1018
1019/* Mach64 foundries */
1020#define MACH64_FND_SGS 0
1021#define MACH64_FND_NEC 1
1022#define MACH64_FND_UMC 3
1023
1024/* Mach64 chip types */
1025#define MACH64_UNKNOWN 0
1026#define MACH64_GX 1
1027#define MACH64_CX 2
1028#define MACH64_CT 3Restore
1029#define MACH64_ET 4
1030#define MACH64_VT 5
1031#define MACH64_GT 6
1032
1033/* DST_CNTL register constants */
1034#define DST_X_RIGHT_TO_LEFT 0
1035#define DST_X_LEFT_TO_RIGHT 1
1036#define DST_Y_BOTTOM_TO_TOP 0
1037#define DST_Y_TOP_TO_BOTTOM 2
1038#define DST_X_MAJOR 0
1039#define DST_Y_MAJOR 4
1040#define DST_X_TILE 8
1041#define DST_Y_TILE 0x10
1042#define DST_LAST_PEL 0x20
1043#define DST_POLYGON_ENABLE 0x40
1044#define DST_24_ROTATION_ENABLE 0x80
1045
1046/* SRC_CNTL register constants */
1047#define SRC_PATTERN_ENABLE 1
1048#define SRC_ROTATION_ENABLE 2
1049#define SRC_LINEAR_ENABLE 4
1050#define SRC_BYTE_ALIGN 8
1051#define SRC_LINE_X_RIGHT_TO_LEFT 0
1052#define SRC_LINE_X_LEFT_TO_RIGHT 0x10
1053
1054/* HOST_CNTL register constants */
1055#define HOST_BYTE_ALIGN 1
1056
1057/* GUI_TRAJ_CNTL register constants */
1058#define PAT_MONO_8x8_ENABLE 0x01000000
1059#define PAT_CLR_4x2_ENABLE 0x02000000
1060#define PAT_CLR_8x1_ENABLE 0x04000000
1061
1062/* DP_CHAIN_MASK register constants */
1063#define DP_CHAIN_4BPP 0x8888
1064#define DP_CHAIN_7BPP 0xD2D2
1065#define DP_CHAIN_8BPP 0x8080
1066#define DP_CHAIN_8BPP_RGB 0x9292
1067#define DP_CHAIN_15BPP 0x4210
1068#define DP_CHAIN_16BPP 0x8410
1069#define DP_CHAIN_24BPP 0x8080
1070#define DP_CHAIN_32BPP 0x8080
1071
1072/* DP_PIX_WIDTH register constants */
1073#define DST_1BPP 0x0
1074#define DST_4BPP 0x1
1075#define DST_8BPP 0x2
1076#define DST_15BPP 0x3
1077#define DST_16BPP 0x4
1078#define DST_24BPP 0x5
1079#define DST_32BPP 0x6
1080#define DST_MASK 0xF
1081#define SRC_1BPP 0x000
1082#define SRC_4BPP 0x100
1083#define SRC_8BPP 0x200
1084#define SRC_15BPP 0x300
1085#define SRC_16BPP 0x400
1086#define SRC_24BPP 0x500
1087#define SRC_32BPP 0x600
1088#define SRC_MASK 0xF00
1089#define DP_HOST_TRIPLE_EN 0x2000
1090#define HOST_1BPP 0x00000
1091#define HOST_4BPP 0x10000
1092#define HOST_8BPP 0x20000
1093#define HOST_15BPP 0x30000
1094#define HOST_16BPP 0x40000
1095#define HOST_24BPP 0x50000
1096#define HOST_32BPP 0x60000
1097#define HOST_MASK 0xF0000
1098#define BYTE_ORDER_MSB_TO_LSB 0
1099#define BYTE_ORDER_LSB_TO_MSB 0x1000000
1100#define BYTE_ORDER_MASK 0x1000000
1101
1102/* DP_MIX register constants */
1103#define BKGD_MIX_NOT_D 0
1104#define BKGD_MIX_ZERO 1
1105#define BKGD_MIX_ONE 2
1106#define BKGD_MIX_D 3
1107#define BKGD_MIX_NOT_S 4
1108#define BKGD_MIX_D_XOR_S 5
1109#define BKGD_MIX_NOT_D_XOR_S 6
1110#define BKGD_MIX_S 7
1111#define BKGD_MIX_NOT_D_OR_NOT_S 8
1112#define BKGD_MIX_D_OR_NOT_S 9
1113#define BKGD_MIX_NOT_D_OR_S 10
1114#define BKGD_MIX_D_OR_S 11
1115#define BKGD_MIX_D_AND_S 12
1116#define BKGD_MIX_NOT_D_AND_S 13
1117#define BKGD_MIX_D_AND_NOT_S 14
1118#define BKGD_MIX_NOT_D_AND_NOT_S 15
1119#define BKGD_MIX_D_PLUS_S_DIV2 0x17
1120#define FRGD_MIX_NOT_D 0
1121#define FRGD_MIX_ZERO 0x10000
1122#define FRGD_MIX_ONE 0x20000
1123#define FRGD_MIX_D 0x30000
1124#define FRGD_MIX_NOT_S 0x40000
1125#define FRGD_MIX_D_XOR_S 0x50000
1126#define FRGD_MIX_NOT_D_XOR_S 0x60000
1127#define FRGD_MIX_S 0x70000
1128#define FRGD_MIX_NOT_D_OR_NOT_S 0x80000
1129#define FRGD_MIX_D_OR_NOT_S 0x90000
1130#define FRGD_MIX_NOT_D_OR_S 0xa0000
1131#define FRGD_MIX_D_OR_S 0xb0000
1132#define FRGD_MIX_D_AND_S 0xc0000
1133#define FRGD_MIX_NOT_D_AND_S 0xd0000
1134#define FRGD_MIX_D_AND_NOT_S 0xe0000
1135#define FRGD_MIX_NOT_D_AND_NOT_S 0xf0000
1136#define FRGD_MIX_D_PLUS_S_DIV2 0x170000
1137
1138/* DP_SRC register constants */
1139#define BKGD_SRC_BKGD_CLR 0
1140#define BKGD_SRC_FRGD_CLR 1
1141#define BKGD_SRC_HOST 2
1142#define BKGD_SRC_BLIT 3
1143#define BKGD_SRC_PATTERN 4
1144#define FRGD_SRC_BKGD_CLR 0
1145#define FRGD_SRC_FRGD_CLR 0x100
1146#define FRGD_SRC_HOST 0x200
1147#define FRGD_SRC_BLIT 0x300
1148#define FRGD_SRC_PATTERN 0x400
1149#define MONO_SRC_ONE 0
1150#define MONO_SRC_PATTERN 0x10000
1151#define MONO_SRC_HOST 0x20000
1152#define MONO_SRC_BLIT 0x30000
1153
1154/* CLR_CMP_CNTL register constants */
1155#define COMPARE_FALSE 0
1156#define COMPARE_TRUE 1
1157#define COMPARE_NOT_EQUAL 4
1158#define COMPARE_EQUAL 5
1159#define COMPARE_DESTINATION 0
1160#define COMPARE_SOURCE 0x1000000
1161
1162/* FIFO_STAT register constants */
1163#define FIFO_ERR 0x80000000
1164
1165/* CONTEXT_LOAD_CNTL constants */
1166#define CONTEXT_NO_LOAD 0
1167#define CONTEXT_LOAD 0x10000
1168#define CONTEXT_LOAD_AND_DO_FILL 0x20000
1169#define CONTEXT_LOAD_AND_DO_LINE 0x30000
1170#define CONTEXT_EXECUTE 0
1171#define CONTEXT_CMD_DISABLE 0x80000000
1172
1173/* GUI_STAT register constants */
1174#define ENGINE_IDLE 0
1175#define ENGINE_BUSY 1
1176#define SCISSOR_LEFT_FLAG 0x10
1177#define SCISSOR_RIGHT_FLAG 0x20
1178#define SCISSOR_TOP_FLAG 0x40
1179#define SCISSOR_BOTTOM_FLAG 0x80
1180
1181/* ATI VGA Extended Regsiters */
1182#define sioATIEXT 0x1ce
1183#define bioATIEXT 0x3ce
1184
1185#define ATI2E 0xae
1186#define ATI32 0xb2
1187#define ATI36 0xb6
1188
1189/* VGA Graphics Controller Registers */
1190#define R_GENMO 0x3cc
1191#define VGAGRA 0x3ce
1192#define GRA06 0x06
1193
1194/* VGA Seququencer Registers */
1195#define VGASEQ 0x3c4
1196#define SEQ02 0x02
1197#define SEQ04 0x04
1198
1199#define MACH64_MAX_X ENGINE_MAX_X
1200#define MACH64_MAX_Y ENGINE_MAX_Y
1201
1202#define INC_X 0x0020
1203#define INC_Y 0x0080
1204
1205#define RGB16_555 0x0000
1206#define RGB16_565 0x0040
1207#define RGB16_655 0x0080
1208#define RGB16_664 0x00c0
1209
1210#define POLY_TEXT_TYPE 0x0001
1211#define IMAGE_TEXT_TYPE 0x0002
1212#define TEXT_TYPE_8_BIT 0x0004
1213#define TEXT_TYPE_16_BIT 0x0008
1214#define POLY_TEXT_TYPE_8 (POLY_TEXT_TYPE | TEXT_TYPE_8_BIT)
1215#define IMAGE_TEXT_TYPE_8 (IMAGE_TEXT_TYPE | TEXT_TYPE_8_BIT)
1216#define POLY_TEXT_TYPE_16 (POLY_TEXT_TYPE | TEXT_TYPE_16_BIT)
1217#define IMAGE_TEXT_TYPE_16 (IMAGE_TEXT_TYPE | TEXT_TYPE_16_BIT)
1218
1219#define MACH64_NUM_CLOCKS 16
1220#define MACH64_NUM_FREQS 50
1221
1222/* Power Management register constants (LT & LT Pro) */
1223#define PWR_MGT_ON 0x00000001
1224#define PWR_MGT_MODE_MASK 0x00000006
1225#define AUTO_PWR_UP 0x00000008
1226#define USE_F32KHZ 0x00000400
1227#define TRISTATE_MEM_EN 0x00000800
1228#define SELF_REFRESH 0x00000080
1229#define PWR_BLON 0x02000000
1230#define STANDBY_NOW 0x10000000
1231#define SUSPEND_NOW 0x20000000
1232#define PWR_MGT_STATUS_MASK 0xC0000000
1233#define PWR_MGT_STATUS_SUSPEND 0x80000000
1234
1235/* PM Mode constants */
1236#define PWR_MGT_MODE_PIN 0x00000000
1237#define PWR_MGT_MODE_REG 0x00000002
1238#define PWR_MGT_MODE_TIMER 0x00000004
1239#define PWR_MGT_MODE_PCI 0x00000006
1240
1241/* LCD registers (LT Pro) */
1242
1243/* LCD Index register */
1244#define LCD_INDEX_MASK 0x0000003F
1245#define LCD_DISPLAY_DIS 0x00000100
1246#define LCD_SRC_SEL 0x00000200
1247#define CRTC2_DISPLAY_DIS 0x00000400
1248
1249/* LCD register indices */
1250#define CNFG_PANEL 0x00
1251#define LCD_GEN_CNTL 0x01
1252#define DSTN_CONTROL 0x02
1253#define HFB_PITCH_ADDR 0x03
1254#define HORZ_STRETCHING 0x04
1255#define VERT_STRETCHING 0x05
1256#define EXT_VERT_STRETCH 0x06
1257#define LT_GIO 0x07
1258#define POWER_MANAGEMENT 0x08
1259#define ZVGPIO 0x09
1260#define ICON_CLR0 0x0A
1261#define ICON_CLR1 0x0B
1262#define ICON_OFFSET 0x0C
1263#define ICON_HORZ_VERT_POSN 0x0D
1264#define ICON_HORZ_VERT_OFF 0x0E
1265#define ICON2_CLR0 0x0F
1266#define ICON2_CLR1 0x10
1267#define ICON2_OFFSET 0x11
1268#define ICON2_HORZ_VERT_POSN 0x12
1269#define ICON2_HORZ_VERT_OFF 0x13
1270#define LCD_MISC_CNTL 0x14
1271#define APC_CNTL 0x1C
1272#define POWER_MANAGEMENT_2 0x1D
1273#define ALPHA_BLENDING 0x25
1274#define PORTRAIT_GEN_CNTL 0x26
1275#define APC_CTRL_IO 0x27
1276#define TEST_IO 0x28
1277#define TEST_OUTPUTS 0x29
1278#define DP1_MEM_ACCESS 0x2A
1279#define DP0_MEM_ACCESS 0x2B
1280#define DP0_DEBUG_A 0x2C
1281#define DP0_DEBUG_B 0x2D
1282#define DP1_DEBUG_A 0x2E
1283#define DP1_DEBUG_B 0x2F
1284#define DPCTRL_DEBUG_A 0x30
1285#define DPCTRL_DEBUG_B 0x31
1286#define MEMBLK_DEBUG 0x32
1287#define APC_LUT_AB 0x33
1288#define APC_LUT_CD 0x34
1289#define APC_LUT_EF 0x35
1290#define APC_LUT_GH 0x36
1291#define APC_LUT_IJ 0x37
1292#define APC_LUT_KL 0x38
1293#define APC_LUT_MN 0x39
1294#define APC_LUT_OP 0x3A
1295
1296/* Values in LCD_GEN_CTRL */
1297#define CRT_ON 0x00000001ul
1298#define LCD_ON 0x00000002ul
1299#define HORZ_DIVBY2_EN 0x00000004ul
1300#define DONT_DS_ICON 0x00000008ul
1301#define LOCK_8DOT 0x00000010ul
1302#define ICON_ENABLE 0x00000020ul
1303#define DONT_SHADOW_VPAR 0x00000040ul
1304#define V2CLK_PM_EN 0x00000080ul
1305#define RST_FM 0x00000100ul
1306#define DISABLE_PCLK_RESET 0x00000200ul /* XC/XL */
1307#define DIS_HOR_CRT_DIVBY2 0x00000400ul
1308#define SCLK_SEL 0x00000800ul
1309#define SCLK_DELAY 0x0000f000ul
1310#define TVCLK_PM_EN 0x00010000ul
1311#define VCLK_DAC_PM_EN 0x00020000ul
1312#define VCLK_LCD_OFF 0x00040000ul
1313#define SELECT_WAIT_4MS 0x00080000ul
1314#define XTALIN_PM_EN 0x00080000ul /* XC/XL */
1315#define V2CLK_DAC_PM_EN 0x00100000ul
1316#define LVDS_EN 0x00200000ul
1317#define LVDS_PLL_EN 0x00400000ul
1318#define LVDS_PLL_RESET 0x00800000ul
1319#define LVDS_RESERVED_BITS 0x07000000ul
1320#define CRTC_RW_SELECT 0x08000000ul /* LTPro */
1321#define USE_SHADOWED_VEND 0x10000000ul
1322#define USE_SHADOWED_ROWCUR 0x20000000ul
1323#define SHADOW_EN 0x40000000ul
1324#define SHADOW_RW_EN 0x80000000ul
1325
1326#define LCD_SET_PRIMARY_MASK 0x07FFFBFBul
1327
1328/* Values in HORZ_STRETCHING */
1329#define HORZ_STRETCH_BLEND 0x00000ffful
1330#define HORZ_STRETCH_RATIO 0x0000fffful
1331#define HORZ_STRETCH_LOOP 0x00070000ul
1332#define HORZ_STRETCH_LOOP09 0x00000000ul
1333#define HORZ_STRETCH_LOOP11 0x00010000ul
1334#define HORZ_STRETCH_LOOP12 0x00020000ul
1335#define HORZ_STRETCH_LOOP14 0x00030000ul
1336#define HORZ_STRETCH_LOOP15 0x00040000ul
1337/* ? 0x00050000ul */
1338/* ? 0x00060000ul */
1339/* ? 0x00070000ul */
1340/* ? 0x00080000ul */
1341#define HORZ_PANEL_SIZE 0x0ff00000ul /* XC/XL */
1342/* ? 0x10000000ul */
1343#define AUTO_HORZ_RATIO 0x20000000ul /* XC/XL */
1344#define HORZ_STRETCH_MODE 0x40000000ul
1345#define HORZ_STRETCH_EN 0x80000000ul
1346
1347/* Values in VERT_STRETCHING */
1348#define VERT_STRETCH_RATIO0 0x000003fful
1349#define VERT_STRETCH_RATIO1 0x000ffc00ul
1350#define VERT_STRETCH_RATIO2 0x3ff00000ul
1351#define VERT_STRETCH_USE0 0x40000000ul
1352#define VERT_STRETCH_EN 0x80000000ul
1353
1354/* Values in EXT_VERT_STRETCH */
1355#define VERT_STRETCH_RATIO3 0x000003fful
1356#define FORCE_DAC_DATA 0x000000fful
1357#define FORCE_DAC_DATA_SEL 0x00000300ul
1358#define VERT_STRETCH_MODE 0x00000400ul
1359#define VERT_PANEL_SIZE 0x003ff800ul
1360#define AUTO_VERT_RATIO 0x00400000ul
1361#define USE_AUTO_FP_POS 0x00800000ul
1362#define USE_AUTO_LCD_VSYNC 0x01000000ul
1363/* ? 0xfe000000ul */
1364
1365/* Values in LCD_MISC_CNTL */
1366#define BIAS_MOD_LEVEL_MASK 0x0000ff00
1367#define BIAS_MOD_LEVEL_SHIFT 8
1368#define BLMOD_EN 0x00010000
1369#define BIASMOD_EN 0x00020000
1370
1371#endif /* REGMACH64_H */