| 1 |
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| 2 | |
| 3 | * xen.h
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| 4 | *
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| 5 | * Guest OS interface to Xen.
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| 6 | *
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| 7 | * Copyright (c) 2004, K A Fraser
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| 8 |
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| 9 |
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| 10 | #ifndef __XEN_PUBLIC_XEN_H__
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| 11 | #define __XEN_PUBLIC_XEN_H__
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| 12 |
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| 13 | #include <asm/xen/interface.h>
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| 14 |
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| 15 | |
| 16 | * XEN "SYSTEM CALLS" (a.k.a. HYPERCALLS).
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| 17 |
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| 18 |
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| 19 | |
| 20 | * x86_32: EAX = vector; EBX, ECX, EDX, ESI, EDI = args 1, 2, 3, 4, 5.
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| 21 | * EAX = return value
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| 22 | * (argument registers may be clobbered on return)
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| 23 | * x86_64: RAX = vector; RDI, RSI, RDX, R10, R8, R9 = args 1, 2, 3, 4, 5, 6.
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| 24 | * RAX = return value
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| 25 | * (argument registers not clobbered on return; RCX, R11 are)
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| 26 |
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| 27 | #define __HYPERVISOR_set_trap_table 0
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| 28 | #define __HYPERVISOR_mmu_update 1
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| 29 | #define __HYPERVISOR_set_gdt 2
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| 30 | #define __HYPERVISOR_stack_switch 3
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| 31 | #define __HYPERVISOR_set_callbacks 4
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| 32 | #define __HYPERVISOR_fpu_taskswitch 5
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| 33 | #define __HYPERVISOR_sched_op_compat 6
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| 34 | #define __HYPERVISOR_platform_op 7
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| 35 | #define __HYPERVISOR_set_debugreg 8
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| 36 | #define __HYPERVISOR_get_debugreg 9
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| 37 | #define __HYPERVISOR_update_descriptor 10
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| 38 | #define __HYPERVISOR_memory_op 12
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| 39 | #define __HYPERVISOR_multicall 13
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| 40 | #define __HYPERVISOR_update_va_mapping 14
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| 41 | #define __HYPERVISOR_set_timer_op 15
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| 42 | #define __HYPERVISOR_event_channel_op_compat 16
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| 43 | #define __HYPERVISOR_xen_version 17
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| 44 | #define __HYPERVISOR_console_io 18
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| 45 | #define __HYPERVISOR_physdev_op_compat 19
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| 46 | #define __HYPERVISOR_grant_table_op 20
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| 47 | #define __HYPERVISOR_vm_assist 21
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| 48 | #define __HYPERVISOR_update_va_mapping_otherdomain 22
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| 49 | #define __HYPERVISOR_iret 23
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| 50 | #define __HYPERVISOR_vcpu_op 24
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| 51 | #define __HYPERVISOR_set_segment_base 25
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| 52 | #define __HYPERVISOR_mmuext_op 26
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| 53 | #define __HYPERVISOR_xsm_op 27
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| 54 | #define __HYPERVISOR_nmi_op 28
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| 55 | #define __HYPERVISOR_sched_op 29
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| 56 | #define __HYPERVISOR_callback_op 30
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| 57 | #define __HYPERVISOR_xenoprof_op 31
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| 58 | #define __HYPERVISOR_event_channel_op 32
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| 59 | #define __HYPERVISOR_physdev_op 33
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| 60 | #define __HYPERVISOR_hvm_op 34
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| 61 | #define __HYPERVISOR_sysctl 35
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| 62 | #define __HYPERVISOR_domctl 36
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| 63 | #define __HYPERVISOR_kexec_op 37
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| 64 | #define __HYPERVISOR_tmem_op 38
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| 65 | #define __HYPERVISOR_xc_reserved_op 39
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| 66 | #define __HYPERVISOR_xenpmu_op 40
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| 67 | #define __HYPERVISOR_dm_op 41
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| 68 |
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| 69 |
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| 70 | #define __HYPERVISOR_arch_0 48
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| 71 | #define __HYPERVISOR_arch_1 49
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| 72 | #define __HYPERVISOR_arch_2 50
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| 73 | #define __HYPERVISOR_arch_3 51
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| 74 | #define __HYPERVISOR_arch_4 52
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| 75 | #define __HYPERVISOR_arch_5 53
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| 76 | #define __HYPERVISOR_arch_6 54
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| 77 | #define __HYPERVISOR_arch_7 55
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| 78 |
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| 79 | |
| 80 | * VIRTUAL INTERRUPTS
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| 81 | *
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| 82 | * Virtual interrupts that a guest OS may receive from Xen.
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| 83 | * In the side comments, 'V.' denotes a per-VCPU VIRQ while 'G.' denotes a
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| 84 | * global VIRQ. The former can be bound once per VCPU and cannot be re-bound.
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| 85 | * The latter can be allocated only once per guest: they must initially be
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| 86 | * allocated to VCPU0 but can subsequently be re-bound.
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| 87 |
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| 88 | #define VIRQ_TIMER 0
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| 89 | #define VIRQ_DEBUG 1
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| 90 | #define VIRQ_CONSOLE 2
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| 91 | #define VIRQ_DOM_EXC 3
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| 92 | #define VIRQ_TBUF 4
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| 93 | #define VIRQ_DEBUGGER 6
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| 94 | #define VIRQ_XENOPROF 7
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| 95 | #define VIRQ_CON_RING 8
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| 96 | #define VIRQ_PCPU_STATE 9
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| 97 | #define VIRQ_MEM_EVENT 10
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| 98 | #define VIRQ_XC_RESERVED 11
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| 99 | #define VIRQ_ENOMEM 12
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| 100 | #define VIRQ_XENPMU 13
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| 101 |
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| 102 |
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| 103 | #define VIRQ_ARCH_0 16
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| 104 | #define VIRQ_ARCH_1 17
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| 105 | #define VIRQ_ARCH_2 18
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| 106 | #define VIRQ_ARCH_3 19
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| 107 | #define VIRQ_ARCH_4 20
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| 108 | #define VIRQ_ARCH_5 21
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| 109 | #define VIRQ_ARCH_6 22
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| 110 | #define VIRQ_ARCH_7 23
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| 111 |
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| 112 | #define NR_VIRQS 24
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| 113 |
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| 114 | |
| 115 | * enum neg_errnoval HYPERVISOR_mmu_update(const struct mmu_update reqs[],
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| 116 | * unsigned count, unsigned *done_out,
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| 117 | * unsigned foreigndom)
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| 118 | * @reqs is an array of mmu_update_t structures ((ptr, val) pairs).
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| 119 | * @count is the length of the above array.
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| 120 | * @pdone is an output parameter indicating number of completed operations
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| 121 | * @foreigndom[15:0]: FD, the expected owner of data pages referenced in this
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| 122 | * hypercall invocation. Can be DOMID_SELF.
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| 123 | * @foreigndom[31:16]: PFD, the expected owner of pagetable pages referenced
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| 124 | * in this hypercall invocation. The value of this field
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| 125 | * (x) encodes the PFD as follows:
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| 126 | * x == 0 => PFD == DOMID_SELF
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| 127 | * x != 0 => PFD == x - 1
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| 128 | *
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| 129 | * Sub-commands: ptr[1:0] specifies the appropriate MMU_* command.
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| 130 | * -------------
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| 131 | * ptr[1:0] == MMU_NORMAL_PT_UPDATE:
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| 132 | * Updates an entry in a page table belonging to PFD. If updating an L1 table,
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| 133 | * and the new table entry is valid/present, the mapped frame must belong to
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| 134 | * FD. If attempting to map an I/O page then the caller assumes the privilege
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| 135 | * of the FD.
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| 136 | * FD == DOMID_IO: Permit /only/ I/O mappings, at the priv level of the caller.
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| 137 | * FD == DOMID_XEN: Map restricted areas of Xen's heap space.
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| 138 | * ptr[:2] -- Machine address of the page-table entry to modify.
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| 139 | * val -- Value to write.
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| 140 | *
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| 141 | * There also certain implicit requirements when using this hypercall. The
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| 142 | * pages that make up a pagetable must be mapped read-only in the guest.
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| 143 | * This prevents uncontrolled guest updates to the pagetable. Xen strictly
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| 144 | * enforces this, and will disallow any pagetable update which will end up
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| 145 | * mapping pagetable page RW, and will disallow using any writable page as a
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| 146 | * pagetable. In practice it means that when constructing a page table for a
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| 147 | * process, thread, etc, we MUST be very dilligient in following these rules:
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| 148 | * 1). Start with top-level page (PGD or in Xen language: L4). Fill out
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| 149 | * the entries.
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| 150 | * 2). Keep on going, filling out the upper (PUD or L3), and middle (PMD
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| 151 | * or L2).
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| 152 | * 3). Start filling out the PTE table (L1) with the PTE entries. Once
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| 153 | * done, make sure to set each of those entries to RO (so writeable bit
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| 154 | * is unset). Once that has been completed, set the PMD (L2) for this
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| 155 | * PTE table as RO.
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| 156 | * 4). When completed with all of the PMD (L2) entries, and all of them have
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| 157 | * been set to RO, make sure to set RO the PUD (L3). Do the same
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| 158 | * operation on PGD (L4) pagetable entries that have a PUD (L3) entry.
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| 159 | * 5). Now before you can use those pages (so setting the cr3), you MUST also
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| 160 | * pin them so that the hypervisor can verify the entries. This is done
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| 161 | * via the HYPERVISOR_mmuext_op(MMUEXT_PIN_L4_TABLE, guest physical frame
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| 162 | * number of the PGD (L4)). And this point the HYPERVISOR_mmuext_op(
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| 163 | * MMUEXT_NEW_BASEPTR, guest physical frame number of the PGD (L4)) can be
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| 164 | * issued.
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| 165 | * For 32-bit guests, the L4 is not used (as there is less pagetables), so
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| 166 | * instead use L3.
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| 167 | * At this point the pagetables can be modified using the MMU_NORMAL_PT_UPDATE
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| 168 | * hypercall. Also if so desired the OS can also try to write to the PTE
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| 169 | * and be trapped by the hypervisor (as the PTE entry is RO).
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| 170 | *
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| 171 | * To deallocate the pages, the operations are the reverse of the steps
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| 172 | * mentioned above. The argument is MMUEXT_UNPIN_TABLE for all levels and the
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| 173 | * pagetable MUST not be in use (meaning that the cr3 is not set to it).
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| 174 | *
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| 175 | * ptr[1:0] == MMU_MACHPHYS_UPDATE:
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| 176 | * Updates an entry in the machine->pseudo-physical mapping table.
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| 177 | * ptr[:2] -- Machine address within the frame whose mapping to modify.
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| 178 | * The frame must belong to the FD, if one is specified.
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| 179 | * val -- Value to write into the mapping entry.
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| 180 | *
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| 181 | * ptr[1:0] == MMU_PT_UPDATE_PRESERVE_AD:
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| 182 | * As MMU_NORMAL_PT_UPDATE above, but A/D bits currently in the PTE are ORed
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| 183 | * with those in @val.
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| 184 | *
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| 185 | * @val is usually the machine frame number along with some attributes.
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| 186 | * The attributes by default follow the architecture defined bits. Meaning that
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| 187 | * if this is a X86_64 machine and four page table layout is used, the layout
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| 188 | * of val is:
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| 189 | * - 63 if set means No execute (NX)
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| 190 | * - 46-13 the machine frame number
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| 191 | * - 12 available for guest
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| 192 | * - 11 available for guest
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| 193 | * - 10 available for guest
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| 194 | * - 9 available for guest
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| 195 | * - 8 global
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| 196 | * - 7 PAT (PSE is disabled, must use hypercall to make 4MB or 2MB pages)
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| 197 | * - 6 dirty
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| 198 | * - 5 accessed
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| 199 | * - 4 page cached disabled
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| 200 | * - 3 page write through
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| 201 | * - 2 userspace accessible
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| 202 | * - 1 writeable
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| 203 | * - 0 present
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| 204 | *
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| 205 | * The one bits that does not fit with the default layout is the PAGE_PSE
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| 206 | * also called PAGE_PAT). The MMUEXT_[UN]MARK_SUPER arguments to the
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| 207 | * HYPERVISOR_mmuext_op serve as mechanism to set a pagetable to be 4MB
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| 208 | * (or 2MB) instead of using the PAGE_PSE bit.
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| 209 | *
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| 210 | * The reason that the PAGE_PSE (bit 7) is not being utilized is due to Xen
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| 211 | * using it as the Page Attribute Table (PAT) bit - for details on it please
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| 212 | * refer to Intel SDM 10.12. The PAT allows to set the caching attributes of
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| 213 | * pages instead of using MTRRs.
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| 214 | *
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| 215 | * The PAT MSR is as follows (it is a 64-bit value, each entry is 8 bits):
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| 216 | * PAT4 PAT0
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| 217 | * +-----+-----+----+----+----+-----+----+----+
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| 218 | * | UC | UC- | WC | WB | UC | UC- | WC | WB | <= Linux
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| 219 | * +-----+-----+----+----+----+-----+----+----+
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| 220 | * | UC | UC- | WT | WB | UC | UC- | WT | WB | <= BIOS (default when machine boots)
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| 221 | * +-----+-----+----+----+----+-----+----+----+
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| 222 | * | rsv | rsv | WP | WC | UC | UC- | WT | WB | <= Xen
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| 223 | * +-----+-----+----+----+----+-----+----+----+
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| 224 | *
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| 225 | * The lookup of this index table translates to looking up
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| 226 | * Bit 7, Bit 4, and Bit 3 of val entry:
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| 227 | *
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| 228 | * PAT/PSE (bit 7) ... PCD (bit 4) .. PWT (bit 3).
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| 229 | *
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| 230 | * If all bits are off, then we are using PAT0. If bit 3 turned on,
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| 231 | * then we are using PAT1, if bit 3 and bit 4, then PAT2..
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| 232 | *
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| 233 | * As you can see, the Linux PAT1 translates to PAT4 under Xen. Which means
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| 234 | * that if a guest that follows Linux's PAT setup and would like to set Write
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| 235 | * Combined on pages it MUST use PAT4 entry. Meaning that Bit 7 (PAGE_PAT) is
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| 236 | * set. For example, under Linux it only uses PAT0, PAT1, and PAT2 for the
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| 237 | * caching as:
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| 238 | *
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| 239 | * WB = none (so PAT0)
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| 240 | * WC = PWT (bit 3 on)
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| 241 | * UC = PWT | PCD (bit 3 and 4 are on).
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| 242 | *
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| 243 | * To make it work with Xen, it needs to translate the WC bit as so:
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| 244 | *
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| 245 | * PWT (so bit 3 on) --> PAT (so bit 7 is on) and clear bit 3
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| 246 | *
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| 247 | * And to translate back it would:
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| 248 | *
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| 249 | * PAT (bit 7 on) --> PWT (bit 3 on) and clear bit 7.
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| 250 |
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| 251 | #define MMU_NORMAL_PT_UPDATE 0
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| 252 | #define MMU_MACHPHYS_UPDATE 1
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| 253 | #define MMU_PT_UPDATE_PRESERVE_AD 2
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| 254 | #define MMU_PT_UPDATE_NO_TRANSLATE 3
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| 255 |
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| 256 | |
| 257 | * MMU EXTENDED OPERATIONS
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| 258 | *
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| 259 | * enum neg_errnoval HYPERVISOR_mmuext_op(mmuext_op_t uops[],
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| 260 | * unsigned int count,
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| 261 | * unsigned int *pdone,
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| 262 | * unsigned int foreigndom)
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| 263 |
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| 264 | |
| 265 | * A foreigndom (FD) can be specified (or DOMID_SELF for none).
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| 266 | * Where the FD has some effect, it is described below.
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| 267 | *
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| 268 | * cmd: MMUEXT_(UN)PIN_*_TABLE
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| 269 | * mfn: Machine frame number to be (un)pinned as a p.t. page.
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| 270 | * The frame must belong to the FD, if one is specified.
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| 271 | *
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| 272 | * cmd: MMUEXT_NEW_BASEPTR
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| 273 | * mfn: Machine frame number of new page-table base to install in MMU.
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| 274 | *
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| 275 | * cmd: MMUEXT_NEW_USER_BASEPTR [x86/64 only]
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| 276 | * mfn: Machine frame number of new page-table base to install in MMU
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| 277 | * when in user space.
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| 278 | *
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| 279 | * cmd: MMUEXT_TLB_FLUSH_LOCAL
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| 280 | * No additional arguments. Flushes local TLB.
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| 281 | *
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| 282 | * cmd: MMUEXT_INVLPG_LOCAL
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| 283 | * linear_addr: Linear address to be flushed from the local TLB.
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| 284 | *
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| 285 | * cmd: MMUEXT_TLB_FLUSH_MULTI
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| 286 | * vcpumask: Pointer to bitmap of VCPUs to be flushed.
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| 287 | *
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| 288 | * cmd: MMUEXT_INVLPG_MULTI
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| 289 | * linear_addr: Linear address to be flushed.
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| 290 | * vcpumask: Pointer to bitmap of VCPUs to be flushed.
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| 291 | *
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| 292 | * cmd: MMUEXT_TLB_FLUSH_ALL
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| 293 | * No additional arguments. Flushes all VCPUs' TLBs.
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| 294 | *
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| 295 | * cmd: MMUEXT_INVLPG_ALL
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| 296 | * linear_addr: Linear address to be flushed from all VCPUs' TLBs.
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| 297 | *
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| 298 | * cmd: MMUEXT_FLUSH_CACHE
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| 299 | * No additional arguments. Writes back and flushes cache contents.
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| 300 | *
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| 301 | * cmd: MMUEXT_FLUSH_CACHE_GLOBAL
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| 302 | * No additional arguments. Writes back and flushes cache contents
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| 303 | * on all CPUs in the system.
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| 304 | *
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| 305 | * cmd: MMUEXT_SET_LDT
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| 306 | * linear_addr: Linear address of LDT base (NB. must be page-aligned).
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| 307 | * nr_ents: Number of entries in LDT.
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| 308 | *
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| 309 | * cmd: MMUEXT_CLEAR_PAGE
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| 310 | * mfn: Machine frame number to be cleared.
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| 311 | *
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| 312 | * cmd: MMUEXT_COPY_PAGE
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| 313 | * mfn: Machine frame number of the destination page.
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| 314 | * src_mfn: Machine frame number of the source page.
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| 315 | *
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| 316 | * cmd: MMUEXT_[UN]MARK_SUPER
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| 317 | * mfn: Machine frame number of head of superpage to be [un]marked.
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| 318 |
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| 319 | #define MMUEXT_PIN_L1_TABLE 0
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| 320 | #define MMUEXT_PIN_L2_TABLE 1
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| 321 | #define MMUEXT_PIN_L3_TABLE 2
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| 322 | #define MMUEXT_PIN_L4_TABLE 3
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| 323 | #define MMUEXT_UNPIN_TABLE 4
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| 324 | #define MMUEXT_NEW_BASEPTR 5
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| 325 | #define MMUEXT_TLB_FLUSH_LOCAL 6
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| 326 | #define MMUEXT_INVLPG_LOCAL 7
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| 327 | #define MMUEXT_TLB_FLUSH_MULTI 8
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| 328 | #define MMUEXT_INVLPG_MULTI 9
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| 329 | #define MMUEXT_TLB_FLUSH_ALL 10
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| 330 | #define MMUEXT_INVLPG_ALL 11
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| 331 | #define MMUEXT_FLUSH_CACHE 12
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| 332 | #define MMUEXT_SET_LDT 13
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| 333 | #define MMUEXT_NEW_USER_BASEPTR 15
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| 334 | #define MMUEXT_CLEAR_PAGE 16
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| 335 | #define MMUEXT_COPY_PAGE 17
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| 336 | #define MMUEXT_FLUSH_CACHE_GLOBAL 18
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| 337 | #define MMUEXT_MARK_SUPER 19
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| 338 | #define MMUEXT_UNMARK_SUPER 20
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| 339 |
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| 340 | #ifndef __ASSEMBLER__
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| 341 | struct mmuext_op {
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| 342 | unsigned int cmd;
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| 343 | union {
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| 344 | |
| 345 | * CLEAR_PAGE, COPY_PAGE, [UN]MARK_SUPER
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| 346 | xen_pfn_t mfn;
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| 347 |
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| 348 | unsigned long linear_addr;
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| 349 | } arg1;
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| 350 | union {
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| 351 |
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| 352 | unsigned int nr_ents;
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| 353 |
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| 354 | void *vcpumask;
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| 355 |
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| 356 | xen_pfn_t src_mfn;
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| 357 | } arg2;
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| 358 | };
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| 359 | DEFINE_GUEST_HANDLE_STRUCT(mmuext_op);
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| 360 | #endif
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| 361 |
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| 362 |
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| 363 |
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| 364 |
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| 365 | #define UVMF_NONE (0UL<<0)
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| 366 | #define UVMF_TLB_FLUSH (1UL<<0)
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| 367 | #define UVMF_INVLPG (2UL<<0)
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| 368 | #define UVMF_FLUSHTYPE_MASK (3UL<<0)
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| 369 | #define UVMF_MULTI (0UL<<2)
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| 370 | #define UVMF_LOCAL (0UL<<2)
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| 371 | #define UVMF_ALL (1UL<<2)
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| 372 |
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| 373 | |
| 374 | * Commands to HYPERVISOR_console_io().
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| 375 |
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| 376 | #define CONSOLEIO_write 0
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| 377 | #define CONSOLEIO_read 1
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| 378 |
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| 379 | |
| 380 | * Commands to HYPERVISOR_vm_assist().
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| 381 |
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| 382 | #define VMASST_CMD_enable 0
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| 383 | #define VMASST_CMD_disable 1
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| 384 |
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| 385 |
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| 386 | #define VMASST_TYPE_4gb_segments 0
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| 387 |
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| 388 |
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| 389 | #define VMASST_TYPE_4gb_segments_notify 1
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| 390 |
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| 391 | |
| 392 | * x86 guests: support writes to bottom-level PTEs.
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| 393 | * NB1. Page-directory entries cannot be written.
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| 394 | * NB2. Guest must continue to remove all writable mappings of PTEs.
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| 395 |
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| 396 | #define VMASST_TYPE_writable_pagetables 2
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| 397 |
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| 398 |
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| 399 | #define VMASST_TYPE_pae_extended_cr3 3
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| 400 |
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| 401 | |
| 402 | * x86 guests: Sane behaviour for virtual iopl
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| 403 | * - virtual iopl updated from do_iret() hypercalls.
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| 404 | * - virtual iopl reported in bounce frames.
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| 405 | * - guest kernels assumed to be level 0 for the purpose of iopl checks.
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| 406 |
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| 407 | #define VMASST_TYPE_architectural_iopl 4
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| 408 |
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| 409 | |
| 410 | * All guests: activate update indicator in vcpu_runstate_info
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| 411 | * Enable setting the XEN_RUNSTATE_UPDATE flag in guest memory mapped
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| 412 | * vcpu_runstate_info during updates of the runstate information.
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| 413 |
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| 414 | #define VMASST_TYPE_runstate_update_flag 5
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| 415 |
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| 416 | #define MAX_VMASST_TYPE 5
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| 417 |
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| 418 | #ifndef __ASSEMBLER__
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| 419 |
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| 420 | typedef uint16_t domid_t;
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| 421 |
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| 422 |
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| 423 | #define DOMID_FIRST_RESERVED (0x7FF0U)
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| 424 |
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| 425 |
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| 426 | #define DOMID_SELF (0x7FF0U)
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| 427 |
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| 428 | |
| 429 | * DOMID_IO is used to restrict page-table updates to mapping I/O memory.
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| 430 | * Although no Foreign Domain need be specified to map I/O pages, DOMID_IO
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| 431 | * is useful to ensure that no mappings to the OS's own heap are accidentally
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| 432 | * installed. (e.g., in Linux this could cause havoc as reference counts
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| 433 | * aren't adjusted on the I/O-mapping code path).
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| 434 | * This only makes sense in MMUEXT_SET_FOREIGNDOM, but in that context can
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| 435 | * be specified by any calling domain.
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| 436 |
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| 437 | #define DOMID_IO (0x7FF1U)
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| 438 |
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| 439 | |
| 440 | * DOMID_XEN is used to allow privileged domains to map restricted parts of
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| 441 | * Xen's heap space (e.g., the machine_to_phys table).
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| 442 | * This only makes sense in MMUEXT_SET_FOREIGNDOM, and is only permitted if
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| 443 | * the caller is privileged.
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| 444 |
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| 445 | #define DOMID_XEN (0x7FF2U)
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| 446 |
|
| 447 |
|
| 448 | #define DOMID_COW (0x7FF3U)
|
| 449 |
|
| 450 |
|
| 451 | #define DOMID_INVALID (0x7FF4U)
|
| 452 |
|
| 453 |
|
| 454 | #define DOMID_IDLE (0x7FFFU)
|
| 455 |
|
| 456 | |
| 457 | * Send an array of these to HYPERVISOR_mmu_update().
|
| 458 | * NB. The fields are natural pointer/address size for this architecture.
|
| 459 |
|
| 460 | struct mmu_update {
|
| 461 | uint64_t ptr;
|
| 462 | uint64_t val;
|
| 463 | };
|
| 464 | DEFINE_GUEST_HANDLE_STRUCT(mmu_update);
|
| 465 |
|
| 466 | |
| 467 | * Send an array of these to HYPERVISOR_multicall().
|
| 468 | * NB. The fields are logically the natural register size for this
|
| 469 | * architecture. In cases where xen_ulong_t is larger than this then
|
| 470 | * any unused bits in the upper portion must be zero.
|
| 471 |
|
| 472 | struct multicall_entry {
|
| 473 | xen_ulong_t op;
|
| 474 | xen_long_t result;
|
| 475 | xen_ulong_t args[6];
|
| 476 | };
|
| 477 | DEFINE_GUEST_HANDLE_STRUCT(multicall_entry);
|
| 478 |
|
| 479 | struct vcpu_time_info {
|
| 480 | |
| 481 | * Updates to the following values are preceded and followed
|
| 482 | * by an increment of 'version'. The guest can therefore
|
| 483 | * detect updates by looking for changes to 'version'. If the
|
| 484 | * least-significant bit of the version number is set then an
|
| 485 | * update is in progress and the guest must wait to read a
|
| 486 | * consistent set of values. The correct way to interact with
|
| 487 | * the version number is similar to Linux's seqlock: see the
|
| 488 | * implementations of read_seqbegin/read_seqretry.
|
| 489 |
|
| 490 | uint32_t version;
|
| 491 | uint32_t pad0;
|
| 492 | uint64_t tsc_timestamp;
|
| 493 | uint64_t system_time;
|
| 494 | |
| 495 | * Current system time:
|
| 496 | * system_time + ((tsc - tsc_timestamp) << tsc_shift) * tsc_to_system_mul
|
| 497 | * CPU frequency (Hz):
|
| 498 | * ((10^9 << 32) / tsc_to_system_mul) >> tsc_shift
|
| 499 |
|
| 500 | uint32_t tsc_to_system_mul;
|
| 501 | int8_t tsc_shift;
|
| 502 | int8_t pad1[3];
|
| 503 | };
|
| 504 |
|
| 505 | struct vcpu_info {
|
| 506 | |
| 507 | * 'evtchn_upcall_pending' is written non-zero by Xen to indicate
|
| 508 | * a pending notification for a particular VCPU. It is then cleared
|
| 509 | * by the guest OS /before/ checking for pending work, thus avoiding
|
| 510 | * a set-and-check race. Note that the mask is only accessed by Xen
|
| 511 | * on the CPU that is currently hosting the VCPU. This means that the
|
| 512 | * pending and mask flags can be updated by the guest without special
|
| 513 | * synchronisation (i.e., no need for the x86 LOCK prefix).
|
| 514 | * This may seem suboptimal because if the pending flag is set by
|
| 515 | * a different CPU then an IPI may be scheduled even when the mask
|
| 516 | * is set. However, note:
|
| 517 | * 1. The task of 'interrupt holdoff' is covered by the per-event-
|
| 518 | * channel mask bits. A 'noisy' event that is continually being
|
| 519 | * triggered can be masked at source at this very precise
|
| 520 | * granularity.
|
| 521 | * 2. The main purpose of the per-VCPU mask is therefore to restrict
|
| 522 | * reentrant execution: whether for concurrency control, or to
|
| 523 | * prevent unbounded stack usage. Whatever the purpose, we expect
|
| 524 | * that the mask will be asserted only for short periods at a time,
|
| 525 | * and so the likelihood of a 'spurious' IPI is suitably small.
|
| 526 | * The mask is read before making an event upcall to the guest: a
|
| 527 | * non-zero mask therefore guarantees that the VCPU will not receive
|
| 528 | * an upcall activation. The mask is cleared when the VCPU requests
|
| 529 | * to block: this avoids wakeup-waiting races.
|
| 530 |
|
| 531 | uint8_t evtchn_upcall_pending;
|
| 532 | uint8_t evtchn_upcall_mask;
|
| 533 | xen_ulong_t evtchn_pending_sel;
|
| 534 | struct arch_vcpu_info arch;
|
| 535 | struct pvclock_vcpu_time_info time;
|
| 536 | };
|
| 537 |
|
| 538 | |
| 539 | * Xen/kernel shared data -- pointer provided in start_info.
|
| 540 | * NB. We expect that this struct is smaller than a page.
|
| 541 |
|
| 542 | struct shared_info {
|
| 543 | struct vcpu_info vcpu_info[MAX_VIRT_CPUS];
|
| 544 |
|
| 545 | |
| 546 | * A domain can create "event channels" on which it can send and receive
|
| 547 | * asynchronous event notifications. There are three classes of event that
|
| 548 | * are delivered by this mechanism:
|
| 549 | * 1. Bi-directional inter- and intra-domain connections. Domains must
|
| 550 | * arrange out-of-band to set up a connection (usually by allocating
|
| 551 | * an unbound 'listener' port and avertising that via a storage service
|
| 552 | * such as xenstore).
|
| 553 | * 2. Physical interrupts. A domain with suitable hardware-access
|
| 554 | * privileges can bind an event-channel port to a physical interrupt
|
| 555 | * source.
|
| 556 | * 3. Virtual interrupts ('events'). A domain can bind an event-channel
|
| 557 | * port to a virtual interrupt source, such as the virtual-timer
|
| 558 | * device or the emergency console.
|
| 559 | *
|
| 560 | * Event channels are addressed by a "port index". Each channel is
|
| 561 | * associated with two bits of information:
|
| 562 | * 1. PENDING -- notifies the domain that there is a pending notification
|
| 563 | * to be processed. This bit is cleared by the guest.
|
| 564 | * 2. MASK -- if this bit is clear then a 0->1 transition of PENDING
|
| 565 | * will cause an asynchronous upcall to be scheduled. This bit is only
|
| 566 | * updated by the guest. It is read-only within Xen. If a channel
|
| 567 | * becomes pending while the channel is masked then the 'edge' is lost
|
| 568 | * (i.e., when the channel is unmasked, the guest must manually handle
|
| 569 | * pending notifications as no upcall will be scheduled by Xen).
|
| 570 | *
|
| 571 | * To expedite scanning of pending notifications, any 0->1 pending
|
| 572 | * transition on an unmasked channel causes a corresponding bit in a
|
| 573 | * per-vcpu selector word to be set. Each bit in the selector covers a
|
| 574 | * 'C long' in the PENDING bitfield array.
|
| 575 |
|
| 576 | xen_ulong_t evtchn_pending[sizeof(xen_ulong_t) * 8];
|
| 577 | xen_ulong_t evtchn_mask[sizeof(xen_ulong_t) * 8];
|
| 578 |
|
| 579 | |
| 580 | * Wallclock time: updated only by control software. Guests should base
|
| 581 | * their gettimeofday() syscall on this wallclock-base value.
|
| 582 |
|
| 583 | struct pvclock_wall_clock wc;
|
| 584 | #ifndef CONFIG_X86_32
|
| 585 | uint32_t wc_sec_hi;
|
| 586 | #endif
|
| 587 | struct arch_shared_info arch;
|
| 588 |
|
| 589 | };
|
| 590 |
|
| 591 | |
| 592 | * Start-of-day memory layout
|
| 593 | *
|
| 594 | * 1. The domain is started within contiguous virtual-memory region.
|
| 595 | * 2. The contiguous region begins and ends on an aligned 4MB boundary.
|
| 596 | * 3. This the order of bootstrap elements in the initial virtual region:
|
| 597 | * a. relocated kernel image
|
| 598 | * b. initial ram disk [mod_start, mod_len]
|
| 599 | * (may be omitted)
|
| 600 | * c. list of allocated page frames [mfn_list, nr_pages]
|
| 601 | * (unless relocated due to XEN_ELFNOTE_INIT_P2M)
|
| 602 | * d. start_info_t structure [register ESI (x86)]
|
| 603 | * in case of dom0 this page contains the console info, too
|
| 604 | * e. unless dom0: xenstore ring page
|
| 605 | * f. unless dom0: console ring page
|
| 606 | * g. bootstrap page tables [pt_base, CR3 (x86)]
|
| 607 | * h. bootstrap stack [register ESP (x86)]
|
| 608 | * 4. Bootstrap elements are packed together, but each is 4kB-aligned.
|
| 609 | * 5. The list of page frames forms a contiguous 'pseudo-physical' memory
|
| 610 | * layout for the domain. In particular, the bootstrap virtual-memory
|
| 611 | * region is a 1:1 mapping to the first section of the pseudo-physical map.
|
| 612 | * 6. All bootstrap elements are mapped read-writable for the guest OS. The
|
| 613 | * only exception is the bootstrap page table, which is mapped read-only.
|
| 614 | * 7. There is guaranteed to be at least 512kB padding after the final
|
| 615 | * bootstrap element. If necessary, the bootstrap virtual region is
|
| 616 | * extended by an extra 4MB to ensure this.
|
| 617 |
|
| 618 |
|
| 619 | #define MAX_GUEST_CMDLINE 1024
|
| 620 | struct start_info {
|
| 621 |
|
| 622 | char magic[32];
|
| 623 | unsigned long nr_pages;
|
| 624 | unsigned long shared_info;
|
| 625 | uint32_t flags;
|
| 626 | xen_pfn_t store_mfn;
|
| 627 | uint32_t store_evtchn;
|
| 628 | union {
|
| 629 | struct {
|
| 630 | xen_pfn_t mfn;
|
| 631 | uint32_t evtchn;
|
| 632 | } domU;
|
| 633 | struct {
|
| 634 | uint32_t info_off;
|
| 635 | uint32_t info_size;
|
| 636 | } dom0;
|
| 637 | } console;
|
| 638 |
|
| 639 | unsigned long pt_base;
|
| 640 | unsigned long nr_pt_frames;
|
| 641 | unsigned long mfn_list;
|
| 642 | unsigned long mod_start;
|
| 643 | unsigned long mod_len;
|
| 644 | int8_t cmd_line[MAX_GUEST_CMDLINE];
|
| 645 |
|
| 646 | unsigned long first_p2m_pfn;
|
| 647 | unsigned long nr_p2m_frames;
|
| 648 | };
|
| 649 |
|
| 650 |
|
| 651 | #define SIF_PRIVILEGED (1<<0)
|
| 652 | #define SIF_INITDOMAIN (1<<1)
|
| 653 | #define SIF_MULTIBOOT_MOD (1<<2)
|
| 654 | #define SIF_MOD_START_PFN (1<<3)
|
| 655 | #define SIF_VIRT_P2M_4TOOLS (1<<4)
|
| 656 |
|
| 657 | #define SIF_PM_MASK (0xFF<<8)
|
| 658 |
|
| 659 | |
| 660 | * A multiboot module is a package containing modules very similar to a
|
| 661 | * multiboot module array. The only differences are:
|
| 662 | * - the array of module descriptors is by convention simply at the beginning
|
| 663 | * of the multiboot module,
|
| 664 | * - addresses in the module descriptors are based on the beginning of the
|
| 665 | * multiboot module,
|
| 666 | * - the number of modules is determined by a termination descriptor that has
|
| 667 | * mod_start == 0.
|
| 668 | *
|
| 669 | * This permits to both build it statically and reference it in a configuration
|
| 670 | * file, and let the PV guest easily rebase the addresses to virtual addresses
|
| 671 | * and at the same time count the number of modules.
|
| 672 |
|
| 673 | struct xen_multiboot_mod_list {
|
| 674 |
|
| 675 | uint32_t mod_start;
|
| 676 |
|
| 677 | uint32_t mod_end;
|
| 678 |
|
| 679 | uint32_t cmdline;
|
| 680 |
|
| 681 | uint32_t pad;
|
| 682 | };
|
| 683 | |
| 684 | * The console structure in start_info.console.dom0
|
| 685 | *
|
| 686 | * This structure includes a variety of information required to
|
| 687 | * have a working VGA/VESA console.
|
| 688 |
|
| 689 | struct dom0_vga_console_info {
|
| 690 | uint8_t video_type;
|
| 691 | #define XEN_VGATYPE_TEXT_MODE_3 0x03
|
| 692 | #define XEN_VGATYPE_VESA_LFB 0x23
|
| 693 | #define XEN_VGATYPE_EFI_LFB 0x70
|
| 694 |
|
| 695 | union {
|
| 696 | struct {
|
| 697 |
|
| 698 | uint16_t font_height;
|
| 699 |
|
| 700 | uint16_t cursor_x, cursor_y;
|
| 701 |
|
| 702 | uint16_t rows, columns;
|
| 703 | } text_mode_3;
|
| 704 |
|
| 705 | struct {
|
| 706 |
|
| 707 | uint16_t width, height;
|
| 708 |
|
| 709 | uint16_t bytes_per_line;
|
| 710 |
|
| 711 | uint16_t bits_per_pixel;
|
| 712 |
|
| 713 | uint32_t lfb_base;
|
| 714 | uint32_t lfb_size;
|
| 715 |
|
| 716 | uint8_t red_pos, red_size;
|
| 717 | uint8_t green_pos, green_size;
|
| 718 | uint8_t blue_pos, blue_size;
|
| 719 | uint8_t rsvd_pos, rsvd_size;
|
| 720 |
|
| 721 |
|
| 722 | uint32_t gbl_caps;
|
| 723 |
|
| 724 | uint16_t mode_attrs;
|
| 725 | uint16_t pad;
|
| 726 |
|
| 727 | uint32_t ext_lfb_base;
|
| 728 | } vesa_lfb;
|
| 729 | } u;
|
| 730 | };
|
| 731 |
|
| 732 | typedef uint64_t cpumap_t;
|
| 733 |
|
| 734 | typedef uint8_t xen_domain_handle_t[16];
|
| 735 |
|
| 736 |
|
| 737 | #define __mk_unsigned_long(x) x ## UL
|
| 738 | #define mk_unsigned_long(x) __mk_unsigned_long(x)
|
| 739 |
|
| 740 | #define TMEM_SPEC_VERSION 1
|
| 741 |
|
| 742 | struct tmem_op {
|
| 743 | uint32_t cmd;
|
| 744 | int32_t pool_id;
|
| 745 | union {
|
| 746 | struct {
|
| 747 | uint64_t uuid[2];
|
| 748 | uint32_t flags;
|
| 749 | } new;
|
| 750 | struct {
|
| 751 | uint64_t oid[3];
|
| 752 | uint32_t index;
|
| 753 | uint32_t tmem_offset;
|
| 754 | uint32_t pfn_offset;
|
| 755 | uint32_t len;
|
| 756 | GUEST_HANDLE(void) gmfn;
|
| 757 | } gen;
|
| 758 | } u;
|
| 759 | };
|
| 760 |
|
| 761 | DEFINE_GUEST_HANDLE(u64);
|
| 762 |
|
| 763 | #else
|
| 764 |
|
| 765 |
|
| 766 | #define mk_unsigned_long(x) x
|
| 767 |
|
| 768 | #endif
|
| 769 |
|
| 770 | #endif
|