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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2018-2020 Christoph Hellwig.
4 *
5 * DMA operations that map physical memory directly without using an IOMMU.
6 */
7#include <linux/memblock.h> /* for max_pfn */
8#include <linux/export.h>
9#include <linux/mm.h>
10#include <linux/dma-map-ops.h>
11#include <linux/scatterlist.h>
12#include <linux/pfn.h>
13#include <linux/vmalloc.h>
14#include <linux/set_memory.h>
15#include <linux/slab.h>
16#include <linux/pci-p2pdma.h>
17#include <linux/cc_platform.h>
18
19#include "direct.h"
20
21/*
22 * Most architectures use ZONE_DMA for the first 16 Megabytes, but some use
23 * it for entirely different regions. In that case the arch code needs to
24 * override the variable below for dma-direct to work properly.
25 */
26u64 zone_dma_limit __ro_after_init = DMA_BIT_MASK(24);
27
28static inline dma_addr_t phys_to_dma_direct(struct device *dev,
29 phys_addr_t phys, bool unencrypted)
30{
31 if (unencrypted)
32 return phys_to_dma_unencrypted(dev, phys);
33 return phys_to_dma_encrypted(dev, phys);
34}
35
36static inline struct page *dma_direct_to_page(struct device *dev,
37 dma_addr_t dma_addr)
38{
39 return pfn_to_page(PHYS_PFN(dma_to_phys(dev, dma_addr)));
40}
41
42u64 dma_direct_get_required_mask(struct device *dev)
43{
44 bool require_decrypted = force_dma_unencrypted(dev);
45 phys_addr_t phys = ((phys_addr_t)max_pfn << PAGE_SHIFT) - 1;
46 u64 max_dma = phys_to_dma_direct(dev, phys, require_decrypted);
47
48 return (1ULL << (fls64(max_dma) - 1)) * 2 - 1;
49}
50
51static gfp_t dma_direct_optimal_gfp_mask(struct device *dev, u64 *phys_limit)
52{
53 u64 dma_limit = min_not_zero(
54 dev->coherent_dma_mask,
55 dev->bus_dma_limit);
56
57 /*
58 * Optimistically try the zone that the physical address mask falls
59 * into first. If that returns memory that isn't actually addressable
60 * we will fallback to the next lower zone and try again.
61 *
62 * Note that GFP_DMA32 and GFP_DMA are no ops without the corresponding
63 * zones.
64 */
65 *phys_limit = dma_to_phys(dev, dma_limit);
66 if (*phys_limit <= zone_dma_limit)
67 return GFP_DMA;
68 if (*phys_limit <= DMA_BIT_MASK(32))
69 return GFP_DMA32;
70 return 0;
71}
72
73bool dma_coherent_ok(struct device *dev, phys_addr_t phys, size_t size)
74{
75 bool require_decrypted = force_dma_unencrypted(dev);
76 dma_addr_t dma_addr = phys_to_dma_direct(dev, phys, require_decrypted);
77
78 if (dma_addr == DMA_MAPPING_ERROR)
79 return false;
80 return dma_addr + size - 1 <=
81 min_not_zero(dev->coherent_dma_mask, dev->bus_dma_limit);
82}
83
84static int dma_set_decrypted(struct device *dev, void *vaddr, size_t size)
85{
86 int ret;
87
88 ret = set_memory_decrypted((unsigned long)vaddr, PFN_UP(size));
89 if (ret)
90 pr_warn_ratelimited("leaking DMA memory that can't be decrypted\n");
91 return ret;
92}
93
94static int dma_set_encrypted(struct device *dev, void *vaddr, size_t size)
95{
96 int ret;
97
98 ret = set_memory_encrypted((unsigned long)vaddr, PFN_UP(size));
99 if (ret)
100 pr_warn_ratelimited("leaking DMA memory that can't be re-encrypted\n");
101 return ret;
102}
103
104static struct page *dma_direct_alloc_swiotlb(struct device *dev, size_t size,
105 unsigned long attrs)
106{
107 struct page *page = swiotlb_alloc(dev, size, attrs);
108
109 if (page && !dma_coherent_ok(dev, page_to_phys(page), size)) {
110 swiotlb_free(dev, page, size);
111 return NULL;
112 }
113
114 return page;
115}
116
117static struct page *__dma_direct_alloc_pages(struct device *dev, size_t size,
118 gfp_t gfp, bool allow_highmem)
119{
120 int node = dev_to_node(dev);
121 struct page *page;
122 u64 phys_limit;
123
124 WARN_ON_ONCE(!PAGE_ALIGNED(size));
125
126 gfp |= dma_direct_optimal_gfp_mask(dev, &phys_limit);
127 page = dma_alloc_contiguous(dev, size, gfp);
128 if (page) {
129 if (dma_coherent_ok(dev, page_to_phys(page), size) &&
130 (allow_highmem || !PageHighMem(page)))
131 return page;
132
133 dma_free_contiguous(dev, page, size);
134 }
135
136 while ((page = alloc_pages_node(node, gfp, get_order(size)))
137 && !dma_coherent_ok(dev, page_to_phys(page), size)) {
138 __free_pages(page, get_order(size));
139
140 if (IS_ENABLED(CONFIG_ZONE_DMA32) &&
141 phys_limit < DMA_BIT_MASK(64) &&
142 !(gfp & (GFP_DMA32 | GFP_DMA)))
143 gfp |= GFP_DMA32;
144 else if (IS_ENABLED(CONFIG_ZONE_DMA) && !(gfp & GFP_DMA))
145 gfp = (gfp & ~GFP_DMA32) | GFP_DMA;
146 else
147 return NULL;
148 }
149
150 return page;
151}
152
153/*
154 * Check if a potentially blocking operations needs to dip into the atomic
155 * pools for the given device/gfp.
156 */
157static bool dma_direct_use_pool(struct device *dev, gfp_t gfp)
158{
159 return !gfpflags_allow_blocking(gfp) && !is_swiotlb_for_alloc(dev);
160}
161
162static struct page *dma_direct_alloc_from_pool(struct device *dev, size_t size,
163 dma_addr_t *dma_handle, void **cpu_addr, gfp_t gfp,
164 unsigned long attrs)
165{
166 struct page *page;
167 u64 phys_limit;
168
169 if (WARN_ON_ONCE(!IS_ENABLED(CONFIG_DMA_COHERENT_POOL)))
170 return NULL;
171
172 gfp |= dma_direct_optimal_gfp_mask(dev, &phys_limit);
173 page = dma_alloc_from_pool(dev, size, cpu_addr, gfp, attrs,
174 dma_coherent_ok);
175 if (!page)
176 return NULL;
177 *dma_handle = phys_to_dma_direct(dev, page_to_phys(page),
178 attrs & __DMA_ATTR_ALLOC_CC_SHARED);
179 return page;
180}
181
182static void *dma_direct_alloc_no_mapping(struct device *dev, size_t size,
183 dma_addr_t *dma_handle, gfp_t gfp)
184{
185 struct page *page;
186
187 page = __dma_direct_alloc_pages(dev, size, gfp & ~__GFP_ZERO, true);
188 if (!page)
189 return NULL;
190
191 /* remove any dirty cache lines on the kernel alias */
192 if (!PageHighMem(page))
193 arch_dma_prep_coherent(page, size);
194 /*
195 * return the page pointer as the opaque cookie.
196 * Never used for unencrypted allocation
197 */
198 *dma_handle = phys_to_dma_encrypted(dev, page_to_phys(page));
199 return page;
200}
201
202void *dma_direct_alloc(struct device *dev, size_t size,
203 dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs)
204{
205 bool remap = false, set_uncached = false;
206 bool mark_mem_decrypt = false;
207 bool allow_highmem = true;
208 struct page *page;
209 void *cpu_addr;
210
211 if (force_dma_unencrypted(dev))
212 attrs |= __DMA_ATTR_ALLOC_CC_SHARED;
213
214 if (attrs & __DMA_ATTR_ALLOC_CC_SHARED) {
215 /*
216 * Unencrypted/shared DMA requires a linear-mapped buffer
217 * address to look up the PFN and set architecture-required PFN
218 * attributes. This is not possible with HighMem. Avoid HighMem
219 * allocation.
220 */
221 allow_highmem = false;
222 mark_mem_decrypt = true;
223 }
224
225 size = PAGE_ALIGN(size);
226 if (attrs & DMA_ATTR_NO_WARN)
227 gfp |= __GFP_NOWARN;
228
229 if (((attrs & (DMA_ATTR_NO_KERNEL_MAPPING | __DMA_ATTR_ALLOC_CC_SHARED)) ==
230 DMA_ATTR_NO_KERNEL_MAPPING) && !is_swiotlb_for_alloc(dev))
231 return dma_direct_alloc_no_mapping(dev, size, dma_handle, gfp);
232
233 if (!dev_is_dma_coherent(dev)) {
234 if (IS_ENABLED(CONFIG_ARCH_HAS_DMA_ALLOC) &&
235 !is_swiotlb_for_alloc(dev))
236 return arch_dma_alloc(dev, size, dma_handle, gfp,
237 attrs);
238
239 /*
240 * If there is a global pool, always allocate from it for
241 * non-coherent devices.
242 */
243 if (IS_ENABLED(CONFIG_DMA_GLOBAL_POOL))
244 return dma_alloc_from_global_coherent(dev, size,
245 dma_handle);
246
247 /*
248 * Otherwise we require the architecture to either be able to
249 * mark arbitrary parts of the kernel direct mapping uncached,
250 * or remapped it uncached.
251 */
252 set_uncached = IS_ENABLED(CONFIG_ARCH_HAS_DMA_SET_UNCACHED);
253 remap = IS_ENABLED(CONFIG_DMA_DIRECT_REMAP);
254 if (!set_uncached && !remap) {
255 pr_warn_once("coherent DMA allocations not supported on this platform.\n");
256 return NULL;
257 }
258 }
259
260 /*
261 * Remapping or decrypting memory may block, allocate the memory from
262 * the atomic pools instead if we aren't allowed block.
263 * FIXME: With CONFIG_DMA_DIRECT_REMAP, the pool is also mapped as
264 * DMA-coherent (non-cacheable). We may want to create a separate pool
265 * dedicated to CC_SHARED atomic allocations.
266 */
267 if ((remap || (attrs & __DMA_ATTR_ALLOC_CC_SHARED)) &&
268 dma_direct_use_pool(dev, gfp)) {
269 page = dma_direct_alloc_from_pool(dev, size,
270 dma_handle, &cpu_addr,
271 gfp, attrs);
272 return page ? cpu_addr : NULL;
273 }
274
275 if (is_swiotlb_for_alloc(dev)) {
276 page = dma_direct_alloc_swiotlb(dev, size, attrs);
277 if (page) {
278 /*
279 * swiotlb allocations comes from pool already marked
280 * decrypted
281 */
282 mark_mem_decrypt = false;
283 goto setup_page;
284 }
285 return NULL;
286 }
287
288 /* we always manually zero the memory once we are done */
289 page = __dma_direct_alloc_pages(dev, size, gfp & ~__GFP_ZERO, allow_highmem);
290 if (!page)
291 return NULL;
292
293setup_page:
294 /*
295 * dma_alloc_contiguous can return highmem pages depending on a
296 * combination the cma= arguments and per-arch setup. These need to be
297 * remapped to return a kernel virtual address.
298 */
299 if (PageHighMem(page)) {
300 remap = true;
301 set_uncached = false;
302 }
303
304 if (mark_mem_decrypt) {
305 void *lm_addr;
306
307 lm_addr = page_address(page);
308 if (set_memory_decrypted((unsigned long)lm_addr, PFN_UP(size)))
309 goto out_leak_pages;
310 }
311
312 if (remap) {
313 pgprot_t prot = dma_pgprot(dev, PAGE_KERNEL, attrs);
314
315 /* remove any dirty cache lines on the kernel alias */
316 arch_dma_prep_coherent(page, size);
317
318 /* create a coherent mapping */
319 cpu_addr = dma_common_contiguous_remap(page, size, prot,
320 __builtin_return_address(0));
321 if (!cpu_addr)
322 goto out_encrypt_pages;
323 } else {
324 cpu_addr = page_address(page);
325 }
326
327 memset(cpu_addr, 0, size);
328
329 if (set_uncached) {
330 void *uncached_cpu_addr;
331
332 arch_dma_prep_coherent(page, size);
333 uncached_cpu_addr = arch_dma_set_uncached(cpu_addr, size);
334 if (IS_ERR(uncached_cpu_addr))
335 goto out_free_remap_pages;
336 cpu_addr = uncached_cpu_addr;
337 }
338
339 *dma_handle = phys_to_dma_direct(dev, page_to_phys(page),
340 attrs & __DMA_ATTR_ALLOC_CC_SHARED);
341 return cpu_addr;
342
343out_free_remap_pages:
344 if (remap)
345 dma_common_free_remap(cpu_addr, size);
346
347out_encrypt_pages:
348 if (mark_mem_decrypt &&
349 dma_set_encrypted(dev, page_address(page), size))
350 goto out_leak_pages;
351
352 if (!swiotlb_free(dev, page, size))
353 dma_free_contiguous(dev, page, size);
354 return NULL;
355out_leak_pages:
356 return NULL;
357}
358
359void dma_direct_free(struct device *dev, size_t size,
360 void *cpu_addr, dma_addr_t dma_addr, unsigned long attrs)
361{
362 phys_addr_t phys;
363 bool mark_mem_encrypted = false;
364 struct io_tlb_pool *swiotlb_pool;
365 unsigned int page_order = get_order(size);
366
367 /*
368 * If the allocation used decrypted/shared backing pages, restore
369 * the encryption state on free.
370 */
371 if (force_dma_unencrypted(dev))
372 attrs |= __DMA_ATTR_ALLOC_CC_SHARED;
373
374 if (attrs & __DMA_ATTR_ALLOC_CC_SHARED)
375 mark_mem_encrypted = true;
376
377 if (((attrs & (DMA_ATTR_NO_KERNEL_MAPPING | __DMA_ATTR_ALLOC_CC_SHARED)) ==
378 DMA_ATTR_NO_KERNEL_MAPPING) && !is_swiotlb_for_alloc(dev)) {
379 /* cpu_addr is a struct page cookie, not a kernel address */
380 dma_free_contiguous(dev, cpu_addr, size);
381 return;
382 }
383
384 if (IS_ENABLED(CONFIG_ARCH_HAS_DMA_ALLOC) &&
385 !dev_is_dma_coherent(dev) &&
386 !is_swiotlb_for_alloc(dev)) {
387 arch_dma_free(dev, size, cpu_addr, dma_addr, attrs);
388 return;
389 }
390
391 if (IS_ENABLED(CONFIG_DMA_GLOBAL_POOL) &&
392 !dev_is_dma_coherent(dev)) {
393 if (!dma_release_from_global_coherent(page_order, cpu_addr))
394 WARN_ON_ONCE(1);
395 return;
396 }
397
398 /* If cpu_addr is not from an atomic pool, dma_free_from_pool() fails */
399 if (IS_ENABLED(CONFIG_DMA_COHERENT_POOL) &&
400 dma_free_from_pool(dev, cpu_addr, PAGE_ALIGN(size)))
401 return;
402
403 phys = dma_to_phys(dev, dma_addr);
404 swiotlb_pool = swiotlb_find_pool(dev, phys);
405 if (swiotlb_pool)
406 /* Swiotlb doesn't need a page attribute update on free */
407 mark_mem_encrypted = false;
408
409 if (is_vmalloc_addr(cpu_addr)) {
410 vunmap(cpu_addr);
411 } else {
412 if (IS_ENABLED(CONFIG_ARCH_HAS_DMA_CLEAR_UNCACHED))
413 arch_dma_clear_uncached(cpu_addr, size);
414 }
415
416 if (mark_mem_encrypted) {
417 void *lm_addr;
418
419 lm_addr = phys_to_virt(phys);
420 if (set_memory_encrypted((unsigned long)lm_addr, PFN_UP(size))) {
421 pr_warn_ratelimited("leaking DMA memory that can't be re-encrypted\n");
422 return;
423 }
424 }
425
426 if (swiotlb_pool)
427 swiotlb_free_from_pool(dev, phys, swiotlb_pool);
428 else
429 dma_free_contiguous(dev, dma_direct_to_page(dev, dma_addr), size);
430}
431
432struct page *dma_direct_alloc_pages(struct device *dev, size_t size,
433 dma_addr_t *dma_handle, enum dma_data_direction dir, gfp_t gfp)
434{
435 unsigned long attrs = 0;
436 struct page *page;
437 void *cpu_addr;
438
439 if (force_dma_unencrypted(dev))
440 attrs |= __DMA_ATTR_ALLOC_CC_SHARED;
441
442 if ((attrs & __DMA_ATTR_ALLOC_CC_SHARED) && dma_direct_use_pool(dev, gfp))
443 return dma_direct_alloc_from_pool(dev, size, dma_handle,
444 &cpu_addr, gfp, attrs);
445
446 if (is_swiotlb_for_alloc(dev)) {
447 page = dma_direct_alloc_swiotlb(dev, size, attrs);
448 if (!page)
449 return NULL;
450
451 cpu_addr = page_address(page);
452 goto setup_page;
453 }
454
455 page = __dma_direct_alloc_pages(dev, size, gfp, false);
456 if (!page)
457 return NULL;
458
459 cpu_addr = page_address(page);
460 if ((attrs & __DMA_ATTR_ALLOC_CC_SHARED) &&
461 dma_set_decrypted(dev, cpu_addr, size))
462 goto out_leak_pages;
463setup_page:
464 memset(cpu_addr, 0, size);
465 *dma_handle = phys_to_dma_direct(dev, page_to_phys(page),
466 attrs & __DMA_ATTR_ALLOC_CC_SHARED);
467 return page;
468out_leak_pages:
469 return NULL;
470}
471
472void dma_direct_free_pages(struct device *dev, size_t size,
473 struct page *page, dma_addr_t dma_addr,
474 enum dma_data_direction dir)
475{
476 phys_addr_t phys;
477 void *vaddr = page_address(page);
478 struct io_tlb_pool *swiotlb_pool;
479 /*
480 * if the device had requested for an unencrypted buffer,
481 * convert it to encrypted on free
482 */
483 bool mark_mem_encrypted = force_dma_unencrypted(dev);
484
485 /* If page is not from an atomic pool, dma_free_from_pool_page() fails */
486 if (IS_ENABLED(CONFIG_DMA_COHERENT_POOL) &&
487 dma_free_from_pool_page(dev, page, size))
488 return;
489
490 phys = page_to_phys(page);
491 swiotlb_pool = swiotlb_find_pool(dev, phys);
492 if (swiotlb_pool)
493 mark_mem_encrypted = false;
494
495 if (mark_mem_encrypted && dma_set_encrypted(dev, vaddr, size))
496 return;
497
498 if (swiotlb_pool)
499 swiotlb_free_from_pool(dev, phys, swiotlb_pool);
500 else
501 dma_free_contiguous(dev, page, size);
502}
503
504#if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \
505 defined(CONFIG_SWIOTLB)
506void dma_direct_sync_sg_for_device(struct device *dev,
507 struct scatterlist *sgl, int nents, enum dma_data_direction dir)
508{
509 struct scatterlist *sg;
510 int i;
511
512 for_each_sg(sgl, sg, nents, i) {
513 phys_addr_t paddr = dma_to_phys(dev, sg_dma_address(sg));
514
515 swiotlb_sync_single_for_device(dev, paddr, sg->length, dir);
516
517 if (!dev_is_dma_coherent(dev))
518 arch_sync_dma_for_device(paddr, sg->length,
519 dir);
520 }
521 if (!dev_is_dma_coherent(dev))
522 arch_sync_dma_flush();
523}
524#endif
525
526#if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \
527 defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL) || \
528 defined(CONFIG_SWIOTLB)
529void dma_direct_sync_sg_for_cpu(struct device *dev,
530 struct scatterlist *sgl, int nents, enum dma_data_direction dir)
531{
532 struct scatterlist *sg;
533 int i;
534
535 for_each_sg(sgl, sg, nents, i) {
536 phys_addr_t paddr = dma_to_phys(dev, sg_dma_address(sg));
537
538 if (!dev_is_dma_coherent(dev))
539 arch_sync_dma_for_cpu(paddr, sg->length, dir);
540
541 swiotlb_sync_single_for_cpu(dev, paddr, sg->length, dir);
542 }
543
544 if (!dev_is_dma_coherent(dev)) {
545 arch_sync_dma_flush();
546 arch_sync_dma_for_cpu_all();
547 }
548}
549
550/*
551 * Unmaps segments, except for ones marked as pci_p2pdma which do not
552 * require any further action as they contain a bus address.
553 */
554void dma_direct_unmap_sg(struct device *dev, struct scatterlist *sgl,
555 int nents, enum dma_data_direction dir, unsigned long attrs)
556{
557 struct scatterlist *sg;
558 int i;
559 bool need_sync = false;
560
561 for_each_sg(sgl, sg, nents, i) {
562 if (sg_dma_is_bus_address(sg)) {
563 sg_dma_unmark_bus_address(sg);
564 } else {
565 need_sync = true;
566 dma_direct_unmap_phys(dev, sg->dma_address,
567 sg_dma_len(sg), dir, attrs, false);
568 }
569 }
570 if (need_sync && !dev_is_dma_coherent(dev))
571 arch_sync_dma_flush();
572}
573#endif
574
575int dma_direct_map_sg(struct device *dev, struct scatterlist *sgl, int nents,
576 enum dma_data_direction dir, unsigned long attrs)
577{
578 struct pci_p2pdma_map_state p2pdma_state = {};
579 struct scatterlist *sg;
580 int i, ret;
581 bool need_sync = false;
582
583 for_each_sg(sgl, sg, nents, i) {
584 switch (pci_p2pdma_state(&p2pdma_state, dev, sg_page(sg))) {
585 case PCI_P2PDMA_MAP_THRU_HOST_BRIDGE:
586 /*
587 * Any P2P mapping that traverses the PCI host bridge
588 * must be mapped with CPU physical address and not PCI
589 * bus addresses.
590 */
591 fallthrough;
592 case PCI_P2PDMA_MAP_NONE:
593 need_sync = true;
594 sg->dma_address = dma_direct_map_phys(dev, sg_phys(sg),
595 sg->length, dir, attrs, false);
596 if (sg->dma_address == DMA_MAPPING_ERROR) {
597 ret = -EIO;
598 goto out_unmap;
599 }
600 break;
601 case PCI_P2PDMA_MAP_BUS_ADDR:
602 sg->dma_address = pci_p2pdma_bus_addr_map(
603 p2pdma_state.mem, sg_phys(sg));
604 sg_dma_mark_bus_address(sg);
605 break;
606 default:
607 ret = -EREMOTEIO;
608 goto out_unmap;
609 }
610 sg_dma_len(sg) = sg->length;
611 }
612
613 if (need_sync && !dev_is_dma_coherent(dev))
614 arch_sync_dma_flush();
615 return nents;
616
617out_unmap:
618 dma_direct_unmap_sg(dev, sgl, i, dir, attrs | DMA_ATTR_SKIP_CPU_SYNC);
619 return ret;
620}
621
622int dma_direct_get_sgtable(struct device *dev, struct sg_table *sgt,
623 void *cpu_addr, dma_addr_t dma_addr, size_t size,
624 unsigned long attrs)
625{
626 struct page *page = dma_direct_to_page(dev, dma_addr);
627 int ret;
628
629 ret = sg_alloc_table(sgt, 1, GFP_KERNEL);
630 if (!ret)
631 sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0);
632 return ret;
633}
634
635bool dma_direct_can_mmap(struct device *dev)
636{
637 return dev_is_dma_coherent(dev) ||
638 IS_ENABLED(CONFIG_DMA_NONCOHERENT_MMAP);
639}
640
641int dma_direct_mmap(struct device *dev, struct vm_area_struct *vma,
642 void *cpu_addr, dma_addr_t dma_addr, size_t size,
643 unsigned long attrs)
644{
645 unsigned long user_count = vma_pages(vma);
646 unsigned long count = PAGE_ALIGN(size) >> PAGE_SHIFT;
647 unsigned long pfn = PHYS_PFN(dma_to_phys(dev, dma_addr));
648 const pgoff_t pgoff_start = vma_start_pgoff(vma);
649 const pgoff_t pgoff_end = vma_end_pgoff(vma);
650 int ret = -ENXIO;
651
652 if (force_dma_unencrypted(dev))
653 attrs |= DMA_ATTR_CC_SHARED;
654
655 vma->vm_page_prot = dma_pgprot(dev, vma->vm_page_prot, attrs);
656
657 if (dma_mmap_from_dev_coherent(dev, vma, cpu_addr, size, &ret))
658 return ret;
659 if (dma_mmap_from_global_coherent(vma, cpu_addr, size, &ret))
660 return ret;
661
662 if (pgoff_start >= count || pgoff_end > count)
663 return -ENXIO;
664 return remap_pfn_range(vma, vma->vm_start, pfn + pgoff_start,
665 user_count << PAGE_SHIFT, vma->vm_page_prot);
666}
667
668dma_addr_t dma_direct_map_phys(struct device *dev, phys_addr_t phys,
669 size_t size, enum dma_data_direction dir,
670 unsigned long attrs, bool flush)
671{
672 dma_addr_t dma_addr;
673
674 if (attrs & DMA_ATTR_MMIO) {
675 /*
676 * For host memory encryption treat MMIO memory as shared
677 */
678 if (cc_platform_has(CC_ATTR_HOST_MEM_ENCRYPT))
679 attrs |= DMA_ATTR_CC_SHARED;
680 }
681
682 if (is_swiotlb_force_bounce(dev)) {
683 if (attrs & (DMA_ATTR_MMIO | DMA_ATTR_REQUIRE_COHERENT))
684 return DMA_MAPPING_ERROR;
685
686 return swiotlb_map(dev, phys, size, dir, attrs);
687 }
688
689 if (attrs & DMA_ATTR_CC_SHARED)
690 dma_addr = phys_to_dma_unencrypted(dev, phys);
691 else
692 dma_addr = phys_to_dma_encrypted(dev, phys);
693
694 if (attrs & DMA_ATTR_MMIO) {
695 if (unlikely(!dma_capable(dev, dma_addr, size, false, attrs)))
696 goto err_overflow;
697 goto dma_mapped;
698 }
699
700 if (unlikely(!dma_capable(dev, dma_addr, size, true, attrs)) ||
701 dma_kmalloc_needs_bounce(dev, size, dir)) {
702 if (is_swiotlb_active(dev) &&
703 !(attrs & DMA_ATTR_REQUIRE_COHERENT))
704 return swiotlb_map(dev, phys, size, dir, attrs);
705 goto err_overflow;
706 }
707
708dma_mapped:
709 if (!dev_is_dma_coherent(dev) &&
710 !(attrs & (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_MMIO))) {
711 arch_sync_dma_for_device(phys, size, dir);
712 if (flush)
713 arch_sync_dma_flush();
714 }
715 return dma_addr;
716
717err_overflow:
718 dev_WARN_ONCE(
719 dev, 1,
720 "DMA addr %pad+%zu overflow (mask %llx, bus limit %llx).\n",
721 &dma_addr, size, *dev->dma_mask, dev->bus_dma_limit);
722 return DMA_MAPPING_ERROR;
723}
724
725int dma_direct_supported(struct device *dev, u64 mask)
726{
727 u64 min_mask = ((u64)max_pfn << PAGE_SHIFT) - 1;
728
729 /*
730 * Because 32-bit DMA masks are so common we expect every architecture
731 * to be able to satisfy them - either by not supporting more physical
732 * memory, or by providing a ZONE_DMA32. If neither is the case, the
733 * architecture needs to use an IOMMU instead of the direct mapping.
734 */
735 if (mask >= DMA_BIT_MASK(32))
736 return 1;
737
738 /*
739 * This check needs to be against the actual bit mask value, so use
740 * phys_to_dma_unencrypted() here so that the SME encryption mask isn't
741 * part of the check.
742 */
743 if (IS_ENABLED(CONFIG_ZONE_DMA))
744 min_mask = min_t(u64, min_mask, zone_dma_limit);
745 return mask >= phys_to_dma_unencrypted(dev, min_mask);
746}
747
748static const struct bus_dma_region *dma_find_range(struct device *dev,
749 unsigned long start_pfn)
750{
751 const struct bus_dma_region *m;
752
753 for (m = dev->dma_range_map; PFN_DOWN(m->size); m++) {
754 unsigned long cpu_start_pfn = PFN_DOWN(m->cpu_start);
755
756 if (start_pfn >= cpu_start_pfn &&
757 start_pfn - cpu_start_pfn < PFN_DOWN(m->size))
758 return m;
759 }
760
761 return NULL;
762}
763
764/*
765 * To check whether all ram resource ranges are covered by dma range map
766 * Returns 0 when further check is needed
767 * Returns 1 if there is some RAM range can't be covered by dma_range_map
768 */
769static int check_ram_in_range_map(unsigned long start_pfn,
770 unsigned long nr_pages, void *data)
771{
772 unsigned long end_pfn = start_pfn + nr_pages;
773 struct device *dev = data;
774
775 while (start_pfn < end_pfn) {
776 const struct bus_dma_region *bdr;
777
778 bdr = dma_find_range(dev, start_pfn);
779 if (!bdr)
780 return 1;
781
782 start_pfn = PFN_DOWN(bdr->cpu_start) + PFN_DOWN(bdr->size);
783 }
784
785 return 0;
786}
787
788bool dma_direct_all_ram_mapped(struct device *dev)
789{
790 if (!dev->dma_range_map)
791 return true;
792 return !walk_system_ram_range(0, PFN_DOWN(ULONG_MAX) + 1, dev,
793 check_ram_in_range_map);
794}
795
796size_t dma_direct_max_mapping_size(struct device *dev)
797{
798 /* If SWIOTLB is active, use its maximum mapping size */
799 if (is_swiotlb_active(dev) &&
800 (dma_addressing_limited(dev) || is_swiotlb_force_bounce(dev) ||
801 force_dma_unencrypted(dev)))
802 return swiotlb_max_mapping_size(dev);
803
804 return SIZE_MAX;
805}
806
807bool dma_direct_need_sync(struct device *dev, dma_addr_t dma_addr)
808{
809 return !dev_is_dma_coherent(dev) ||
810 swiotlb_find_pool(dev, dma_to_phys(dev, dma_addr));
811}
812
813/**
814 * dma_direct_set_offset - Assign scalar offset for a single DMA range.
815 * @dev: device pointer; needed to "own" the alloced memory.
816 * @cpu_start: beginning of memory region covered by this offset.
817 * @dma_start: beginning of DMA/PCI region covered by this offset.
818 * @size: size of the region.
819 *
820 * This is for the simple case of a uniform offset which cannot
821 * be discovered by "dma-ranges".
822 *
823 * It returns -ENOMEM if out of memory, -EINVAL if a map
824 * already exists, 0 otherwise.
825 *
826 * Note: any call to this from a driver is a bug. The mapping needs
827 * to be described by the device tree or other firmware interfaces.
828 */
829int dma_direct_set_offset(struct device *dev, phys_addr_t cpu_start,
830 dma_addr_t dma_start, u64 size)
831{
832 struct bus_dma_region *map;
833 u64 offset = (u64)cpu_start - (u64)dma_start;
834
835 if (dev->dma_range_map) {
836 dev_err(dev, "attempt to add DMA range to existing map\n");
837 return -EINVAL;
838 }
839
840 if (!offset)
841 return 0;
842
843 map = kzalloc_objs(*map, 2);
844 if (!map)
845 return -ENOMEM;
846 map[0].cpu_start = cpu_start;
847 map[0].dma_start = dma_start;
848 map[0].size = size;
849 dev->dma_range_map = map;
850 return 0;
851}