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1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
2/*
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * Copyright(c) 2017 Intel Corporation
7 *
8 * Author: Liam Girdwood <[email protected]>
9 */
10
11#ifndef __SOF_INTEL_HDA_H
12#define __SOF_INTEL_HDA_H
13
14#include <linux/completion.h>
15#include <linux/soundwire/sdw.h>
16#include <linux/soundwire/sdw_intel.h>
17#include <sound/compress_driver.h>
18#include <sound/hda_codec.h>
19#include <sound/hdaudio_ext.h>
20#include "../sof-client-probes.h"
21#include "../sof-audio.h"
22#include "shim.h"
23
24/* PCI registers */
25#define PCI_TCSEL 0x44
26#define PCI_PGCTL PCI_TCSEL
27#define PCI_CGCTL 0x48
28
29/* PCI_PGCTL bits */
30#define PCI_PGCTL_ADSPPGD BIT(2)
31#define PCI_PGCTL_LSRMD_MASK BIT(4)
32
33/* PCI_CGCTL bits */
34#define PCI_CGCTL_MISCBDCGE_MASK BIT(6)
35#define PCI_CGCTL_ADSPDCGE BIT(1)
36
37/* Legacy HDA registers and bits used - widths are variable */
38#define SOF_HDA_GCAP 0x0
39#define SOF_HDA_GCTL 0x8
40/* accept unsol. response enable */
41#define SOF_HDA_GCTL_UNSOL BIT(8)
42#define SOF_HDA_LLCH 0x14
43#define SOF_HDA_INTCTL 0x20
44#define SOF_HDA_INTSTS 0x24
45#define SOF_HDA_WAKESTS 0x0E
46#define SOF_HDA_WAKESTS_INT_MASK ((1 << 8) - 1)
47#define SOF_HDA_RIRBSTS 0x5d
48
49/* SOF_HDA_GCTL register bist */
50#define SOF_HDA_GCTL_RESET BIT(0)
51
52/* SOF_HDA_INCTL regs */
53#define SOF_HDA_INT_GLOBAL_EN BIT(31)
54#define SOF_HDA_INT_CTRL_EN BIT(30)
55#define SOF_HDA_INT_ALL_STREAM 0xff
56
57/* SOF_HDA_INTSTS regs */
58#define SOF_HDA_INTSTS_GIS BIT(31)
59
60#define SOF_HDA_MAX_CAPS 10
61#define SOF_HDA_CAP_ID_OFF 16
62#define SOF_HDA_CAP_ID_MASK GENMASK(SOF_HDA_CAP_ID_OFF + 11,\
63 SOF_HDA_CAP_ID_OFF)
64#define SOF_HDA_CAP_NEXT_MASK 0xFFFF
65
66#define SOF_HDA_GTS_CAP_ID 0x1
67#define SOF_HDA_ML_CAP_ID 0x2
68
69#define SOF_HDA_PP_CAP_ID 0x3
70#define SOF_HDA_REG_PP_PPCH 0x10
71#define SOF_HDA_REG_PP_PPCTL 0x04
72#define SOF_HDA_REG_PP_PPSTS 0x08
73#define SOF_HDA_PPCTL_PIE BIT(31)
74#define SOF_HDA_PPCTL_GPROCEN BIT(30)
75
76/*Vendor Specific Registers*/
77#define SOF_HDA_VS_D0I3C 0x104A
78
79/* D0I3C Register fields */
80#define SOF_HDA_VS_D0I3C_CIP BIT(0) /* Command-In-Progress */
81#define SOF_HDA_VS_D0I3C_I3 BIT(2) /* D0i3 enable bit */
82
83/* DPIB entry size: 8 Bytes = 2 DWords */
84#define SOF_HDA_DPIB_ENTRY_SIZE 0x8
85
86#define SOF_HDA_SPIB_CAP_ID 0x4
87#define SOF_HDA_DRSM_CAP_ID 0x5
88
89#define SOF_HDA_SPIB_BASE 0x08
90#define SOF_HDA_SPIB_INTERVAL 0x08
91#define SOF_HDA_SPIB_SPIB 0x00
92#define SOF_HDA_SPIB_MAXFIFO 0x04
93
94#define SOF_HDA_PPHC_BASE 0x10
95#define SOF_HDA_PPHC_INTERVAL 0x10
96
97#define SOF_HDA_PPLC_BASE 0x10
98#define SOF_HDA_PPLC_MULTI 0x10
99#define SOF_HDA_PPLC_INTERVAL 0x10
100
101#define SOF_HDA_DRSM_BASE 0x08
102#define SOF_HDA_DRSM_INTERVAL 0x08
103
104/* Descriptor error interrupt */
105#define SOF_HDA_CL_DMA_SD_INT_DESC_ERR 0x10
106
107/* FIFO error interrupt */
108#define SOF_HDA_CL_DMA_SD_INT_FIFO_ERR 0x08
109
110/* Buffer completion interrupt */
111#define SOF_HDA_CL_DMA_SD_INT_COMPLETE 0x04
112
113#define SOF_HDA_CL_DMA_SD_INT_MASK \
114 (SOF_HDA_CL_DMA_SD_INT_DESC_ERR | \
115 SOF_HDA_CL_DMA_SD_INT_FIFO_ERR | \
116 SOF_HDA_CL_DMA_SD_INT_COMPLETE)
117#define SOF_HDA_SD_CTL_DMA_START 0x02 /* Stream DMA start bit */
118
119/* Intel HD Audio Code Loader DMA Registers */
120#define SOF_HDA_ADSP_LOADER_BASE 0x80
121#define SOF_HDA_ADSP_DPLBASE 0x70
122#define SOF_HDA_ADSP_DPUBASE 0x74
123#define SOF_HDA_ADSP_DPLBASE_ENABLE 0x01
124
125/* Stream Registers */
126#define SOF_HDA_ADSP_REG_SD_CTL 0x00
127#define SOF_HDA_ADSP_REG_SD_STS 0x03
128#define SOF_HDA_ADSP_REG_SD_LPIB 0x04
129#define SOF_HDA_ADSP_REG_SD_CBL 0x08
130#define SOF_HDA_ADSP_REG_SD_LVI 0x0C
131#define SOF_HDA_ADSP_REG_SD_FIFOW 0x0E
132#define SOF_HDA_ADSP_REG_SD_FIFOSIZE 0x10
133#define SOF_HDA_ADSP_REG_SD_FORMAT 0x12
134#define SOF_HDA_ADSP_REG_SD_FIFOL 0x14
135#define SOF_HDA_ADSP_REG_SD_BDLPL 0x18
136#define SOF_HDA_ADSP_REG_SD_BDLPU 0x1C
137#define SOF_HDA_ADSP_SD_ENTRY_SIZE 0x20
138
139/* SDxFIFOS FIFOS */
140#define SOF_HDA_SD_FIFOSIZE_FIFOS_MASK GENMASK(15, 0)
141
142/* CL: Software Position Based FIFO Capability Registers */
143#define SOF_DSP_REG_CL_SPBFIFO \
144 (SOF_HDA_ADSP_LOADER_BASE + 0x20)
145#define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCH 0x0
146#define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCCTL 0x4
147#define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPIB 0x8
148#define SOF_HDA_ADSP_REG_CL_SPBFIFO_MAXFIFOS 0xc
149
150/* Stream Number */
151#define SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT 20
152#define SOF_HDA_CL_SD_CTL_STREAM_TAG_MASK \
153 GENMASK(SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT + 3,\
154 SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT)
155
156#define HDA_DSP_HDA_BAR 0
157#define HDA_DSP_PP_BAR 1
158#define HDA_DSP_SPIB_BAR 2
159#define HDA_DSP_DRSM_BAR 3
160#define HDA_DSP_BAR 4
161
162#define SRAM_WINDOW_OFFSET(x) (0x80000 + (x) * 0x20000)
163
164#define HDA_DSP_MBOX_OFFSET SRAM_WINDOW_OFFSET(0)
165
166#define HDA_DSP_PANIC_OFFSET(x) \
167 (((x) & 0xFFFFFF) + HDA_DSP_MBOX_OFFSET)
168
169/* SRAM window 0 FW "registers" */
170#define HDA_DSP_SRAM_REG_ROM_STATUS (HDA_DSP_MBOX_OFFSET + 0x0)
171#define HDA_DSP_SRAM_REG_ROM_ERROR (HDA_DSP_MBOX_OFFSET + 0x4)
172/* FW and ROM share offset 4 */
173#define HDA_DSP_SRAM_REG_FW_STATUS (HDA_DSP_MBOX_OFFSET + 0x4)
174#define HDA_DSP_SRAM_REG_FW_TRACEP (HDA_DSP_MBOX_OFFSET + 0x8)
175#define HDA_DSP_SRAM_REG_FW_END (HDA_DSP_MBOX_OFFSET + 0xc)
176
177#define HDA_DSP_MBOX_UPLINK_OFFSET 0x81000
178
179#define HDA_DSP_STREAM_RESET_TIMEOUT 300
180/*
181 * Timeout in us, for setting the stream RUN bit, during
182 * start/stop the stream. The timeout expires if new RUN bit
183 * value cannot be read back within the specified time.
184 */
185#define HDA_DSP_STREAM_RUN_TIMEOUT 300
186
187#define HDA_DSP_SPIB_ENABLE 1
188#define HDA_DSP_SPIB_DISABLE 0
189
190#define SOF_HDA_MAX_BUFFER_SIZE (32 * PAGE_SIZE)
191
192#define HDA_DSP_STACK_DUMP_SIZE 32
193
194/* ROM/FW status register */
195#define FSR_STATE_MASK GENMASK(23, 0)
196#define FSR_WAIT_STATE_MASK GENMASK(27, 24)
197#define FSR_MODULE_MASK GENMASK(30, 28)
198#define FSR_HALTED BIT(31)
199#define FSR_TO_STATE_CODE(x) ((x) & FSR_STATE_MASK)
200#define FSR_TO_WAIT_STATE_CODE(x) (((x) & FSR_WAIT_STATE_MASK) >> 24)
201#define FSR_TO_MODULE_CODE(x) (((x) & FSR_MODULE_MASK) >> 28)
202
203/* Wait states */
204#define FSR_WAIT_FOR_IPC_BUSY 0x1
205#define FSR_WAIT_FOR_IPC_DONE 0x2
206#define FSR_WAIT_FOR_CACHE_INVALIDATION 0x3
207#define FSR_WAIT_FOR_LP_SRAM_OFF 0x4
208#define FSR_WAIT_FOR_DMA_BUFFER_FULL 0x5
209#define FSR_WAIT_FOR_CSE_CSR 0x6
210
211/* Module codes */
212#define FSR_MOD_ROM 0x0
213#define FSR_MOD_ROM_BYP 0x1
214#define FSR_MOD_BASE_FW 0x2
215#define FSR_MOD_LP_BOOT 0x3
216#define FSR_MOD_BRNGUP 0x4
217#define FSR_MOD_ROM_EXT 0x5
218
219/* State codes (module dependent) */
220/* Module independent states */
221#define FSR_STATE_INIT 0x0
222#define FSR_STATE_INIT_DONE 0x1
223#define FSR_STATE_FW_ENTERED 0x5
224
225/* ROM states */
226#define FSR_STATE_ROM_INIT FSR_STATE_INIT
227#define FSR_STATE_ROM_INIT_DONE FSR_STATE_INIT_DONE
228#define FSR_STATE_ROM_CSE_MANIFEST_LOADED 0x2
229#define FSR_STATE_ROM_FW_MANIFEST_LOADED 0x3
230#define FSR_STATE_ROM_FW_FW_LOADED 0x4
231#define FSR_STATE_ROM_FW_ENTERED FSR_STATE_FW_ENTERED
232#define FSR_STATE_ROM_VERIFY_FEATURE_MASK 0x6
233#define FSR_STATE_ROM_GET_LOAD_OFFSET 0x7
234#define FSR_STATE_ROM_FETCH_ROM_EXT 0x8
235#define FSR_STATE_ROM_FETCH_ROM_EXT_DONE 0x9
236#define FSR_STATE_ROM_BASEFW_ENTERED 0xf /* SKL */
237
238/* (ROM) CSE states */
239#define FSR_STATE_ROM_CSE_IMR_REQUEST 0x10
240#define FSR_STATE_ROM_CSE_IMR_GRANTED 0x11
241#define FSR_STATE_ROM_CSE_VALIDATE_IMAGE_REQUEST 0x12
242#define FSR_STATE_ROM_CSE_IMAGE_VALIDATED 0x13
243
244#define FSR_STATE_ROM_CSE_IPC_IFACE_INIT 0x20
245#define FSR_STATE_ROM_CSE_IPC_RESET_PHASE_1 0x21
246#define FSR_STATE_ROM_CSE_IPC_OPERATIONAL_ENTRY 0x22
247#define FSR_STATE_ROM_CSE_IPC_OPERATIONAL 0x23
248#define FSR_STATE_ROM_CSE_IPC_DOWN 0x24
249
250/* BRINGUP (or BRNGUP) states */
251#define FSR_STATE_BRINGUP_INIT FSR_STATE_INIT
252#define FSR_STATE_BRINGUP_INIT_DONE FSR_STATE_INIT_DONE
253#define FSR_STATE_BRINGUP_HPSRAM_LOAD 0x2
254#define FSR_STATE_BRINGUP_UNPACK_START 0X3
255#define FSR_STATE_BRINGUP_IMR_RESTORE 0x4
256#define FSR_STATE_BRINGUP_FW_ENTERED FSR_STATE_FW_ENTERED
257
258/* ROM status/error values */
259#define HDA_DSP_ROM_CSE_ERROR 40
260#define HDA_DSP_ROM_CSE_WRONG_RESPONSE 41
261#define HDA_DSP_ROM_IMR_TO_SMALL 42
262#define HDA_DSP_ROM_BASE_FW_NOT_FOUND 43
263#define HDA_DSP_ROM_CSE_VALIDATION_FAILED 44
264#define HDA_DSP_ROM_IPC_FATAL_ERROR 45
265#define HDA_DSP_ROM_L2_CACHE_ERROR 46
266#define HDA_DSP_ROM_LOAD_OFFSET_TO_SMALL 47
267#define HDA_DSP_ROM_API_PTR_INVALID 50
268#define HDA_DSP_ROM_BASEFW_INCOMPAT 51
269#define HDA_DSP_ROM_UNHANDLED_INTERRUPT 0xBEE00000
270#define HDA_DSP_ROM_MEMORY_HOLE_ECC 0xECC00000
271#define HDA_DSP_ROM_KERNEL_EXCEPTION 0xCAFE0000
272#define HDA_DSP_ROM_USER_EXCEPTION 0xBEEF0000
273#define HDA_DSP_ROM_UNEXPECTED_RESET 0xDECAF000
274#define HDA_DSP_ROM_NULL_FW_ENTRY 0x4c4c4e55
275
276#define HDA_DSP_ROM_IPC_CONTROL 0x01000000
277#define HDA_DSP_ROM_IPC_PURGE_FW 0x00004000
278
279/* various timeout values */
280#define HDA_DSP_PU_TIMEOUT 50
281#define HDA_DSP_PD_TIMEOUT 50
282#define HDA_DSP_RESET_TIMEOUT_US 50000
283#define HDA_DSP_BASEFW_TIMEOUT_US 3000000
284#define HDA_DSP_INIT_TIMEOUT_US 500000
285#define HDA_DSP_CTRL_RESET_TIMEOUT 100
286#define HDA_DSP_WAIT_TIMEOUT 500 /* 500 msec */
287#define HDA_DSP_REG_POLL_INTERVAL_US 500 /* 0.5 msec */
288#define HDA_DSP_REG_POLL_RETRY_COUNT 50
289
290#define HDA_DSP_ADSPIC_IPC BIT(0)
291#define HDA_DSP_ADSPIS_IPC BIT(0)
292
293/* Intel HD Audio General DSP Registers */
294#define HDA_DSP_GEN_BASE 0x0
295#define HDA_DSP_REG_ADSPCS (HDA_DSP_GEN_BASE + 0x04)
296#define HDA_DSP_REG_ADSPIC (HDA_DSP_GEN_BASE + 0x08)
297#define HDA_DSP_REG_ADSPIS (HDA_DSP_GEN_BASE + 0x0C)
298#define HDA_DSP_REG_ADSPIC2 (HDA_DSP_GEN_BASE + 0x10)
299#define HDA_DSP_REG_ADSPIS2 (HDA_DSP_GEN_BASE + 0x14)
300
301#define HDA_DSP_REG_ADSPIC2_SNDW BIT(5)
302#define HDA_DSP_REG_ADSPIS2_SNDW BIT(5)
303
304/* Intel HD Audio Inter-Processor Communication Registers */
305#define HDA_DSP_IPC_BASE 0x40
306#define HDA_DSP_REG_HIPCT (HDA_DSP_IPC_BASE + 0x00)
307#define HDA_DSP_REG_HIPCTE (HDA_DSP_IPC_BASE + 0x04)
308#define HDA_DSP_REG_HIPCI (HDA_DSP_IPC_BASE + 0x08)
309#define HDA_DSP_REG_HIPCIE (HDA_DSP_IPC_BASE + 0x0C)
310#define HDA_DSP_REG_HIPCCTL (HDA_DSP_IPC_BASE + 0x10)
311
312/* Intel Vendor Specific Registers */
313#define HDA_VS_INTEL_EM2 0x1030
314#define HDA_VS_INTEL_EM2_L1SEN BIT(13)
315#define HDA_VS_INTEL_LTRP 0x1048
316#define HDA_VS_INTEL_LTRP_GB_MASK 0x3F
317
318/* HIPCI */
319#define HDA_DSP_REG_HIPCI_BUSY BIT(31)
320#define HDA_DSP_REG_HIPCI_MSG_MASK 0x7FFFFFFF
321
322/* HIPCIE */
323#define HDA_DSP_REG_HIPCIE_DONE BIT(30)
324#define HDA_DSP_REG_HIPCIE_MSG_MASK 0x3FFFFFFF
325
326/* HIPCCTL */
327#define HDA_DSP_REG_HIPCCTL_DONE BIT(1)
328#define HDA_DSP_REG_HIPCCTL_BUSY BIT(0)
329
330/* HIPCT */
331#define HDA_DSP_REG_HIPCT_BUSY BIT(31)
332#define HDA_DSP_REG_HIPCT_MSG_MASK 0x7FFFFFFF
333
334/* HIPCTE */
335#define HDA_DSP_REG_HIPCTE_MSG_MASK 0x3FFFFFFF
336
337#define HDA_DSP_ADSPIC_CL_DMA BIT(1)
338#define HDA_DSP_ADSPIS_CL_DMA BIT(1)
339
340/* Delay before scheduling D0i3 entry */
341#define BXT_D0I3_DELAY 5000
342
343#define FW_CL_STREAM_NUMBER 0x1
344#define HDA_FW_BOOT_ATTEMPTS 3
345
346/* ADSPCS - Audio DSP Control & Status */
347
348/*
349 * Core Reset - asserted high
350 * CRST Mask for a given core mask pattern, cm
351 */
352#define HDA_DSP_ADSPCS_CRST_SHIFT 0
353#define HDA_DSP_ADSPCS_CRST_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CRST_SHIFT)
354
355/*
356 * Core run/stall - when set to '1' core is stalled
357 * CSTALL Mask for a given core mask pattern, cm
358 */
359#define HDA_DSP_ADSPCS_CSTALL_SHIFT 8
360#define HDA_DSP_ADSPCS_CSTALL_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CSTALL_SHIFT)
361
362/*
363 * Set Power Active - when set to '1' turn cores on
364 * SPA Mask for a given core mask pattern, cm
365 */
366#define HDA_DSP_ADSPCS_SPA_SHIFT 16
367#define HDA_DSP_ADSPCS_SPA_MASK(cm) ((cm) << HDA_DSP_ADSPCS_SPA_SHIFT)
368
369/*
370 * Current Power Active - power status of cores, set by hardware
371 * CPA Mask for a given core mask pattern, cm
372 */
373#define HDA_DSP_ADSPCS_CPA_SHIFT 24
374#define HDA_DSP_ADSPCS_CPA_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CPA_SHIFT)
375
376/*
377 * Mask for a given number of cores
378 * nc = number of supported cores
379 */
380#define SOF_DSP_CORES_MASK(nc) GENMASK(((nc) - 1), 0)
381
382/* Intel HD Audio Inter-Processor Communication Registers for Cannonlake*/
383#define CNL_DSP_IPC_BASE 0xc0
384#define CNL_DSP_REG_HIPCTDR (CNL_DSP_IPC_BASE + 0x00)
385#define CNL_DSP_REG_HIPCTDA (CNL_DSP_IPC_BASE + 0x04)
386#define CNL_DSP_REG_HIPCTDD (CNL_DSP_IPC_BASE + 0x08)
387#define CNL_DSP_REG_HIPCIDR (CNL_DSP_IPC_BASE + 0x10)
388#define CNL_DSP_REG_HIPCIDA (CNL_DSP_IPC_BASE + 0x14)
389#define CNL_DSP_REG_HIPCIDD (CNL_DSP_IPC_BASE + 0x18)
390#define CNL_DSP_REG_HIPCCTL (CNL_DSP_IPC_BASE + 0x28)
391
392/* HIPCI */
393#define CNL_DSP_REG_HIPCIDR_BUSY BIT(31)
394#define CNL_DSP_REG_HIPCIDR_MSG_MASK 0x7FFFFFFF
395
396/* HIPCIE */
397#define CNL_DSP_REG_HIPCIDA_DONE BIT(31)
398#define CNL_DSP_REG_HIPCIDA_MSG_MASK 0x7FFFFFFF
399
400/* HIPCCTL */
401#define CNL_DSP_REG_HIPCCTL_DONE BIT(1)
402#define CNL_DSP_REG_HIPCCTL_BUSY BIT(0)
403
404/* HIPCT */
405#define CNL_DSP_REG_HIPCTDR_BUSY BIT(31)
406#define CNL_DSP_REG_HIPCTDR_MSG_MASK 0x7FFFFFFF
407
408/* HIPCTDA */
409#define CNL_DSP_REG_HIPCTDA_DONE BIT(31)
410#define CNL_DSP_REG_HIPCTDA_MSG_MASK 0x7FFFFFFF
411
412/* HIPCTDD */
413#define CNL_DSP_REG_HIPCTDD_MSG_MASK 0x7FFFFFFF
414
415/* BDL */
416#define HDA_DSP_BDL_SIZE 4096
417#define HDA_DSP_MAX_BDL_ENTRIES \
418 (HDA_DSP_BDL_SIZE / sizeof(struct sof_intel_dsp_bdl))
419
420/* Number of DAIs */
421#define SOF_SKL_NUM_DAIS_NOCODEC 9
422
423#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC)
424#define SOF_SKL_NUM_DAIS 16
425#else
426#define SOF_SKL_NUM_DAIS SOF_SKL_NUM_DAIS_NOCODEC
427#endif
428
429/* Intel HD Audio SRAM Window 0*/
430#define HDA_DSP_SRAM_REG_ROM_STATUS_SKL 0x8000
431#define HDA_ADSP_SRAM0_BASE_SKL 0x8000
432
433/* Firmware status window */
434#define HDA_ADSP_FW_STATUS_SKL HDA_ADSP_SRAM0_BASE_SKL
435#define HDA_ADSP_ERROR_CODE_SKL (HDA_ADSP_FW_STATUS_SKL + 0x4)
436
437/* Host Device Memory Space */
438#define APL_SSP_BASE_OFFSET 0x2000
439#define CNL_SSP_BASE_OFFSET 0x10000
440
441/* Host Device Memory Size of a Single SSP */
442#define SSP_DEV_MEM_SIZE 0x1000
443
444/* SSP Count of the Platform */
445#define APL_SSP_COUNT 6
446#define CNL_SSP_COUNT 3
447#define ICL_SSP_COUNT 6
448#define TGL_SSP_COUNT 3
449#define MTL_SSP_COUNT 3
450
451/* SSP Registers */
452#define SSP_SSC1_OFFSET 0x4
453#define SSP_SET_SCLK_CONSUMER BIT(25)
454#define SSP_SET_SFRM_CONSUMER BIT(24)
455#define SSP_SET_CBP_CFP (SSP_SET_SCLK_CONSUMER | SSP_SET_SFRM_CONSUMER)
456
457#define HDA_EXT_ADDR 0
458#define HDA_EXT_CODEC(x) ((x) & BIT(HDA_EXT_ADDR))
459#define HDA_IDISP_ADDR 2
460#define HDA_IDISP_CODEC(x) ((x) & BIT(HDA_IDISP_ADDR))
461
462struct sof_intel_dsp_bdl {
463 __le32 addr_l;
464 __le32 addr_h;
465 __le32 size;
466 __le32 ioc;
467} __attribute((packed));
468
469#define SOF_HDA_PLAYBACK_STREAMS 16
470#define SOF_HDA_CAPTURE_STREAMS 16
471#define SOF_HDA_PLAYBACK 0
472#define SOF_HDA_CAPTURE 1
473
474/* stream flags */
475#define SOF_HDA_STREAM_DMI_L1_COMPATIBLE 1
476
477/*
478 * Time in ms for opportunistic D0I3 entry delay.
479 * This has been deliberately chosen to be long to avoid race conditions.
480 * Could be optimized in future.
481 */
482#define SOF_HDA_D0I3_WORK_DELAY_MS 5000
483
484/* HDA DSP D0 substate */
485enum sof_hda_D0_substate {
486 SOF_HDA_DSP_PM_D0I0, /* default D0 substate */
487 SOF_HDA_DSP_PM_D0I3, /* low power D0 substate */
488};
489
490struct sof_ace3_mic_privacy {
491 bool active;
492 struct work_struct work;
493};
494
495/* represents DSP HDA controller frontend - i.e. host facing control */
496struct sof_intel_hda_dev {
497 bool imrboot_supported;
498 bool skip_imr_boot;
499 bool booted_from_imr;
500
501 int boot_iteration;
502
503 /*
504 * DMA buffers for base firmware download. By default the buffers are
505 * allocated once and kept through the lifetime of the driver.
506 * See module parameter: persistent_cl_buffer
507 */
508 struct snd_dma_buffer cl_dmab;
509 bool cl_dmab_contains_basefw;
510 struct snd_dma_buffer iccmax_dmab;
511
512 struct hda_bus hbus;
513
514 /* hw config */
515 const struct sof_intel_dsp_desc *desc;
516
517 /* trace */
518 struct hdac_ext_stream *dtrace_stream;
519
520 /* if position update IPC needed */
521 u32 no_ipc_position;
522
523 /* the maximum number of streams (playback + capture) supported */
524 u32 stream_max;
525
526 /*
527 * ACE2+ link DMA stream allocation constraints (stream index =
528 * stream_tag - 1, shared between input and output directions). All
529 * masks are cleared by hda_dsp_ctrl_init_chip() on controller reset
530 * (CRST#).
531 *
532 * - Concurrent (cross-direction) constraint: a SoundWire stream and
533 * a HDA/iDisp/UAOL stream cannot share a physical stream index
534 * across directions, the resulting LLP/timestamp values are wrong.
535 * link_dma_active_sdw_mask and link_dma_active_multi_mask
536 * (indexed by SNDRV_PCM_STREAM_*) track currently allocated
537 * streams per direction in each of the conflicting groups; SSP
538 * and DMIC do not participate. Bits are cleared on stream release.
539 *
540 * - Sequential (playback only) constraint: once a HDA/iDisp link
541 * has used a playback stream index, that index cannot drive a
542 * non-HDA/iDisp link in the same direction until the next CRST#.
543 * link_dma_out_hda_used_mask records this.
544 */
545 u32 link_dma_active_sdw_mask[SNDRV_PCM_STREAM_LAST + 1];
546 u32 link_dma_active_multi_mask[SNDRV_PCM_STREAM_LAST + 1];
547 u32 link_dma_out_hda_used_mask;
548
549 /* PM related */
550 bool l1_disabled;/* is DMI link L1 disabled? */
551
552 /* DMIC device */
553 struct platform_device *dmic_dev;
554
555 /* delayed work to enter D0I3 opportunistically */
556 struct delayed_work d0i3_work;
557
558 /* ACPI information stored between scan and probe steps */
559 struct sdw_intel_acpi_info info;
560
561 /* sdw context allocated by SoundWire driver */
562 struct sdw_intel_ctx *sdw;
563
564 /* FW clock config, 0:HPRO, 1:LPRO */
565 bool clk_config_lpro;
566
567 wait_queue_head_t waitq;
568 bool code_loading;
569
570 /* Intel NHLT information */
571 struct nhlt_acpi_table *nhlt;
572
573 /* work queue for mic privacy state change notification sending */
574 struct sof_ace3_mic_privacy mic_privacy;
575
576 /*
577 * Pointing to the IPC message if immediate sending was not possible
578 * because the downlink communication channel was BUSY at the time.
579 * The message will be re-tried when the channel becomes free (the ACK
580 * is received from the DSP for the previous message)
581 */
582 struct snd_sof_ipc_msg *delayed_ipc_tx_msg;
583};
584
585static inline struct hdac_bus *sof_to_bus(struct snd_sof_dev *s)
586{
587 struct sof_intel_hda_dev *hda = s->pdata->hw_pdata;
588
589 return &hda->hbus.core;
590}
591
592static inline struct hda_bus *sof_to_hbus(struct snd_sof_dev *s)
593{
594 struct sof_intel_hda_dev *hda = s->pdata->hw_pdata;
595
596 return &hda->hbus;
597}
598
599struct sof_intel_hda_stream {
600 struct snd_sof_dev *sdev;
601 struct hdac_ext_stream hext_stream;
602 struct sof_intel_stream sof_intel_stream;
603 int host_reserved; /* reserve host DMA channel */
604 u32 flags;
605 struct completion ioc;
606};
607
608#define hstream_to_sof_hda_stream(hstream) \
609 container_of(hstream, struct sof_intel_hda_stream, hext_stream)
610
611#define bus_to_sof_hda(bus) \
612 container_of(bus, struct sof_intel_hda_dev, hbus.core)
613
614#define SOF_STREAM_SD_OFFSET(s) \
615 (SOF_HDA_ADSP_SD_ENTRY_SIZE * ((s)->index) \
616 + SOF_HDA_ADSP_LOADER_BASE)
617
618#define SOF_STREAM_SD_OFFSET_CRST 0x1
619
620/*
621 * DAI support
622 */
623bool hda_is_chain_dma_supported(struct snd_sof_dev *sdev, u32 dai_type);
624
625/*
626 * DSP Core services.
627 */
628int hda_dsp_probe_early(struct snd_sof_dev *sdev);
629int hda_dsp_probe(struct snd_sof_dev *sdev);
630void hda_dsp_remove(struct snd_sof_dev *sdev);
631void hda_dsp_remove_late(struct snd_sof_dev *sdev);
632int hda_dsp_core_power_up(struct snd_sof_dev *sdev, unsigned int core_mask);
633int hda_dsp_core_run(struct snd_sof_dev *sdev, unsigned int core_mask);
634int hda_dsp_enable_core(struct snd_sof_dev *sdev, unsigned int core_mask);
635int hda_dsp_core_reset_power_down(struct snd_sof_dev *sdev,
636 unsigned int core_mask);
637int hda_power_down_dsp(struct snd_sof_dev *sdev);
638int hda_dsp_core_get(struct snd_sof_dev *sdev, int core);
639void hda_dsp_ipc_int_enable(struct snd_sof_dev *sdev);
640void hda_dsp_ipc_int_disable(struct snd_sof_dev *sdev);
641bool hda_dsp_core_is_enabled(struct snd_sof_dev *sdev, unsigned int core_mask);
642
643int hda_dsp_set_power_state_ipc3(struct snd_sof_dev *sdev,
644 const struct sof_dsp_power_state *target_state);
645int hda_dsp_set_power_state_ipc4(struct snd_sof_dev *sdev,
646 const struct sof_dsp_power_state *target_state);
647
648int hda_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state);
649int hda_dsp_resume(struct snd_sof_dev *sdev);
650int hda_dsp_runtime_suspend(struct snd_sof_dev *sdev);
651int hda_dsp_runtime_resume(struct snd_sof_dev *sdev);
652int hda_dsp_runtime_idle(struct snd_sof_dev *sdev);
653int hda_dsp_shutdown_dma_flush(struct snd_sof_dev *sdev);
654int hda_dsp_shutdown(struct snd_sof_dev *sdev);
655int hda_dsp_set_hw_params_upon_resume(struct snd_sof_dev *sdev);
656void hda_dsp_dump(struct snd_sof_dev *sdev, u32 flags);
657void hda_ipc4_dsp_dump(struct snd_sof_dev *sdev, u32 flags);
658void hda_ipc_dump(struct snd_sof_dev *sdev);
659void hda_ipc_irq_dump(struct snd_sof_dev *sdev);
660void hda_dsp_d0i3_work(struct work_struct *work);
661int hda_dsp_disable_interrupts(struct snd_sof_dev *sdev);
662bool hda_check_ipc_irq(struct snd_sof_dev *sdev);
663u32 hda_get_interface_mask(struct snd_sof_dev *sdev);
664
665/*
666 * DSP PCM Operations.
667 */
668u32 hda_dsp_get_mult_div(struct snd_sof_dev *sdev, int rate);
669u32 hda_dsp_get_bits(struct snd_sof_dev *sdev, int sample_bits);
670int hda_dsp_pcm_open(struct snd_sof_dev *sdev,
671 struct snd_pcm_substream *substream);
672int hda_dsp_pcm_close(struct snd_sof_dev *sdev,
673 struct snd_pcm_substream *substream);
674int hda_dsp_pcm_hw_params(struct snd_sof_dev *sdev,
675 struct snd_pcm_substream *substream,
676 struct snd_pcm_hw_params *params,
677 struct snd_sof_platform_stream_params *platform_params);
678int hda_dsp_stream_hw_free(struct snd_sof_dev *sdev,
679 struct snd_pcm_substream *substream);
680int hda_dsp_pcm_trigger(struct snd_sof_dev *sdev,
681 struct snd_pcm_substream *substream, int cmd);
682snd_pcm_uframes_t hda_dsp_pcm_pointer(struct snd_sof_dev *sdev,
683 struct snd_pcm_substream *substream);
684int hda_dsp_pcm_ack(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream);
685
686/*
687 * DSP Stream Operations.
688 */
689
690int hda_dsp_stream_init(struct snd_sof_dev *sdev);
691void hda_dsp_stream_free(struct snd_sof_dev *sdev);
692int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev,
693 struct hdac_ext_stream *hext_stream,
694 struct snd_dma_buffer *dmab,
695 struct snd_pcm_hw_params *params);
696int hda_dsp_iccmax_stream_hw_params(struct snd_sof_dev *sdev,
697 struct hdac_ext_stream *hext_stream,
698 struct snd_dma_buffer *dmab,
699 struct snd_pcm_hw_params *params);
700int hda_dsp_stream_trigger(struct snd_sof_dev *sdev,
701 struct hdac_ext_stream *hext_stream, int cmd);
702irqreturn_t hda_dsp_stream_threaded_handler(int irq, void *context);
703int hda_dsp_stream_setup_bdl(struct snd_sof_dev *sdev,
704 struct snd_dma_buffer *dmab,
705 struct hdac_stream *hstream);
706bool hda_dsp_check_ipc_irq(struct snd_sof_dev *sdev);
707bool hda_dsp_check_stream_irq(struct snd_sof_dev *sdev);
708
709snd_pcm_uframes_t hda_dsp_stream_get_position(struct hdac_stream *hstream,
710 int direction, bool can_sleep);
711u64 hda_dsp_get_stream_llp(struct snd_sof_dev *sdev,
712 struct snd_soc_component *component,
713 struct snd_pcm_substream *substream);
714u64 hda_dsp_get_stream_ldp(struct snd_sof_dev *sdev,
715 struct snd_soc_component *component,
716 struct snd_pcm_substream *substream);
717
718struct hdac_ext_stream *
719 hda_dsp_stream_get(struct snd_sof_dev *sdev, int direction, u32 flags);
720struct hdac_ext_stream *
721 hda_dsp_stream_pair_get(struct snd_sof_dev *sdev, int direction, u32 flags);
722int hda_dsp_stream_put(struct snd_sof_dev *sdev, int direction, int stream_tag);
723int hda_dsp_stream_pair_put(struct snd_sof_dev *sdev, int direction, int stream_tag);
724int hda_dsp_stream_spib_config(struct snd_sof_dev *sdev,
725 struct hdac_ext_stream *hext_stream,
726 int enable, u32 size);
727
728int hda_ipc_msg_data(struct snd_sof_dev *sdev,
729 struct snd_sof_pcm_stream *sps,
730 void *p, size_t sz);
731int hda_set_stream_data_offset(struct snd_sof_dev *sdev,
732 struct snd_sof_pcm_stream *sps,
733 size_t posn_offset);
734
735/*
736 * DSP IPC Operations.
737 */
738int hda_dsp_ipc_send_msg(struct snd_sof_dev *sdev,
739 struct snd_sof_ipc_msg *msg);
740void hda_dsp_ipc_get_reply(struct snd_sof_dev *sdev);
741int hda_dsp_ipc_get_mailbox_offset(struct snd_sof_dev *sdev);
742int hda_dsp_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id);
743
744irqreturn_t hda_dsp_ipc_irq_thread(int irq, void *context);
745int hda_dsp_ipc_cmd_done(struct snd_sof_dev *sdev, int dir);
746
747void hda_dsp_get_state(struct snd_sof_dev *sdev, const char *level);
748void hda_dsp_dump_ext_rom_status(struct snd_sof_dev *sdev, const char *level,
749 u32 flags);
750
751/*
752 * DSP Code loader.
753 */
754int hda_dsp_cl_boot_firmware(struct snd_sof_dev *sdev);
755int hda_dsp_cl_boot_firmware_iccmax(struct snd_sof_dev *sdev);
756int hda_cl_copy_fw(struct snd_sof_dev *sdev, struct hdac_ext_stream *hext_stream);
757
758struct hdac_ext_stream *hda_cl_prepare(struct device *dev, unsigned int format,
759 unsigned int size, struct snd_dma_buffer *dmab,
760 bool persistent_buffer, int direction,
761 bool is_iccmax);
762int hda_cl_trigger(struct device *dev, struct hdac_ext_stream *hext_stream, int cmd);
763
764int hda_cl_cleanup(struct device *dev, struct snd_dma_buffer *dmab,
765 bool persistent_buffer, struct hdac_ext_stream *hext_stream, bool is_iccmax);
766int cl_dsp_init(struct snd_sof_dev *sdev, int stream_tag, bool imr_boot);
767#define HDA_CL_STREAM_FORMAT 0x40
768
769/* pre and post fw run ops */
770int hda_dsp_pre_fw_run(struct snd_sof_dev *sdev);
771int hda_dsp_post_fw_run(struct snd_sof_dev *sdev);
772
773/* parse platform specific ext manifest ops */
774int hda_dsp_ext_man_get_cavs_config_data(struct snd_sof_dev *sdev,
775 const struct sof_ext_man_elem_header *hdr);
776
777/*
778 * HDA Controller Operations.
779 */
780int hda_dsp_ctrl_get_caps(struct snd_sof_dev *sdev);
781void hda_dsp_ctrl_ppcap_enable(struct snd_sof_dev *sdev, bool enable);
782void hda_dsp_ctrl_ppcap_int_enable(struct snd_sof_dev *sdev, bool enable);
783int hda_dsp_ctrl_link_reset(struct snd_sof_dev *sdev, bool reset);
784void hda_dsp_ctrl_misc_clock_gating(struct snd_sof_dev *sdev, bool enable);
785int hda_dsp_ctrl_clock_power_gating(struct snd_sof_dev *sdev, bool enable);
786int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev, bool detect_codec);
787void hda_dsp_ctrl_stop_chip(struct snd_sof_dev *sdev);
788/*
789 * HDA bus operations.
790 */
791void sof_hda_bus_init(struct snd_sof_dev *sdev, struct device *dev);
792void sof_hda_bus_exit(struct snd_sof_dev *sdev);
793
794#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC)
795/*
796 * HDA Codec operations.
797 */
798void hda_codec_probe_bus(struct snd_sof_dev *sdev);
799void hda_codec_jack_wake_enable(struct snd_sof_dev *sdev, bool enable);
800void hda_codec_jack_check(struct snd_sof_dev *sdev);
801void hda_codec_check_for_state_change(struct snd_sof_dev *sdev);
802void hda_codec_init_cmd_io(struct snd_sof_dev *sdev);
803void hda_codec_resume_cmd_io(struct snd_sof_dev *sdev);
804void hda_codec_stop_cmd_io(struct snd_sof_dev *sdev);
805void hda_codec_suspend_cmd_io(struct snd_sof_dev *sdev);
806void hda_codec_detect_mask(struct snd_sof_dev *sdev);
807void hda_codec_rirb_status_clear(struct snd_sof_dev *sdev);
808bool hda_codec_check_rirb_status(struct snd_sof_dev *sdev);
809void hda_codec_set_codec_wakeup(struct snd_sof_dev *sdev, bool status);
810void hda_codec_device_remove(struct snd_sof_dev *sdev);
811
812#else
813
814static inline void hda_codec_probe_bus(struct snd_sof_dev *sdev) { }
815static inline void hda_codec_jack_wake_enable(struct snd_sof_dev *sdev, bool enable) { }
816static inline void hda_codec_jack_check(struct snd_sof_dev *sdev) { }
817static inline void hda_codec_check_for_state_change(struct snd_sof_dev *sdev) { }
818static inline void hda_codec_init_cmd_io(struct snd_sof_dev *sdev) { }
819static inline void hda_codec_resume_cmd_io(struct snd_sof_dev *sdev) { }
820static inline void hda_codec_stop_cmd_io(struct snd_sof_dev *sdev) { }
821static inline void hda_codec_suspend_cmd_io(struct snd_sof_dev *sdev) { }
822static inline void hda_codec_detect_mask(struct snd_sof_dev *sdev) { }
823static inline void hda_codec_rirb_status_clear(struct snd_sof_dev *sdev) { }
824static inline bool hda_codec_check_rirb_status(struct snd_sof_dev *sdev) { return false; }
825static inline void hda_codec_set_codec_wakeup(struct snd_sof_dev *sdev, bool status) { }
826static inline void hda_codec_device_remove(struct snd_sof_dev *sdev) { }
827
828#endif /* CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC */
829
830#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC) && IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
831
832void hda_codec_i915_display_power(struct snd_sof_dev *sdev, bool enable);
833int hda_codec_i915_init(struct snd_sof_dev *sdev);
834int hda_codec_i915_exit(struct snd_sof_dev *sdev);
835
836#else
837
838static inline void hda_codec_i915_display_power(struct snd_sof_dev *sdev, bool enable) { }
839static inline int hda_codec_i915_init(struct snd_sof_dev *sdev) { return 0; }
840static inline int hda_codec_i915_exit(struct snd_sof_dev *sdev) { return 0; }
841
842#endif
843
844/*
845 * Trace Control.
846 */
847int hda_dsp_trace_init(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab,
848 struct sof_ipc_dma_trace_params_ext *dtrace_params);
849int hda_dsp_trace_release(struct snd_sof_dev *sdev);
850int hda_dsp_trace_trigger(struct snd_sof_dev *sdev, int cmd);
851
852/*
853 * SoundWire support
854 */
855#if IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE)
856
857int hda_sdw_check_lcount_common(struct snd_sof_dev *sdev);
858int hda_sdw_check_lcount_ext(struct snd_sof_dev *sdev);
859int hda_sdw_check_lcount(struct snd_sof_dev *sdev);
860int hda_sdw_startup(struct snd_sof_dev *sdev);
861void hda_common_enable_sdw_irq(struct snd_sof_dev *sdev, bool enable);
862void hda_sdw_int_enable(struct snd_sof_dev *sdev, bool enable);
863bool hda_sdw_check_wakeen_irq_common(struct snd_sof_dev *sdev);
864void hda_sdw_process_wakeen_common(struct snd_sof_dev *sdev);
865void hda_sdw_process_wakeen(struct snd_sof_dev *sdev);
866bool hda_common_check_sdw_irq(struct snd_sof_dev *sdev);
867
868#else
869
870static inline int hda_sdw_check_lcount_common(struct snd_sof_dev *sdev)
871{
872 return 0;
873}
874
875static inline int hda_sdw_check_lcount_ext(struct snd_sof_dev *sdev)
876{
877 return 0;
878}
879
880static inline int hda_sdw_check_lcount(struct snd_sof_dev *sdev)
881{
882 return 0;
883}
884
885static inline int hda_sdw_startup(struct snd_sof_dev *sdev)
886{
887 return 0;
888}
889
890static inline void hda_common_enable_sdw_irq(struct snd_sof_dev *sdev, bool enable)
891{
892}
893
894static inline void hda_sdw_int_enable(struct snd_sof_dev *sdev, bool enable)
895{
896}
897
898static inline bool hda_sdw_check_wakeen_irq_common(struct snd_sof_dev *sdev)
899{
900 return false;
901}
902
903static inline void hda_sdw_process_wakeen_common(struct snd_sof_dev *sdev)
904{
905}
906
907static inline void hda_sdw_process_wakeen(struct snd_sof_dev *sdev)
908{
909}
910
911static inline bool hda_common_check_sdw_irq(struct snd_sof_dev *sdev)
912{
913 return false;
914}
915
916#endif
917
918int sdw_hda_dai_hw_params(struct snd_pcm_substream *substream,
919 struct snd_pcm_hw_params *params,
920 struct snd_soc_dai *cpu_dai,
921 int link_id,
922 int intel_alh_id);
923
924int sdw_hda_dai_hw_free(struct snd_pcm_substream *substream,
925 struct snd_soc_dai *cpu_dai,
926 int link_id);
927
928int sdw_hda_dai_trigger(struct snd_pcm_substream *substream, int cmd,
929 struct snd_soc_dai *cpu_dai);
930
931struct hdac_ext_stream *
932hda_data_stream_prepare(struct device *dev, unsigned int format, unsigned int size,
933 struct snd_dma_buffer *dmab, bool persistent_buffer, int direction,
934 bool is_iccmax, bool pair);
935
936int hda_data_stream_cleanup(struct device *dev, struct snd_dma_buffer *dmab,
937 bool persistent_buffer, struct hdac_ext_stream *hext_stream,
938 bool is_iccmax, bool pair);
939
940/* common dai driver */
941extern struct snd_soc_dai_driver skl_dai[];
942int hda_dsp_dais_suspend(struct snd_sof_dev *sdev);
943
944/*
945 * Platform Specific HW abstraction Ops.
946 */
947extern const struct snd_sof_dsp_ops sof_hda_common_ops;
948
949extern struct snd_sof_dsp_ops sof_skl_ops;
950int sof_skl_ops_init(struct snd_sof_dev *sdev);
951extern struct snd_sof_dsp_ops sof_apl_ops;
952int sof_apl_ops_init(struct snd_sof_dev *sdev);
953extern struct snd_sof_dsp_ops sof_cnl_ops;
954int sof_cnl_ops_init(struct snd_sof_dev *sdev);
955extern struct snd_sof_dsp_ops sof_tgl_ops;
956int sof_tgl_ops_init(struct snd_sof_dev *sdev);
957extern struct snd_sof_dsp_ops sof_icl_ops;
958int sof_icl_ops_init(struct snd_sof_dev *sdev);
959
960extern const struct sof_intel_dsp_desc skl_chip_info;
961extern const struct sof_intel_dsp_desc apl_chip_info;
962extern const struct sof_intel_dsp_desc cnl_chip_info;
963extern const struct sof_intel_dsp_desc icl_chip_info;
964extern const struct sof_intel_dsp_desc tgl_chip_info;
965extern const struct sof_intel_dsp_desc tglh_chip_info;
966extern const struct sof_intel_dsp_desc ehl_chip_info;
967extern const struct sof_intel_dsp_desc jsl_chip_info;
968extern const struct sof_intel_dsp_desc adls_chip_info;
969extern const struct sof_intel_dsp_desc mtl_chip_info;
970extern const struct sof_intel_dsp_desc arl_s_chip_info;
971extern const struct sof_intel_dsp_desc lnl_chip_info;
972extern const struct sof_intel_dsp_desc ptl_chip_info;
973extern const struct sof_intel_dsp_desc wcl_chip_info;
974extern const struct sof_intel_dsp_desc nvl_chip_info;
975extern const struct sof_intel_dsp_desc nvl_s_chip_info;
976
977/* Probes support */
978#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_PROBES)
979int hda_probes_register(struct snd_sof_dev *sdev);
980void hda_probes_unregister(struct snd_sof_dev *sdev);
981#else
982static inline int hda_probes_register(struct snd_sof_dev *sdev)
983{
984 return 0;
985}
986
987static inline void hda_probes_unregister(struct snd_sof_dev *sdev)
988{
989}
990#endif /* CONFIG_SND_SOC_SOF_HDA_PROBES */
991
992/* SOF client registration for HDA platforms */
993int hda_register_clients(struct snd_sof_dev *sdev);
994void hda_unregister_clients(struct snd_sof_dev *sdev);
995
996/* machine driver select */
997struct snd_soc_acpi_mach *hda_machine_select(struct snd_sof_dev *sdev);
998void hda_set_mach_params(struct snd_soc_acpi_mach *mach,
999 struct snd_sof_dev *sdev);
1000
1001/* PCI driver selection and probe */
1002int hda_pci_intel_probe(struct pci_dev *pci, const struct pci_device_id *pci_id);
1003
1004struct snd_sof_dai;
1005struct sof_ipc_dai_config;
1006
1007#define SOF_HDA_POSITION_QUIRK_USE_SKYLAKE_LEGACY (0) /* previous implementation */
1008#define SOF_HDA_POSITION_QUIRK_USE_DPIB_REGISTERS (1) /* recommended if VC0 only */
1009#define SOF_HDA_POSITION_QUIRK_USE_DPIB_DDR_UPDATE (2) /* recommended with VC0 or VC1 */
1010
1011extern int sof_hda_position_quirk;
1012
1013void hda_set_dai_drv_ops(struct snd_sof_dev *sdev, struct snd_sof_dsp_ops *ops);
1014void hda_ops_free(struct snd_sof_dev *sdev);
1015
1016/* SKL/KBL */
1017int hda_dsp_cl_boot_firmware_skl(struct snd_sof_dev *sdev);
1018int hda_dsp_core_stall_reset(struct snd_sof_dev *sdev, unsigned int core_mask);
1019
1020/* IPC4 */
1021irqreturn_t cnl_ipc4_irq_thread(int irq, void *context);
1022int cnl_ipc4_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg);
1023irqreturn_t hda_dsp_ipc4_irq_thread(int irq, void *context);
1024bool hda_ipc4_tx_is_busy(struct snd_sof_dev *sdev);
1025void hda_dsp_ipc4_schedule_d0i3_work(struct sof_intel_hda_dev *hdev,
1026 struct snd_sof_ipc_msg *msg);
1027int hda_dsp_ipc4_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg);
1028void hda_ipc4_dump(struct snd_sof_dev *sdev);
1029extern struct sdw_intel_ops sdw_callback;
1030
1031struct sof_ipc4_fw_library;
1032int hda_dsp_ipc4_load_library(struct snd_sof_dev *sdev,
1033 struct sof_ipc4_fw_library *fw_lib, bool reload);
1034
1035/**
1036 * struct hda_dai_widget_dma_ops - DAI DMA ops optional by default unless specified otherwise
1037 * @get_hext_stream: Mandatory function pointer to get the saved pointer to struct hdac_ext_stream
1038 * @assign_hext_stream: Function pointer to assign a hdac_ext_stream
1039 * @release_hext_stream: Function pointer to release the hdac_ext_stream
1040 * @setup_hext_stream: Function pointer for hdac_ext_stream setup
1041 * @reset_hext_stream: Function pointer for hdac_ext_stream reset
1042 * @pre_trigger: Function pointer for DAI DMA pre-trigger actions
1043 * @trigger: Function pointer for DAI DMA trigger actions
1044 * @post_trigger: Function pointer for DAI DMA post-trigger actions
1045 * @codec_dai_set_stream: Function pointer to set codec-side stream information
1046 * @calc_stream_format: Function pointer to determine stream format from hw_params and
1047 * for HDaudio codec DAI from the .sig bits
1048 * @get_hlink: Mandatory function pointer to retrieve hlink, mainly to program LOSIDV
1049 * for legacy HDaudio links or program HDaudio Extended Link registers.
1050 */
1051struct hda_dai_widget_dma_ops {
1052 struct hdac_ext_stream *(*get_hext_stream)(struct snd_sof_dev *sdev,
1053 struct snd_soc_dai *cpu_dai,
1054 struct snd_pcm_substream *substream);
1055 struct hdac_ext_stream *(*assign_hext_stream)(struct snd_sof_dev *sdev,
1056 struct snd_soc_dai *cpu_dai,
1057 struct snd_pcm_substream *substream,
1058 struct hdac_ext_link *hlink);
1059 void (*release_hext_stream)(struct snd_sof_dev *sdev, struct snd_soc_dai *cpu_dai,
1060 struct snd_pcm_substream *substream);
1061 void (*setup_hext_stream)(struct snd_sof_dev *sdev, struct hdac_ext_stream *hext_stream,
1062 unsigned int format_val);
1063 void (*reset_hext_stream)(struct snd_sof_dev *sdev, struct hdac_ext_stream *hext_sream);
1064 int (*pre_trigger)(struct snd_sof_dev *sdev, struct snd_soc_dai *cpu_dai,
1065 struct snd_pcm_substream *substream, int cmd);
1066 int (*trigger)(struct snd_sof_dev *sdev, struct snd_soc_dai *cpu_dai,
1067 struct snd_pcm_substream *substream, int cmd);
1068 int (*post_trigger)(struct snd_sof_dev *sdev, struct snd_soc_dai *cpu_dai,
1069 struct snd_pcm_substream *substream, int cmd);
1070 void (*codec_dai_set_stream)(struct snd_sof_dev *sdev,
1071 struct snd_pcm_substream *substream,
1072 struct hdac_stream *hstream);
1073 unsigned int (*calc_stream_format)(struct snd_sof_dev *sdev,
1074 struct snd_pcm_substream *substream,
1075 struct snd_pcm_hw_params *params);
1076 struct hdac_ext_link * (*get_hlink)(struct snd_sof_dev *sdev,
1077 struct snd_pcm_substream *substream);
1078};
1079
1080const struct hda_dai_widget_dma_ops *
1081hda_select_dai_widget_ops(struct snd_sof_dev *sdev, struct snd_sof_widget *swidget);
1082int hda_dai_config(struct snd_soc_dapm_widget *w, unsigned int flags,
1083 struct snd_sof_dai_config_data *data);
1084
1085static inline struct snd_sof_dev *widget_to_sdev(struct snd_soc_dapm_widget *w)
1086{
1087 struct snd_sof_widget *swidget = w->dobj.private;
1088 struct snd_soc_component *component = swidget->scomp;
1089
1090 return snd_soc_component_get_drvdata(component);
1091}
1092
1093#endif