| 1 | {
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| 2 | "SkipList": [
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| 3 | "tsx_aborted_cycles",
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| 4 | "tsx_transactional_cycles",
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| 5 | "C2_Pkg_Residency",
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| 6 | "C6_Pkg_Residency",
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| 7 | "C1_Core_Residency",
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| 8 | "C6_Core_Residency",
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| 9 | "tma_false_sharing",
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| 10 | "tma_remote_cache",
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| 11 | "tma_contested_accesses"
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| 12 | ],
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| 13 | "RelationshipRules": [
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| 14 | {
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| 15 | "RuleIndex": 1,
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| 16 | "Formula": "a+b",
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| 17 | "TestType": "RelationshipTest",
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| 18 | "RangeLower": "c",
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| 19 | "RangeUpper": "c",
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| 20 | "ErrorThreshold": 5.0,
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| 21 | "Description": "Intel(R) Optane(TM) Persistent Memory(PMEM) bandwidth total includes Intel(R) Optane(TM) Persistent Memory(PMEM) read bandwidth and Intel(R) Optane(TM) Persistent Memory(PMEM) write bandwidth",
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| 22 | "Metrics": [
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| 23 | {
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| 24 | "Name": "pmem_memory_bandwidth_read",
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| 25 | "Alias": "a"
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| 26 | },
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| 27 | {
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| 28 | "Name": "pmem_memory_bandwidth_write",
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| 29 | "Alias": "b"
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| 30 | },
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| 31 | {
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| 32 | "Name": "pmem_memory_bandwidth_total",
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| 33 | "Alias": "c"
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| 34 | }
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| 35 | ]
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| 36 | },
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| 37 | {
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| 38 | "RuleIndex": 2,
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| 39 | "Formula": "a+b",
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| 40 | "TestType": "RelationshipTest",
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| 41 | "RangeLower": "c",
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| 42 | "RangeUpper": "c",
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| 43 | "ErrorThreshold": 5.0,
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| 44 | "Description": "DDR memory bandwidth total includes DDR memory read bandwidth and DDR memory write bandwidth",
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| 45 | "Metrics": [
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| 46 | {
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| 47 | "Name": "memory_bandwidth_read",
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| 48 | "Alias": "a"
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| 49 | },
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| 50 | {
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| 51 | "Name": "memory_bandwidth_write",
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| 52 | "Alias": "b"
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| 53 | },
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| 54 | {
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| 55 | "Name": "memory_bandwidth_total",
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| 56 | "Alias": "c"
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| 57 | }
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| 58 | ]
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| 59 | },
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| 60 | {
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| 61 | "RuleIndex": 3,
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| 62 | "Formula": "a+b",
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| 63 | "TestType": "RelationshipTest",
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| 64 | "RangeLower": "100",
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| 65 | "RangeUpper": "100",
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| 66 | "ErrorThreshold": 5.0,
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| 67 | "Description": "Total memory read accesses includes memory reads from last level cache (LLC) addressed to local DRAM and memory reads from the last level cache (LLC) addressed to remote DRAM.",
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| 68 | "Metrics": [
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| 69 | {
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| 70 | "Name": "numa_reads_addressed_to_local_dram",
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| 71 | "Alias": "a"
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| 72 | },
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| 73 | {
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| 74 | "Name": "numa_reads_addressed_to_remote_dram",
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| 75 | "Alias": "b"
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| 76 | }
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| 77 | ]
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| 78 | },
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| 79 | {
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| 80 | "RuleIndex": 4,
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| 81 | "Formula": "a",
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| 82 | "TestType": "SingleMetricTest",
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| 83 | "RangeLower": "0.125",
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| 84 | "RangeUpper": "",
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| 85 | "ErrorThreshold": "",
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| 86 | "Description": "",
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| 87 | "Metrics": [
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| 88 | {
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| 89 | "Name": "cpi",
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| 90 | "Alias": "a"
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| 91 | }
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| 92 | ]
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| 93 | },
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| 94 | {
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| 95 | "RuleIndex": 5,
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| 96 | "Formula": "",
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| 97 | "TestType": "SingleMetricTest",
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| 98 | "RangeLower": "0",
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| 99 | "RangeUpper": "1",
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| 100 | "ErrorThreshold": 5.0,
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| 101 | "Description": "Ratio values should be within value range [0,1)",
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| 102 | "Metrics": [
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| 103 | {
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| 104 | "Name": "loads_per_instr",
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| 105 | "Alias": ""
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| 106 | },
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| 107 | {
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| 108 | "Name": "stores_per_instr",
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| 109 | "Alias": ""
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| 110 | },
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| 111 | {
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| 112 | "Name": "l1d_mpi",
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| 113 | "Alias": ""
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| 114 | },
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| 115 | {
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| 116 | "Name": "l1d_demand_data_read_hits_per_instr",
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| 117 | "Alias": ""
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| 118 | },
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| 119 | {
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| 120 | "Name": "l1_i_code_read_misses_with_prefetches_per_instr",
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| 121 | "Alias": ""
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| 122 | },
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| 123 | {
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| 124 | "Name": "l2_demand_data_read_hits_per_instr",
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| 125 | "Alias": ""
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| 126 | },
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| 127 | {
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| 128 | "Name": "l2_mpi",
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| 129 | "Alias": ""
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| 130 | },
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| 131 | {
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| 132 | "Name": "l2_demand_data_read_mpi",
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| 133 | "Alias": ""
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| 134 | },
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| 135 | {
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| 136 | "Name": "l2_demand_code_mpi",
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| 137 | "Alias": ""
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| 138 | }
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| 139 | ]
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| 140 | },
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| 141 | {
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| 142 | "RuleIndex": 6,
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| 143 | "Formula": "a+b+c+d",
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| 144 | "TestType": "RelationshipTest",
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| 145 | "RangeLower": "100",
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| 146 | "RangeUpper": "100",
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| 147 | "ErrorThreshold": 5.0,
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| 148 | "Description": "Sum of TMA level 1 metrics should be 100%",
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| 149 | "Metrics": [
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| 150 | {
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| 151 | "Name": "tma_frontend_bound",
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| 152 | "Alias": "a"
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| 153 | },
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| 154 | {
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| 155 | "Name": "tma_bad_speculation",
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| 156 | "Alias": "b"
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| 157 | },
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| 158 | {
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| 159 | "Name": "tma_backend_bound",
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| 160 | "Alias": "c"
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| 161 | },
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| 162 | {
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| 163 | "Name": "tma_retiring",
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| 164 | "Alias": "d"
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| 165 | }
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| 166 | ]
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| 167 | },
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| 168 | {
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| 169 | "RuleIndex": 7,
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| 170 | "Formula": "a+b",
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| 171 | "TestType": "RelationshipTest",
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| 172 | "RangeLower": "c",
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| 173 | "RangeUpper": "c",
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| 174 | "ErrorThreshold": 5.0,
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| 175 | "Description": "Sum of the level 2 children should equal level 1 parent",
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| 176 | "Metrics": [
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| 177 | {
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| 178 | "Name": "tma_fetch_latency",
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| 179 | "Alias": "a"
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| 180 | },
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| 181 | {
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| 182 | "Name": "tma_fetch_bandwidth",
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| 183 | "Alias": "b"
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| 184 | },
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| 185 | {
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| 186 | "Name": "tma_frontend_bound",
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| 187 | "Alias": "c"
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| 188 | }
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| 189 | ]
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| 190 | },
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| 191 | {
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| 192 | "RuleIndex": 8,
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| 193 | "Formula": "a+b",
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| 194 | "TestType": "RelationshipTest",
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| 195 | "RangeLower": "c",
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| 196 | "RangeUpper": "c",
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| 197 | "ErrorThreshold": 5.0,
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| 198 | "Description": "Sum of the level 2 children should equal level 1 parent",
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| 199 | "Metrics": [
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| 200 | {
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| 201 | "Name": "tma_branch_mispredicts",
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| 202 | "Alias": "a"
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| 203 | },
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| 204 | {
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| 205 | "Name": "tma_machine_clears",
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| 206 | "Alias": "b"
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| 207 | },
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| 208 | {
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| 209 | "Name": "tma_bad_speculation",
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| 210 | "Alias": "c"
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| 211 | }
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| 212 | ]
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| 213 | },
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| 214 | {
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| 215 | "RuleIndex": 9,
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| 216 | "Formula": "a+b",
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| 217 | "TestType": "RelationshipTest",
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| 218 | "RangeLower": "c",
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| 219 | "RangeUpper": "c",
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| 220 | "ErrorThreshold": 5.0,
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| 221 | "Description": "Sum of the level 2 children should equal level 1 parent",
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| 222 | "Metrics": [
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| 223 | {
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| 224 | "Name": "tma_memory_bound",
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| 225 | "Alias": "a"
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| 226 | },
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| 227 | {
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| 228 | "Name": "tma_core_bound",
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| 229 | "Alias": "b"
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| 230 | },
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| 231 | {
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| 232 | "Name": "tma_backend_bound",
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| 233 | "Alias": "c"
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| 234 | }
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| 235 | ]
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| 236 | },
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| 237 | {
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| 238 | "RuleIndex": 10,
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| 239 | "Formula": "a+b",
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| 240 | "TestType": "RelationshipTest",
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| 241 | "RangeLower": "c",
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| 242 | "RangeUpper": "c",
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| 243 | "ErrorThreshold": 5.0,
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| 244 | "Description": "Sum of the level 2 children should equal level 1 parent",
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| 245 | "Metrics": [
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| 246 | {
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| 247 | "Name": "tma_light_operations",
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| 248 | "Alias": "a"
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| 249 | },
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| 250 | {
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| 251 | "Name": "tma_heavy_operations",
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| 252 | "Alias": "b"
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| 253 | },
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| 254 | {
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| 255 | "Name": "tma_retiring",
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| 256 | "Alias": "c"
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| 257 | }
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| 258 | ]
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| 259 | },
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| 260 | {
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| 261 | "RuleIndex": 11,
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| 262 | "Formula": "a+b+c",
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| 263 | "TestType": "RelationshipTest",
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| 264 | "RangeLower": "100",
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| 265 | "RangeUpper": "100",
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| 266 | "ErrorThreshold": 5.0,
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| 267 | "Description": "The all_requests includes the memory_page_empty, memory_page_misses, and memory_page_hits equals.",
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| 268 | "Metrics": [
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| 269 | {
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| 270 | "Name": "memory_page_empty_vs_all_requests",
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| 271 | "Alias": "a"
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| 272 | },
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| 273 | {
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| 274 | "Name": "memory_page_misses_vs_all_requests",
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| 275 | "Alias": "b"
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| 276 | },
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| 277 | {
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| 278 | "Name": "memory_page_hits_vs_all_requests",
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| 279 | "Alias": "c"
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| 280 | }
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| 281 | ]
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| 282 | },
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| 283 | {
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| 284 | "RuleIndex": 12,
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| 285 | "Formula": "a-b",
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| 286 | "TestType": "RelationshipTest",
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| 287 | "RangeLower": "0",
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| 288 | "RangeUpper": "",
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| 289 | "ErrorThreshold": 5.0,
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| 290 | "Description": "CPU utilization in kernel mode should always be <= cpu utilization",
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| 291 | "Metrics": [
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| 292 | {
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| 293 | "Name": "cpu_utilization",
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| 294 | "Alias": "a"
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| 295 | },
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| 296 | {
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| 297 | "Name": "cpu_utilization_in_kernel_mode",
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| 298 | "Alias": "b"
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| 299 | }
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| 300 | ]
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| 301 | },
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| 302 | {
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| 303 | "RuleIndex": 13,
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| 304 | "Formula": "a-b",
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| 305 | "TestType": "RelationshipTest",
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| 306 | "RangeLower": "0",
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| 307 | "RangeUpper": "",
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| 308 | "ErrorThreshold": 5.0,
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| 309 | "Description": "Total L2 misses per instruction should be >= L2 demand data read misses per instruction",
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| 310 | "Metrics": [
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| 311 | {
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| 312 | "Name": "l2_mpi",
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| 313 | "Alias": "a"
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| 314 | },
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| 315 | {
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| 316 | "Name": "l2_demand_data_read_mpi",
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| 317 | "Alias": "b"
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| 318 | }
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| 319 | ]
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| 320 | },
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| 321 | {
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| 322 | "RuleIndex": 14,
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| 323 | "Formula": "a-b",
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| 324 | "TestType": "RelationshipTest",
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| 325 | "RangeLower": "0",
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| 326 | "RangeUpper": "",
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| 327 | "ErrorThreshold": 5.0,
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| 328 | "Description": "Total L2 misses per instruction should be >= L2 demand code misses per instruction",
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| 329 | "Metrics": [
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| 330 | {
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| 331 | "Name": "l2_mpi",
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| 332 | "Alias": "a"
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| 333 | },
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| 334 | {
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| 335 | "Name": "l2_demand_code_mpi",
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| 336 | "Alias": "b"
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| 337 | }
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| 338 | ]
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| 339 | },
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| 340 | {
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| 341 | "RuleIndex": 15,
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| 342 | "Formula": "b+c+d",
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| 343 | "TestType": "RelationshipTest",
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| 344 | "RangeLower": "a",
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| 345 | "RangeUpper": "a",
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| 346 | "ErrorThreshold": 5.0,
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| 347 | "Description": "L3 data read, rfo, code misses per instruction equals total L3 misses per instruction.",
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| 348 | "Metrics": [
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| 349 | {
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| 350 | "Name": "llc_mpi",
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| 351 | "Alias": "a"
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| 352 | },
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| 353 | {
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| 354 | "Name": "llc_data_read_mpi_demand_plus_prefetch",
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| 355 | "Alias": "b"
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| 356 | },
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| 357 | {
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| 358 | "Name": "llc_rfo_read_mpi_demand_plus_prefetch",
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| 359 | "Alias": "c"
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| 360 | },
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| 361 | {
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| 362 | "Name": "llc_code_read_mpi_demand_plus_prefetch",
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| 363 | "Alias": "d"
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| 364 | }
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| 365 | ]
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| 366 | },
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| 367 | {
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| 368 | "RuleIndex": 16,
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| 369 | "Formula": "a",
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| 370 | "TestType": "SingleMetricTest",
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| 371 | "RangeLower": "0",
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| 372 | "RangeUpper": "8",
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| 373 | "ErrorThreshold": 0.0,
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| 374 | "Description": "Setting generous range for allowable frequencies",
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| 375 | "Metrics": [
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| 376 | {
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| 377 | "Name": "uncore_freq",
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| 378 | "Alias": "a"
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| 379 | }
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| 380 | ]
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| 381 | },
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| 382 | {
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| 383 | "RuleIndex": 17,
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| 384 | "Formula": "a",
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| 385 | "TestType": "SingleMetricTest",
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| 386 | "RangeLower": "0",
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| 387 | "RangeUpper": "8",
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| 388 | "ErrorThreshold": 0.0,
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| 389 | "Description": "Setting generous range for allowable frequencies",
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| 390 | "Metrics": [
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| 391 | {
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| 392 | "Name": "cpu_operating_frequency",
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| 393 | "Alias": "a"
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| 394 | }
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| 395 | ]
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| 396 | }
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| 397 | ]
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| 398 | }
|