projects/linux·blob v2.6.13 · refs

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1/*
2 * I2O kernel space accessible structures/APIs
3 *
4 * (c) Copyright 1999, 2000 Red Hat Software
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 *************************************************************************
12 *
13 * This header file defined the I2O APIs/structures for use by
14 * the I2O kernel modules.
15 *
16 */
17
18#ifndef _I2O_H
19#define _I2O_H
20
21#ifdef __KERNEL__ /* This file to be included by kernel only */
22
23#include <linux/i2o-dev.h>
24
25/* How many different OSM's are we allowing */
26#define I2O_MAX_DRIVERS 8
27
28#include <asm/io.h>
29#include <asm/semaphore.h> /* Needed for MUTEX init macros */
30#include <linux/pci.h>
31#include <linux/dma-mapping.h>
32
33/* message queue empty */
34#define I2O_QUEUE_EMPTY 0xffffffff
35
36/*
37 * Message structures
38 */
39struct i2o_message {
40 union {
41 struct {
42 u8 version_offset;
43 u8 flags;
44 u16 size;
45 u32 target_tid:12;
46 u32 init_tid:12;
47 u32 function:8;
48 u32 icntxt; /* initiator context */
49 u32 tcntxt; /* transaction context */
50 } s;
51 u32 head[4];
52 } u;
53 /* List follows */
54 u32 body[0];
55};
56
57/*
58 * Each I2O device entity has one of these. There is one per device.
59 */
60struct i2o_device {
61 i2o_lct_entry lct_data; /* Device LCT information */
62
63 struct i2o_controller *iop; /* Controlling IOP */
64 struct list_head list; /* node in IOP devices list */
65
66 struct device device;
67
68 struct semaphore lock; /* device lock */
69
70 struct class_device classdev; /* i2o device class */
71};
72
73/*
74 * Event structure provided to the event handling function
75 */
76struct i2o_event {
77 struct work_struct work;
78 struct i2o_device *i2o_dev; /* I2O device pointer from which the
79 event reply was initiated */
80 u16 size; /* Size of data in 32-bit words */
81 u32 tcntxt; /* Transaction context used at
82 registration */
83 u32 event_indicator; /* Event indicator from reply */
84 u32 data[0]; /* Event data from reply */
85};
86
87/*
88 * I2O classes which could be handled by the OSM
89 */
90struct i2o_class_id {
91 u16 class_id:12;
92};
93
94/*
95 * I2O driver structure for OSMs
96 */
97struct i2o_driver {
98 char *name; /* OSM name */
99 int context; /* Low 8 bits of the transaction info */
100 struct i2o_class_id *classes; /* I2O classes that this OSM handles */
101
102 /* Message reply handler */
103 int (*reply) (struct i2o_controller *, u32, struct i2o_message *);
104
105 /* Event handler */
106 void (*event) (struct i2o_event *);
107
108 struct workqueue_struct *event_queue; /* Event queue */
109
110 struct device_driver driver;
111
112 /* notification of changes */
113 void (*notify_controller_add) (struct i2o_controller *);
114 void (*notify_controller_remove) (struct i2o_controller *);
115 void (*notify_device_add) (struct i2o_device *);
116 void (*notify_device_remove) (struct i2o_device *);
117
118 struct semaphore lock;
119};
120
121/*
122 * Contains DMA mapped address information
123 */
124struct i2o_dma {
125 void *virt;
126 dma_addr_t phys;
127 size_t len;
128};
129
130/*
131 * Contains IO mapped address information
132 */
133struct i2o_io {
134 void __iomem *virt;
135 unsigned long phys;
136 unsigned long len;
137};
138
139/*
140 * Context queue entry, used for 32-bit context on 64-bit systems
141 */
142struct i2o_context_list_element {
143 struct list_head list;
144 u32 context;
145 void *ptr;
146 unsigned long timestamp;
147};
148
149/*
150 * Each I2O controller has one of these objects
151 */
152struct i2o_controller {
153 char name[16];
154 int unit;
155 int type;
156
157 struct pci_dev *pdev; /* PCI device */
158
159 unsigned int promise:1; /* Promise controller */
160 unsigned int adaptec:1; /* DPT / Adaptec controller */
161 unsigned int raptor:1; /* split bar */
162 unsigned int no_quiesce:1; /* dont quiesce before reset */
163 unsigned int short_req:1; /* use small block sizes */
164 unsigned int limit_sectors:1; /* limit number of sectors / request */
165 unsigned int pae_support:1; /* controller has 64-bit SGL support */
166
167 struct list_head devices; /* list of I2O devices */
168 struct list_head list; /* Controller list */
169
170 void __iomem *in_port; /* Inbout port address */
171 void __iomem *out_port; /* Outbound port address */
172 void __iomem *irq_status; /* Interrupt status register address */
173 void __iomem *irq_mask; /* Interrupt mask register address */
174
175 /* Dynamic LCT related data */
176
177 struct i2o_dma status; /* IOP status block */
178
179 struct i2o_dma hrt; /* HW Resource Table */
180 i2o_lct *lct; /* Logical Config Table */
181 struct i2o_dma dlct; /* Temp LCT */
182 struct semaphore lct_lock; /* Lock for LCT updates */
183 struct i2o_dma status_block; /* IOP status block */
184
185 struct i2o_io base; /* controller messaging unit */
186 struct i2o_io in_queue; /* inbound message queue Host->IOP */
187 struct i2o_dma out_queue; /* outbound message queue IOP->Host */
188
189 unsigned int battery:1; /* Has a battery backup */
190 unsigned int io_alloc:1; /* An I/O resource was allocated */
191 unsigned int mem_alloc:1; /* A memory resource was allocated */
192
193 struct resource io_resource; /* I/O resource allocated to the IOP */
194 struct resource mem_resource; /* Mem resource allocated to the IOP */
195
196 struct device device;
197 struct class_device classdev; /* I2O controller class */
198 struct i2o_device *exec; /* Executive */
199#if BITS_PER_LONG == 64
200 spinlock_t context_list_lock; /* lock for context_list */
201 atomic_t context_list_counter; /* needed for unique contexts */
202 struct list_head context_list; /* list of context id's
203 and pointers */
204#endif
205 spinlock_t lock; /* lock for controller
206 configuration */
207
208 void *driver_data[I2O_MAX_DRIVERS]; /* storage for drivers */
209};
210
211/*
212 * I2O System table entry
213 *
214 * The system table contains information about all the IOPs in the
215 * system. It is sent to all IOPs so that they can create peer2peer
216 * connections between them.
217 */
218struct i2o_sys_tbl_entry {
219 u16 org_id;
220 u16 reserved1;
221 u32 iop_id:12;
222 u32 reserved2:20;
223 u16 seg_num:12;
224 u16 i2o_version:4;
225 u8 iop_state;
226 u8 msg_type;
227 u16 frame_size;
228 u16 reserved3;
229 u32 last_changed;
230 u32 iop_capabilities;
231 u32 inbound_low;
232 u32 inbound_high;
233};
234
235struct i2o_sys_tbl {
236 u8 num_entries;
237 u8 version;
238 u16 reserved1;
239 u32 change_ind;
240 u32 reserved2;
241 u32 reserved3;
242 struct i2o_sys_tbl_entry iops[0];
243};
244
245extern struct list_head i2o_controllers;
246
247/* Message functions */
248static inline u32 i2o_msg_get(struct i2o_controller *,
249 struct i2o_message __iomem **);
250extern u32 i2o_msg_get_wait(struct i2o_controller *,
251 struct i2o_message __iomem **, int);
252static inline void i2o_msg_post(struct i2o_controller *, u32);
253static inline int i2o_msg_post_wait(struct i2o_controller *, u32,
254 unsigned long);
255extern int i2o_msg_post_wait_mem(struct i2o_controller *, u32, unsigned long,
256 struct i2o_dma *);
257extern void i2o_msg_nop(struct i2o_controller *, u32);
258static inline void i2o_flush_reply(struct i2o_controller *, u32);
259
260/* IOP functions */
261extern int i2o_status_get(struct i2o_controller *);
262
263extern int i2o_event_register(struct i2o_device *, struct i2o_driver *, int,
264 u32);
265extern struct i2o_device *i2o_iop_find_device(struct i2o_controller *, u16);
266extern struct i2o_controller *i2o_find_iop(int);
267
268/* Functions needed for handling 64-bit pointers in 32-bit context */
269#if BITS_PER_LONG == 64
270extern u32 i2o_cntxt_list_add(struct i2o_controller *, void *);
271extern void *i2o_cntxt_list_get(struct i2o_controller *, u32);
272extern u32 i2o_cntxt_list_remove(struct i2o_controller *, void *);
273extern u32 i2o_cntxt_list_get_ptr(struct i2o_controller *, void *);
274
275static inline u32 i2o_ptr_low(void *ptr)
276{
277 return (u32) (u64) ptr;
278};
279
280static inline u32 i2o_ptr_high(void *ptr)
281{
282 return (u32) ((u64) ptr >> 32);
283};
284
285static inline u32 i2o_dma_low(dma_addr_t dma_addr)
286{
287 return (u32) (u64) dma_addr;
288};
289
290static inline u32 i2o_dma_high(dma_addr_t dma_addr)
291{
292 return (u32) ((u64) dma_addr >> 32);
293};
294#else
295static inline u32 i2o_cntxt_list_add(struct i2o_controller *c, void *ptr)
296{
297 return (u32) ptr;
298};
299
300static inline void *i2o_cntxt_list_get(struct i2o_controller *c, u32 context)
301{
302 return (void *)context;
303};
304
305static inline u32 i2o_cntxt_list_remove(struct i2o_controller *c, void *ptr)
306{
307 return (u32) ptr;
308};
309
310static inline u32 i2o_cntxt_list_get_ptr(struct i2o_controller *c, void *ptr)
311{
312 return (u32) ptr;
313};
314
315static inline u32 i2o_ptr_low(void *ptr)
316{
317 return (u32) ptr;
318};
319
320static inline u32 i2o_ptr_high(void *ptr)
321{
322 return 0;
323};
324
325static inline u32 i2o_dma_low(dma_addr_t dma_addr)
326{
327 return (u32) dma_addr;
328};
329
330static inline u32 i2o_dma_high(dma_addr_t dma_addr)
331{
332 return 0;
333};
334#endif
335
336/**
337 * i2o_sg_tablesize - Calculate the maximum number of elements in a SGL
338 * @c: I2O controller for which the calculation should be done
339 * @body_size: maximum body size used for message in 32-bit words.
340 *
341 * Return the maximum number of SG elements in a SG list.
342 */
343static inline u16 i2o_sg_tablesize(struct i2o_controller *c, u16 body_size)
344{
345 i2o_status_block *sb = c->status_block.virt;
346 u16 sg_count =
347 (sb->inbound_frame_size - sizeof(struct i2o_message) / 4) -
348 body_size;
349
350 if (c->pae_support) {
351 /*
352 * for 64-bit a SG attribute element must be added and each
353 * SG element needs 12 bytes instead of 8.
354 */
355 sg_count -= 2;
356 sg_count /= 3;
357 } else
358 sg_count /= 2;
359
360 if (c->short_req && (sg_count > 8))
361 sg_count = 8;
362
363 return sg_count;
364};
365
366/**
367 * i2o_dma_map_single - Map pointer to controller and fill in I2O message.
368 * @c: I2O controller
369 * @ptr: pointer to the data which should be mapped
370 * @size: size of data in bytes
371 * @direction: DMA_TO_DEVICE / DMA_FROM_DEVICE
372 * @sg_ptr: pointer to the SG list inside the I2O message
373 *
374 * This function does all necessary DMA handling and also writes the I2O
375 * SGL elements into the I2O message. For details on DMA handling see also
376 * dma_map_single(). The pointer sg_ptr will only be set to the end of the
377 * SG list if the allocation was successful.
378 *
379 * Returns DMA address which must be checked for failures using
380 * dma_mapping_error().
381 */
382static inline dma_addr_t i2o_dma_map_single(struct i2o_controller *c, void *ptr,
383 size_t size,
384 enum dma_data_direction direction,
385 u32 __iomem ** sg_ptr)
386{
387 u32 sg_flags;
388 u32 __iomem *mptr = *sg_ptr;
389 dma_addr_t dma_addr;
390
391 switch (direction) {
392 case DMA_TO_DEVICE:
393 sg_flags = 0xd4000000;
394 break;
395 case DMA_FROM_DEVICE:
396 sg_flags = 0xd0000000;
397 break;
398 default:
399 return 0;
400 }
401
402 dma_addr = dma_map_single(&c->pdev->dev, ptr, size, direction);
403 if (!dma_mapping_error(dma_addr)) {
404#ifdef CONFIG_I2O_EXT_ADAPTEC_DMA64
405 if ((sizeof(dma_addr_t) > 4) && c->pae_support) {
406 writel(0x7C020002, mptr++);
407 writel(PAGE_SIZE, mptr++);
408 }
409#endif
410
411 writel(sg_flags | size, mptr++);
412 writel(i2o_dma_low(dma_addr), mptr++);
413#ifdef CONFIG_I2O_EXT_ADAPTEC_DMA64
414 if ((sizeof(dma_addr_t) > 4) && c->pae_support)
415 writel(i2o_dma_high(dma_addr), mptr++);
416#endif
417 *sg_ptr = mptr;
418 }
419 return dma_addr;
420};
421
422/**
423 * i2o_dma_map_sg - Map a SG List to controller and fill in I2O message.
424 * @c: I2O controller
425 * @sg: SG list to be mapped
426 * @sg_count: number of elements in the SG list
427 * @direction: DMA_TO_DEVICE / DMA_FROM_DEVICE
428 * @sg_ptr: pointer to the SG list inside the I2O message
429 *
430 * This function does all necessary DMA handling and also writes the I2O
431 * SGL elements into the I2O message. For details on DMA handling see also
432 * dma_map_sg(). The pointer sg_ptr will only be set to the end of the SG
433 * list if the allocation was successful.
434 *
435 * Returns 0 on failure or 1 on success.
436 */
437static inline int i2o_dma_map_sg(struct i2o_controller *c,
438 struct scatterlist *sg, int sg_count,
439 enum dma_data_direction direction,
440 u32 __iomem ** sg_ptr)
441{
442 u32 sg_flags;
443 u32 __iomem *mptr = *sg_ptr;
444
445 switch (direction) {
446 case DMA_TO_DEVICE:
447 sg_flags = 0x14000000;
448 break;
449 case DMA_FROM_DEVICE:
450 sg_flags = 0x10000000;
451 break;
452 default:
453 return 0;
454 }
455
456 sg_count = dma_map_sg(&c->pdev->dev, sg, sg_count, direction);
457 if (!sg_count)
458 return 0;
459
460#ifdef CONFIG_I2O_EXT_ADAPTEC_DMA64
461 if ((sizeof(dma_addr_t) > 4) && c->pae_support) {
462 writel(0x7C020002, mptr++);
463 writel(PAGE_SIZE, mptr++);
464 }
465#endif
466
467 while (sg_count-- > 0) {
468 if (!sg_count)
469 sg_flags |= 0xC0000000;
470 writel(sg_flags | sg_dma_len(sg), mptr++);
471 writel(i2o_dma_low(sg_dma_address(sg)), mptr++);
472#ifdef CONFIG_I2O_EXT_ADAPTEC_DMA64
473 if ((sizeof(dma_addr_t) > 4) && c->pae_support)
474 writel(i2o_dma_high(sg_dma_address(sg)), mptr++);
475#endif
476 sg++;
477 }
478 *sg_ptr = mptr;
479
480 return 1;
481};
482
483/**
484 * i2o_dma_alloc - Allocate DMA memory
485 * @dev: struct device pointer to the PCI device of the I2O controller
486 * @addr: i2o_dma struct which should get the DMA buffer
487 * @len: length of the new DMA memory
488 * @gfp_mask: GFP mask
489 *
490 * Allocate a coherent DMA memory and write the pointers into addr.
491 *
492 * Returns 0 on success or -ENOMEM on failure.
493 */
494static inline int i2o_dma_alloc(struct device *dev, struct i2o_dma *addr,
495 size_t len, unsigned int gfp_mask)
496{
497 struct pci_dev *pdev = to_pci_dev(dev);
498 int dma_64 = 0;
499
500 if ((sizeof(dma_addr_t) > 4) && (pdev->dma_mask == DMA_64BIT_MASK)) {
501 dma_64 = 1;
502 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK))
503 return -ENOMEM;
504 }
505
506 addr->virt = dma_alloc_coherent(dev, len, &addr->phys, gfp_mask);
507
508 if ((sizeof(dma_addr_t) > 4) && dma_64)
509 if (pci_set_dma_mask(pdev, DMA_64BIT_MASK))
510 printk(KERN_WARNING "i2o: unable to set 64-bit DMA");
511
512 if (!addr->virt)
513 return -ENOMEM;
514
515 memset(addr->virt, 0, len);
516 addr->len = len;
517
518 return 0;
519};
520
521/**
522 * i2o_dma_free - Free DMA memory
523 * @dev: struct device pointer to the PCI device of the I2O controller
524 * @addr: i2o_dma struct which contains the DMA buffer
525 *
526 * Free a coherent DMA memory and set virtual address of addr to NULL.
527 */
528static inline void i2o_dma_free(struct device *dev, struct i2o_dma *addr)
529{
530 if (addr->virt) {
531 if (addr->phys)
532 dma_free_coherent(dev, addr->len, addr->virt,
533 addr->phys);
534 else
535 kfree(addr->virt);
536 addr->virt = NULL;
537 }
538};
539
540/**
541 * i2o_dma_realloc - Realloc DMA memory
542 * @dev: struct device pointer to the PCI device of the I2O controller
543 * @addr: pointer to a i2o_dma struct DMA buffer
544 * @len: new length of memory
545 * @gfp_mask: GFP mask
546 *
547 * If there was something allocated in the addr, free it first. If len > 0
548 * than try to allocate it and write the addresses back to the addr
549 * structure. If len == 0 set the virtual address to NULL.
550 *
551 * Returns the 0 on success or negative error code on failure.
552 */
553static inline int i2o_dma_realloc(struct device *dev, struct i2o_dma *addr,
554 size_t len, unsigned int gfp_mask)
555{
556 i2o_dma_free(dev, addr);
557
558 if (len)
559 return i2o_dma_alloc(dev, addr, len, gfp_mask);
560
561 return 0;
562};
563
564/* I2O driver (OSM) functions */
565extern int i2o_driver_register(struct i2o_driver *);
566extern void i2o_driver_unregister(struct i2o_driver *);
567
568/**
569 * i2o_driver_notify_controller_add - Send notification of added controller
570 * to a single I2O driver
571 *
572 * Send notification of added controller to a single registered driver.
573 */
574static inline void i2o_driver_notify_controller_add(struct i2o_driver *drv,
575 struct i2o_controller *c)
576{
577 if (drv->notify_controller_add)
578 drv->notify_controller_add(c);
579};
580
581/**
582 * i2o_driver_notify_controller_remove - Send notification of removed
583 * controller to a single I2O driver
584 *
585 * Send notification of removed controller to a single registered driver.
586 */
587static inline void i2o_driver_notify_controller_remove(struct i2o_driver *drv,
588 struct i2o_controller *c)
589{
590 if (drv->notify_controller_remove)
591 drv->notify_controller_remove(c);
592};
593
594/**
595 * i2o_driver_notify_device_add - Send notification of added device to a
596 * single I2O driver
597 *
598 * Send notification of added device to a single registered driver.
599 */
600static inline void i2o_driver_notify_device_add(struct i2o_driver *drv,
601 struct i2o_device *i2o_dev)
602{
603 if (drv->notify_device_add)
604 drv->notify_device_add(i2o_dev);
605};
606
607/**
608 * i2o_driver_notify_device_remove - Send notification of removed device
609 * to a single I2O driver
610 *
611 * Send notification of removed device to a single registered driver.
612 */
613static inline void i2o_driver_notify_device_remove(struct i2o_driver *drv,
614 struct i2o_device *i2o_dev)
615{
616 if (drv->notify_device_remove)
617 drv->notify_device_remove(i2o_dev);
618};
619
620extern void i2o_driver_notify_controller_add_all(struct i2o_controller *);
621extern void i2o_driver_notify_controller_remove_all(struct i2o_controller *);
622extern void i2o_driver_notify_device_add_all(struct i2o_device *);
623extern void i2o_driver_notify_device_remove_all(struct i2o_device *);
624
625/* I2O device functions */
626extern int i2o_device_claim(struct i2o_device *);
627extern int i2o_device_claim_release(struct i2o_device *);
628
629/* Exec OSM functions */
630extern int i2o_exec_lct_get(struct i2o_controller *);
631
632/* device / driver / kobject conversion functions */
633#define to_i2o_driver(drv) container_of(drv,struct i2o_driver, driver)
634#define to_i2o_device(dev) container_of(dev, struct i2o_device, device)
635#define to_i2o_controller(dev) container_of(dev, struct i2o_controller, device)
636#define kobj_to_i2o_device(kobj) to_i2o_device(container_of(kobj, struct device, kobj))
637
638/**
639 * i2o_msg_get - obtain an I2O message from the IOP
640 * @c: I2O controller
641 * @msg: pointer to a I2O message pointer
642 *
643 * This function tries to get a message slot. If no message slot is
644 * available do not wait until one is availabe (see also i2o_msg_get_wait).
645 *
646 * On a success the message is returned and the pointer to the message is
647 * set in msg. The returned message is the physical page frame offset
648 * address from the read port (see the i2o spec). If no message is
649 * available returns I2O_QUEUE_EMPTY and msg is leaved untouched.
650 */
651static inline u32 i2o_msg_get(struct i2o_controller *c,
652 struct i2o_message __iomem ** msg)
653{
654 u32 m = readl(c->in_port);
655
656 if (m != I2O_QUEUE_EMPTY)
657 *msg = c->in_queue.virt + m;
658
659 return m;
660};
661
662/**
663 * i2o_msg_post - Post I2O message to I2O controller
664 * @c: I2O controller to which the message should be send
665 * @m: the message identifier
666 *
667 * Post the message to the I2O controller.
668 */
669static inline void i2o_msg_post(struct i2o_controller *c, u32 m)
670{
671 writel(m, c->in_port);
672};
673
674/**
675 * i2o_msg_post_wait - Post and wait a message and wait until return
676 * @c: controller
677 * @m: message to post
678 * @timeout: time in seconds to wait
679 *
680 * This API allows an OSM to post a message and then be told whether or
681 * not the system received a successful reply. If the message times out
682 * then the value '-ETIMEDOUT' is returned.
683 *
684 * Returns 0 on success or negative error code on failure.
685 */
686static inline int i2o_msg_post_wait(struct i2o_controller *c, u32 m,
687 unsigned long timeout)
688{
689 return i2o_msg_post_wait_mem(c, m, timeout, NULL);
690};
691
692/**
693 * i2o_flush_reply - Flush reply from I2O controller
694 * @c: I2O controller
695 * @m: the message identifier
696 *
697 * The I2O controller must be informed that the reply message is not needed
698 * anymore. If you forget to flush the reply, the message frame can't be
699 * used by the controller anymore and is therefore lost.
700 */
701static inline void i2o_flush_reply(struct i2o_controller *c, u32 m)
702{
703 writel(m, c->out_port);
704};
705
706/**
707 * i2o_out_to_virt - Turn an I2O message to a virtual address
708 * @c: controller
709 * @m: message engine value
710 *
711 * Turn a receive message from an I2O controller bus address into
712 * a Linux virtual address. The shared page frame is a linear block
713 * so we simply have to shift the offset. This function does not
714 * work for sender side messages as they are ioremap objects
715 * provided by the I2O controller.
716 */
717static inline struct i2o_message *i2o_msg_out_to_virt(struct i2o_controller *c,
718 u32 m)
719{
720 BUG_ON(m < c->out_queue.phys
721 || m >= c->out_queue.phys + c->out_queue.len);
722
723 return c->out_queue.virt + (m - c->out_queue.phys);
724};
725
726/**
727 * i2o_msg_in_to_virt - Turn an I2O message to a virtual address
728 * @c: controller
729 * @m: message engine value
730 *
731 * Turn a send message from an I2O controller bus address into
732 * a Linux virtual address. The shared page frame is a linear block
733 * so we simply have to shift the offset. This function does not
734 * work for receive side messages as they are kmalloc objects
735 * in a different pool.
736 */
737static inline struct i2o_message __iomem *i2o_msg_in_to_virt(struct
738 i2o_controller *c,
739 u32 m)
740{
741 return c->in_queue.virt + m;
742};
743
744/*
745 * Endian handling wrapped into the macro - keeps the core code
746 * cleaner.
747 */
748
749#define i2o_raw_writel(val, mem) __raw_writel(cpu_to_le32(val), mem)
750
751extern int i2o_parm_field_get(struct i2o_device *, int, int, void *, int);
752extern int i2o_parm_table_get(struct i2o_device *, int, int, int, void *, int,
753 void *, int);
754
755/* debugging and troubleshooting/diagnostic helpers. */
756#define osm_printk(level, format, arg...) \
757 printk(level "%s: " format, OSM_NAME , ## arg)
758
759#ifdef DEBUG
760#define osm_debug(format, arg...) \
761 osm_printk(KERN_DEBUG, format , ## arg)
762#else
763#define osm_debug(format, arg...) \
764 do { } while (0)
765#endif
766
767#define osm_err(format, arg...) \
768 osm_printk(KERN_ERR, format , ## arg)
769#define osm_info(format, arg...) \
770 osm_printk(KERN_INFO, format , ## arg)
771#define osm_warn(format, arg...) \
772 osm_printk(KERN_WARNING, format , ## arg)
773
774/* debugging functions */
775extern void i2o_report_status(const char *, const char *, struct i2o_message *);
776extern void i2o_dump_message(struct i2o_message *);
777extern void i2o_dump_hrt(struct i2o_controller *c);
778extern void i2o_debug_state(struct i2o_controller *c);
779
780/*
781 * Cache strategies
782 */
783
784/* The NULL strategy leaves everything up to the controller. This tends to be a
785 * pessimal but functional choice.
786 */
787#define CACHE_NULL 0
788/* Prefetch data when reading. We continually attempt to load the next 32 sectors
789 * into the controller cache.
790 */
791#define CACHE_PREFETCH 1
792/* Prefetch data when reading. We sometimes attempt to load the next 32 sectors
793 * into the controller cache. When an I/O is less <= 8K we assume its probably
794 * not sequential and don't prefetch (default)
795 */
796#define CACHE_SMARTFETCH 2
797/* Data is written to the cache and then out on to the disk. The I/O must be
798 * physically on the medium before the write is acknowledged (default without
799 * NVRAM)
800 */
801#define CACHE_WRITETHROUGH 17
802/* Data is written to the cache and then out on to the disk. The controller
803 * is permitted to write back the cache any way it wants. (default if battery
804 * backed NVRAM is present). It can be useful to set this for swap regardless of
805 * battery state.
806 */
807#define CACHE_WRITEBACK 18
808/* Optimise for under powered controllers, especially on RAID1 and RAID0. We
809 * write large I/O's directly to disk bypassing the cache to avoid the extra
810 * memory copy hits. Small writes are writeback cached
811 */
812#define CACHE_SMARTBACK 19
813/* Optimise for under powered controllers, especially on RAID1 and RAID0. We
814 * write large I/O's directly to disk bypassing the cache to avoid the extra
815 * memory copy hits. Small writes are writethrough cached. Suitable for devices
816 * lacking battery backup
817 */
818#define CACHE_SMARTTHROUGH 20
819
820/*
821 * Ioctl structures
822 */
823
824#define BLKI2OGRSTRAT _IOR('2', 1, int)
825#define BLKI2OGWSTRAT _IOR('2', 2, int)
826#define BLKI2OSRSTRAT _IOW('2', 3, int)
827#define BLKI2OSWSTRAT _IOW('2', 4, int)
828
829/*
830 * I2O Function codes
831 */
832
833/*
834 * Executive Class
835 */
836#define I2O_CMD_ADAPTER_ASSIGN 0xB3
837#define I2O_CMD_ADAPTER_READ 0xB2
838#define I2O_CMD_ADAPTER_RELEASE 0xB5
839#define I2O_CMD_BIOS_INFO_SET 0xA5
840#define I2O_CMD_BOOT_DEVICE_SET 0xA7
841#define I2O_CMD_CONFIG_VALIDATE 0xBB
842#define I2O_CMD_CONN_SETUP 0xCA
843#define I2O_CMD_DDM_DESTROY 0xB1
844#define I2O_CMD_DDM_ENABLE 0xD5
845#define I2O_CMD_DDM_QUIESCE 0xC7
846#define I2O_CMD_DDM_RESET 0xD9
847#define I2O_CMD_DDM_SUSPEND 0xAF
848#define I2O_CMD_DEVICE_ASSIGN 0xB7
849#define I2O_CMD_DEVICE_RELEASE 0xB9
850#define I2O_CMD_HRT_GET 0xA8
851#define I2O_CMD_ADAPTER_CLEAR 0xBE
852#define I2O_CMD_ADAPTER_CONNECT 0xC9
853#define I2O_CMD_ADAPTER_RESET 0xBD
854#define I2O_CMD_LCT_NOTIFY 0xA2
855#define I2O_CMD_OUTBOUND_INIT 0xA1
856#define I2O_CMD_PATH_ENABLE 0xD3
857#define I2O_CMD_PATH_QUIESCE 0xC5
858#define I2O_CMD_PATH_RESET 0xD7
859#define I2O_CMD_STATIC_MF_CREATE 0xDD
860#define I2O_CMD_STATIC_MF_RELEASE 0xDF
861#define I2O_CMD_STATUS_GET 0xA0
862#define I2O_CMD_SW_DOWNLOAD 0xA9
863#define I2O_CMD_SW_UPLOAD 0xAB
864#define I2O_CMD_SW_REMOVE 0xAD
865#define I2O_CMD_SYS_ENABLE 0xD1
866#define I2O_CMD_SYS_MODIFY 0xC1
867#define I2O_CMD_SYS_QUIESCE 0xC3
868#define I2O_CMD_SYS_TAB_SET 0xA3
869
870/*
871 * Utility Class
872 */
873#define I2O_CMD_UTIL_NOP 0x00
874#define I2O_CMD_UTIL_ABORT 0x01
875#define I2O_CMD_UTIL_CLAIM 0x09
876#define I2O_CMD_UTIL_RELEASE 0x0B
877#define I2O_CMD_UTIL_PARAMS_GET 0x06
878#define I2O_CMD_UTIL_PARAMS_SET 0x05
879#define I2O_CMD_UTIL_EVT_REGISTER 0x13
880#define I2O_CMD_UTIL_EVT_ACK 0x14
881#define I2O_CMD_UTIL_CONFIG_DIALOG 0x10
882#define I2O_CMD_UTIL_DEVICE_RESERVE 0x0D
883#define I2O_CMD_UTIL_DEVICE_RELEASE 0x0F
884#define I2O_CMD_UTIL_LOCK 0x17
885#define I2O_CMD_UTIL_LOCK_RELEASE 0x19
886#define I2O_CMD_UTIL_REPLY_FAULT_NOTIFY 0x15
887
888/*
889 * SCSI Host Bus Adapter Class
890 */
891#define I2O_CMD_SCSI_EXEC 0x81
892#define I2O_CMD_SCSI_ABORT 0x83
893#define I2O_CMD_SCSI_BUSRESET 0x27
894
895/*
896 * Bus Adapter Class
897 */
898#define I2O_CMD_BUS_ADAPTER_RESET 0x85
899#define I2O_CMD_BUS_RESET 0x87
900#define I2O_CMD_BUS_SCAN 0x89
901#define I2O_CMD_BUS_QUIESCE 0x8b
902
903/*
904 * Random Block Storage Class
905 */
906#define I2O_CMD_BLOCK_READ 0x30
907#define I2O_CMD_BLOCK_WRITE 0x31
908#define I2O_CMD_BLOCK_CFLUSH 0x37
909#define I2O_CMD_BLOCK_MLOCK 0x49
910#define I2O_CMD_BLOCK_MUNLOCK 0x4B
911#define I2O_CMD_BLOCK_MMOUNT 0x41
912#define I2O_CMD_BLOCK_MEJECT 0x43
913#define I2O_CMD_BLOCK_POWER 0x70
914
915#define I2O_CMD_PRIVATE 0xFF
916
917/* Command status values */
918
919#define I2O_CMD_IN_PROGRESS 0x01
920#define I2O_CMD_REJECTED 0x02
921#define I2O_CMD_FAILED 0x03
922#define I2O_CMD_COMPLETED 0x04
923
924/* I2O API function return values */
925
926#define I2O_RTN_NO_ERROR 0
927#define I2O_RTN_NOT_INIT 1
928#define I2O_RTN_FREE_Q_EMPTY 2
929#define I2O_RTN_TCB_ERROR 3
930#define I2O_RTN_TRANSACTION_ERROR 4
931#define I2O_RTN_ADAPTER_ALREADY_INIT 5
932#define I2O_RTN_MALLOC_ERROR 6
933#define I2O_RTN_ADPTR_NOT_REGISTERED 7
934#define I2O_RTN_MSG_REPLY_TIMEOUT 8
935#define I2O_RTN_NO_STATUS 9
936#define I2O_RTN_NO_FIRM_VER 10
937#define I2O_RTN_NO_LINK_SPEED 11
938
939/* Reply message status defines for all messages */
940
941#define I2O_REPLY_STATUS_SUCCESS 0x00
942#define I2O_REPLY_STATUS_ABORT_DIRTY 0x01
943#define I2O_REPLY_STATUS_ABORT_NO_DATA_TRANSFER 0x02
944#define I2O_REPLY_STATUS_ABORT_PARTIAL_TRANSFER 0x03
945#define I2O_REPLY_STATUS_ERROR_DIRTY 0x04
946#define I2O_REPLY_STATUS_ERROR_NO_DATA_TRANSFER 0x05
947#define I2O_REPLY_STATUS_ERROR_PARTIAL_TRANSFER 0x06
948#define I2O_REPLY_STATUS_PROCESS_ABORT_DIRTY 0x08
949#define I2O_REPLY_STATUS_PROCESS_ABORT_NO_DATA_TRANSFER 0x09
950#define I2O_REPLY_STATUS_PROCESS_ABORT_PARTIAL_TRANSFER 0x0A
951#define I2O_REPLY_STATUS_TRANSACTION_ERROR 0x0B
952#define I2O_REPLY_STATUS_PROGRESS_REPORT 0x80
953
954/* Status codes and Error Information for Parameter functions */
955
956#define I2O_PARAMS_STATUS_SUCCESS 0x00
957#define I2O_PARAMS_STATUS_BAD_KEY_ABORT 0x01
958#define I2O_PARAMS_STATUS_BAD_KEY_CONTINUE 0x02
959#define I2O_PARAMS_STATUS_BUFFER_FULL 0x03
960#define I2O_PARAMS_STATUS_BUFFER_TOO_SMALL 0x04
961#define I2O_PARAMS_STATUS_FIELD_UNREADABLE 0x05
962#define I2O_PARAMS_STATUS_FIELD_UNWRITEABLE 0x06
963#define I2O_PARAMS_STATUS_INSUFFICIENT_FIELDS 0x07
964#define I2O_PARAMS_STATUS_INVALID_GROUP_ID 0x08
965#define I2O_PARAMS_STATUS_INVALID_OPERATION 0x09
966#define I2O_PARAMS_STATUS_NO_KEY_FIELD 0x0A
967#define I2O_PARAMS_STATUS_NO_SUCH_FIELD 0x0B
968#define I2O_PARAMS_STATUS_NON_DYNAMIC_GROUP 0x0C
969#define I2O_PARAMS_STATUS_OPERATION_ERROR 0x0D
970#define I2O_PARAMS_STATUS_SCALAR_ERROR 0x0E
971#define I2O_PARAMS_STATUS_TABLE_ERROR 0x0F
972#define I2O_PARAMS_STATUS_WRONG_GROUP_TYPE 0x10
973
974/* DetailedStatusCode defines for Executive, DDM, Util and Transaction error
975 * messages: Table 3-2 Detailed Status Codes.*/
976
977#define I2O_DSC_SUCCESS 0x0000
978#define I2O_DSC_BAD_KEY 0x0002
979#define I2O_DSC_TCL_ERROR 0x0003
980#define I2O_DSC_REPLY_BUFFER_FULL 0x0004
981#define I2O_DSC_NO_SUCH_PAGE 0x0005
982#define I2O_DSC_INSUFFICIENT_RESOURCE_SOFT 0x0006
983#define I2O_DSC_INSUFFICIENT_RESOURCE_HARD 0x0007
984#define I2O_DSC_CHAIN_BUFFER_TOO_LARGE 0x0009
985#define I2O_DSC_UNSUPPORTED_FUNCTION 0x000A
986#define I2O_DSC_DEVICE_LOCKED 0x000B
987#define I2O_DSC_DEVICE_RESET 0x000C
988#define I2O_DSC_INAPPROPRIATE_FUNCTION 0x000D
989#define I2O_DSC_INVALID_INITIATOR_ADDRESS 0x000E
990#define I2O_DSC_INVALID_MESSAGE_FLAGS 0x000F
991#define I2O_DSC_INVALID_OFFSET 0x0010
992#define I2O_DSC_INVALID_PARAMETER 0x0011
993#define I2O_DSC_INVALID_REQUEST 0x0012
994#define I2O_DSC_INVALID_TARGET_ADDRESS 0x0013
995#define I2O_DSC_MESSAGE_TOO_LARGE 0x0014
996#define I2O_DSC_MESSAGE_TOO_SMALL 0x0015
997#define I2O_DSC_MISSING_PARAMETER 0x0016
998#define I2O_DSC_TIMEOUT 0x0017
999#define I2O_DSC_UNKNOWN_ERROR 0x0018
1000#define I2O_DSC_UNKNOWN_FUNCTION 0x0019
1001#define I2O_DSC_UNSUPPORTED_VERSION 0x001A
1002#define I2O_DSC_DEVICE_BUSY 0x001B
1003#define I2O_DSC_DEVICE_NOT_AVAILABLE 0x001C
1004
1005/* DetailedStatusCode defines for Block Storage Operation: Table 6-7 Detailed
1006 Status Codes.*/
1007
1008#define I2O_BSA_DSC_SUCCESS 0x0000
1009#define I2O_BSA_DSC_MEDIA_ERROR 0x0001
1010#define I2O_BSA_DSC_ACCESS_ERROR 0x0002
1011#define I2O_BSA_DSC_DEVICE_FAILURE 0x0003
1012#define I2O_BSA_DSC_DEVICE_NOT_READY 0x0004
1013#define I2O_BSA_DSC_MEDIA_NOT_PRESENT 0x0005
1014#define I2O_BSA_DSC_MEDIA_LOCKED 0x0006
1015#define I2O_BSA_DSC_MEDIA_FAILURE 0x0007
1016#define I2O_BSA_DSC_PROTOCOL_FAILURE 0x0008
1017#define I2O_BSA_DSC_BUS_FAILURE 0x0009
1018#define I2O_BSA_DSC_ACCESS_VIOLATION 0x000A
1019#define I2O_BSA_DSC_WRITE_PROTECTED 0x000B
1020#define I2O_BSA_DSC_DEVICE_RESET 0x000C
1021#define I2O_BSA_DSC_VOLUME_CHANGED 0x000D
1022#define I2O_BSA_DSC_TIMEOUT 0x000E
1023
1024/* FailureStatusCodes, Table 3-3 Message Failure Codes */
1025
1026#define I2O_FSC_TRANSPORT_SERVICE_SUSPENDED 0x81
1027#define I2O_FSC_TRANSPORT_SERVICE_TERMINATED 0x82
1028#define I2O_FSC_TRANSPORT_CONGESTION 0x83
1029#define I2O_FSC_TRANSPORT_FAILURE 0x84
1030#define I2O_FSC_TRANSPORT_STATE_ERROR 0x85
1031#define I2O_FSC_TRANSPORT_TIME_OUT 0x86
1032#define I2O_FSC_TRANSPORT_ROUTING_FAILURE 0x87
1033#define I2O_FSC_TRANSPORT_INVALID_VERSION 0x88
1034#define I2O_FSC_TRANSPORT_INVALID_OFFSET 0x89
1035#define I2O_FSC_TRANSPORT_INVALID_MSG_FLAGS 0x8A
1036#define I2O_FSC_TRANSPORT_FRAME_TOO_SMALL 0x8B
1037#define I2O_FSC_TRANSPORT_FRAME_TOO_LARGE 0x8C
1038#define I2O_FSC_TRANSPORT_INVALID_TARGET_ID 0x8D
1039#define I2O_FSC_TRANSPORT_INVALID_INITIATOR_ID 0x8E
1040#define I2O_FSC_TRANSPORT_INVALID_INITIATOR_CONTEXT 0x8F
1041#define I2O_FSC_TRANSPORT_UNKNOWN_FAILURE 0xFF
1042
1043/* Device Claim Types */
1044#define I2O_CLAIM_PRIMARY 0x01000000
1045#define I2O_CLAIM_MANAGEMENT 0x02000000
1046#define I2O_CLAIM_AUTHORIZED 0x03000000
1047#define I2O_CLAIM_SECONDARY 0x04000000
1048
1049/* Message header defines for VersionOffset */
1050#define I2OVER15 0x0001
1051#define I2OVER20 0x0002
1052
1053/* Default is 1.5 */
1054#define I2OVERSION I2OVER15
1055
1056#define SGL_OFFSET_0 I2OVERSION
1057#define SGL_OFFSET_4 (0x0040 | I2OVERSION)
1058#define SGL_OFFSET_5 (0x0050 | I2OVERSION)
1059#define SGL_OFFSET_6 (0x0060 | I2OVERSION)
1060#define SGL_OFFSET_7 (0x0070 | I2OVERSION)
1061#define SGL_OFFSET_8 (0x0080 | I2OVERSION)
1062#define SGL_OFFSET_9 (0x0090 | I2OVERSION)
1063#define SGL_OFFSET_10 (0x00A0 | I2OVERSION)
1064#define SGL_OFFSET_11 (0x00B0 | I2OVERSION)
1065#define SGL_OFFSET_12 (0x00C0 | I2OVERSION)
1066#define SGL_OFFSET(x) (((x)<<4) | I2OVERSION)
1067
1068/* Transaction Reply Lists (TRL) Control Word structure */
1069#define TRL_SINGLE_FIXED_LENGTH 0x00
1070#define TRL_SINGLE_VARIABLE_LENGTH 0x40
1071#define TRL_MULTIPLE_FIXED_LENGTH 0x80
1072
1073 /* msg header defines for MsgFlags */
1074#define MSG_STATIC 0x0100
1075#define MSG_64BIT_CNTXT 0x0200
1076#define MSG_MULTI_TRANS 0x1000
1077#define MSG_FAIL 0x2000
1078#define MSG_FINAL 0x4000
1079#define MSG_REPLY 0x8000
1080
1081 /* minimum size msg */
1082#define THREE_WORD_MSG_SIZE 0x00030000
1083#define FOUR_WORD_MSG_SIZE 0x00040000
1084#define FIVE_WORD_MSG_SIZE 0x00050000
1085#define SIX_WORD_MSG_SIZE 0x00060000
1086#define SEVEN_WORD_MSG_SIZE 0x00070000
1087#define EIGHT_WORD_MSG_SIZE 0x00080000
1088#define NINE_WORD_MSG_SIZE 0x00090000
1089#define TEN_WORD_MSG_SIZE 0x000A0000
1090#define ELEVEN_WORD_MSG_SIZE 0x000B0000
1091#define I2O_MESSAGE_SIZE(x) ((x)<<16)
1092
1093/* special TID assignments */
1094#define ADAPTER_TID 0
1095#define HOST_TID 1
1096
1097/* outbound queue defines */
1098#define I2O_MAX_OUTBOUND_MSG_FRAMES 128
1099#define I2O_OUTBOUND_MSG_FRAME_SIZE 128 /* in 32-bit words */
1100
1101#define I2O_POST_WAIT_OK 0
1102#define I2O_POST_WAIT_TIMEOUT -ETIMEDOUT
1103
1104#define I2O_CONTEXT_LIST_MIN_LENGTH 15
1105#define I2O_CONTEXT_LIST_USED 0x01
1106#define I2O_CONTEXT_LIST_DELETED 0x02
1107
1108/* timeouts */
1109#define I2O_TIMEOUT_INIT_OUTBOUND_QUEUE 15
1110#define I2O_TIMEOUT_MESSAGE_GET 5
1111#define I2O_TIMEOUT_RESET 30
1112#define I2O_TIMEOUT_STATUS_GET 5
1113#define I2O_TIMEOUT_LCT_GET 360
1114#define I2O_TIMEOUT_SCSI_SCB_ABORT 240
1115
1116/* retries */
1117#define I2O_HRT_GET_TRIES 3
1118#define I2O_LCT_GET_TRIES 3
1119
1120/* defines for max_sectors and max_phys_segments */
1121#define I2O_MAX_SECTORS 1024
1122#define I2O_MAX_SECTORS_LIMITED 256
1123#define I2O_MAX_PHYS_SEGMENTS MAX_PHYS_SEGMENTS
1124
1125#endif /* __KERNEL__ */
1126#endif /* _I2O_H */