| 1 | |
| 2 | * This file is subject to the terms and conditions of the GNU General Public
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| 3 | * License. See the file "COPYING" in the main directory of this archive
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| 4 | * for more details.
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| 5 | *
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| 6 | * Copyright (C) 1994, 95, 96, 99, 2001 Ralf Baechle
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| 7 | * Copyright (C) 1994, 1995, 1996 Paul M. Antoine.
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| 8 | * Copyright (C) 1999 Silicon Graphics, Inc.
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| 9 |
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| 10 | #ifndef _ASM_STACKFRAME_H
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| 11 | #define _ASM_STACKFRAME_H
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| 12 |
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| 13 | #include <linux/threads.h>
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| 14 |
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| 15 | #include <asm/asm.h>
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| 16 | #include <asm/asmmacro.h>
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| 17 | #include <asm/mipsregs.h>
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| 18 | #include <asm/asm-offsets.h>
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| 19 |
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| 20 | #ifdef CONFIG_MIPS_MT_SMTC
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| 21 | #include <asm/mipsmtregs.h>
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| 22 | #endif
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| 23 |
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| 24 | .macro SAVE_AT
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| 25 | .set push
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| 26 | .set noat
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| 27 | LONG_S $1, PT_R1(sp)
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| 28 | .set pop
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| 29 | .endm
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| 30 |
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| 31 | .macro SAVE_TEMP
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| 32 | mfhi v1
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| 33 | #ifdef CONFIG_32BIT
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| 34 | LONG_S $8, PT_R8(sp)
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| 35 | LONG_S $9, PT_R9(sp)
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| 36 | #endif
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| 37 | LONG_S v1, PT_HI(sp)
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| 38 | mflo v1
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| 39 | LONG_S $10, PT_R10(sp)
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| 40 | LONG_S $11, PT_R11(sp)
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| 41 | LONG_S v1, PT_LO(sp)
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| 42 | LONG_S $12, PT_R12(sp)
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| 43 | LONG_S $13, PT_R13(sp)
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| 44 | LONG_S $14, PT_R14(sp)
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| 45 | LONG_S $15, PT_R15(sp)
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| 46 | LONG_S $24, PT_R24(sp)
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| 47 | .endm
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| 48 |
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| 49 | .macro SAVE_STATIC
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| 50 | LONG_S $16, PT_R16(sp)
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| 51 | LONG_S $17, PT_R17(sp)
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| 52 | LONG_S $18, PT_R18(sp)
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| 53 | LONG_S $19, PT_R19(sp)
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| 54 | LONG_S $20, PT_R20(sp)
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| 55 | LONG_S $21, PT_R21(sp)
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| 56 | LONG_S $22, PT_R22(sp)
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| 57 | LONG_S $23, PT_R23(sp)
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| 58 | LONG_S $30, PT_R30(sp)
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| 59 | .endm
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| 60 |
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| 61 | #ifdef CONFIG_SMP
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| 62 | #ifdef CONFIG_MIPS_MT_SMTC
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| 63 | #define PTEBASE_SHIFT 19
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| 64 | #else
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| 65 | #define PTEBASE_SHIFT 23
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| 66 | #endif
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| 67 | .macro get_saved_sp
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| 68 | #ifdef CONFIG_MIPS_MT_SMTC
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| 69 | mfc0 k0, CP0_TCBIND
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| 70 | #else
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| 71 | MFC0 k0, CP0_CONTEXT
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| 72 | #endif
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| 73 | #if defined(CONFIG_BUILD_ELF64) || (defined(CONFIG_64BIT) && __GNUC__ < 4)
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| 74 | lui k1, %highest(kernelsp)
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| 75 | daddiu k1, %higher(kernelsp)
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| 76 | dsll k1, 16
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| 77 | daddiu k1, %hi(kernelsp)
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| 78 | dsll k1, 16
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| 79 | #else
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| 80 | lui k1, %hi(kernelsp)
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| 81 | #endif
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| 82 | LONG_SRL k0, PTEBASE_SHIFT
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| 83 | LONG_ADDU k1, k0
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| 84 | LONG_L k1, %lo(kernelsp)(k1)
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| 85 | .endm
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| 86 |
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| 87 | .macro set_saved_sp stackp temp temp2
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| 88 | #ifdef CONFIG_MIPS_MT_SMTC
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| 89 | mfc0 \temp, CP0_TCBIND
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| 90 | #else
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| 91 | MFC0 \temp, CP0_CONTEXT
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| 92 | #endif
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| 93 | LONG_SRL \temp, PTEBASE_SHIFT
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| 94 | LONG_S \stackp, kernelsp(\temp)
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| 95 | .endm
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| 96 | #else
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| 97 | .macro get_saved_sp
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| 98 | #if defined(CONFIG_BUILD_ELF64) || (defined(CONFIG_64BIT) && __GNUC__ < 4)
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| 99 | lui k1, %highest(kernelsp)
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| 100 | daddiu k1, %higher(kernelsp)
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| 101 | dsll k1, k1, 16
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| 102 | daddiu k1, %hi(kernelsp)
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| 103 | dsll k1, k1, 16
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| 104 | #else
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| 105 | lui k1, %hi(kernelsp)
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| 106 | #endif
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| 107 | LONG_L k1, %lo(kernelsp)(k1)
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| 108 | .endm
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| 109 |
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| 110 | .macro set_saved_sp stackp temp temp2
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| 111 | LONG_S \stackp, kernelsp
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| 112 | .endm
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| 113 | #endif
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| 114 |
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| 115 | .macro SAVE_SOME
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| 116 | .set push
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| 117 | .set noat
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| 118 | .set reorder
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| 119 | mfc0 k0, CP0_STATUS
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| 120 | sll k0, 3
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| 121 | .set noreorder
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| 122 | bltz k0, 8f
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| 123 | move k1, sp
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| 124 | .set reorder
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| 125 |
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| 126 | get_saved_sp
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| 127 | 8: move k0, sp
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| 128 | PTR_SUBU sp, k1, PT_SIZE
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| 129 | LONG_S k0, PT_R29(sp)
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| 130 | LONG_S $3, PT_R3(sp)
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| 131 | |
| 132 | * You might think that you don't need to save $0,
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| 133 | * but the FPU emulator and gdb remote debug stub
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| 134 | * need it to operate correctly
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| 135 |
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| 136 | LONG_S $0, PT_R0(sp)
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| 137 | mfc0 v1, CP0_STATUS
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| 138 | LONG_S $2, PT_R2(sp)
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| 139 | LONG_S v1, PT_STATUS(sp)
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| 140 | #ifdef CONFIG_MIPS_MT_SMTC
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| 141 | |
| 142 | * Ideally, these instructions would be shuffled in
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| 143 | * to cover the pipeline delay.
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| 144 |
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| 145 | .set mips32
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| 146 | mfc0 v1, CP0_TCSTATUS
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| 147 | .set mips0
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| 148 | LONG_S v1, PT_TCSTATUS(sp)
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| 149 | #endif
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| 150 | LONG_S $4, PT_R4(sp)
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| 151 | mfc0 v1, CP0_CAUSE
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| 152 | LONG_S $5, PT_R5(sp)
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| 153 | LONG_S v1, PT_CAUSE(sp)
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| 154 | LONG_S $6, PT_R6(sp)
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| 155 | MFC0 v1, CP0_EPC
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| 156 | LONG_S $7, PT_R7(sp)
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| 157 | #ifdef CONFIG_64BIT
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| 158 | LONG_S $8, PT_R8(sp)
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| 159 | LONG_S $9, PT_R9(sp)
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| 160 | #endif
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| 161 | LONG_S v1, PT_EPC(sp)
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| 162 | LONG_S $25, PT_R25(sp)
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| 163 | LONG_S $28, PT_R28(sp)
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| 164 | LONG_S $31, PT_R31(sp)
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| 165 | ori $28, sp, _THREAD_MASK
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| 166 | xori $28, _THREAD_MASK
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| 167 | .set pop
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| 168 | .endm
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| 169 |
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| 170 | .macro SAVE_ALL
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| 171 | SAVE_SOME
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| 172 | SAVE_AT
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| 173 | SAVE_TEMP
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| 174 | SAVE_STATIC
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| 175 | .endm
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| 176 |
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| 177 | .macro RESTORE_AT
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| 178 | .set push
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| 179 | .set noat
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| 180 | LONG_L $1, PT_R1(sp)
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| 181 | .set pop
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| 182 | .endm
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| 183 |
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| 184 | .macro RESTORE_TEMP
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| 185 | LONG_L $24, PT_LO(sp)
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| 186 | #ifdef CONFIG_32BIT
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| 187 | LONG_L $8, PT_R8(sp)
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| 188 | LONG_L $9, PT_R9(sp)
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| 189 | #endif
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| 190 | mtlo $24
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| 191 | LONG_L $24, PT_HI(sp)
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| 192 | LONG_L $10, PT_R10(sp)
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| 193 | LONG_L $11, PT_R11(sp)
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| 194 | mthi $24
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| 195 | LONG_L $12, PT_R12(sp)
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| 196 | LONG_L $13, PT_R13(sp)
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| 197 | LONG_L $14, PT_R14(sp)
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| 198 | LONG_L $15, PT_R15(sp)
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| 199 | LONG_L $24, PT_R24(sp)
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| 200 | .endm
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| 201 |
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| 202 | .macro RESTORE_STATIC
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| 203 | LONG_L $16, PT_R16(sp)
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| 204 | LONG_L $17, PT_R17(sp)
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| 205 | LONG_L $18, PT_R18(sp)
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| 206 | LONG_L $19, PT_R19(sp)
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| 207 | LONG_L $20, PT_R20(sp)
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| 208 | LONG_L $21, PT_R21(sp)
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| 209 | LONG_L $22, PT_R22(sp)
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| 210 | LONG_L $23, PT_R23(sp)
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| 211 | LONG_L $30, PT_R30(sp)
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| 212 | .endm
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| 213 |
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| 214 | #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
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| 215 |
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| 216 | .macro RESTORE_SOME
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| 217 | .set push
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| 218 | .set reorder
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| 219 | .set noat
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| 220 | mfc0 a0, CP0_STATUS
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| 221 | ori a0, 0x1f
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| 222 | xori a0, 0x1f
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| 223 | mtc0 a0, CP0_STATUS
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| 224 | li v1, 0xff00
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| 225 | and a0, v1
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| 226 | LONG_L v0, PT_STATUS(sp)
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| 227 | nor v1, $0, v1
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| 228 | and v0, v1
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| 229 | or v0, a0
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| 230 | mtc0 v0, CP0_STATUS
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| 231 | LONG_L $31, PT_R31(sp)
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| 232 | LONG_L $28, PT_R28(sp)
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| 233 | LONG_L $25, PT_R25(sp)
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| 234 | #ifdef CONFIG_64BIT
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| 235 | LONG_L $8, PT_R8(sp)
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| 236 | LONG_L $9, PT_R9(sp)
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| 237 | #endif
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| 238 | LONG_L $7, PT_R7(sp)
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| 239 | LONG_L $6, PT_R6(sp)
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| 240 | LONG_L $5, PT_R5(sp)
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| 241 | LONG_L $4, PT_R4(sp)
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| 242 | LONG_L $3, PT_R3(sp)
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| 243 | LONG_L $2, PT_R2(sp)
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| 244 | .set pop
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| 245 | .endm
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| 246 |
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| 247 | .macro RESTORE_SP_AND_RET
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| 248 | .set push
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| 249 | .set noreorder
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| 250 | LONG_L k0, PT_EPC(sp)
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| 251 | LONG_L sp, PT_R29(sp)
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| 252 | jr k0
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| 253 | rfe
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| 254 | .set pop
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| 255 | .endm
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| 256 |
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| 257 | #else
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| 258 | |
| 259 | * For SMTC kernel, global IE should be left set, and interrupts
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| 260 | * controlled exclusively via IXMT.
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| 261 |
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| 262 |
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| 263 | #ifdef CONFIG_MIPS_MT_SMTC
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| 264 | #define STATMASK 0x1e
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| 265 | #else
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| 266 | #define STATMASK 0x1f
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| 267 | #endif
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| 268 | .macro RESTORE_SOME
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| 269 | .set push
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| 270 | .set reorder
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| 271 | .set noat
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| 272 | #ifdef CONFIG_MIPS_MT_SMTC
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| 273 | .set mips32r2
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| 274 | |
| 275 | * This may not really be necessary if ints are already
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| 276 | * inhibited here.
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| 277 |
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| 278 | mfc0 v0, CP0_TCSTATUS
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| 279 | ori v0, TCSTATUS_IXMT
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| 280 | mtc0 v0, CP0_TCSTATUS
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| 281 | _ehb
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| 282 | DMT 5 # dmt a1
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| 283 | jal mips_ihb
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| 284 | #endif
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| 285 | mfc0 a0, CP0_STATUS
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| 286 | ori a0, STATMASK
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| 287 | xori a0, STATMASK
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| 288 | mtc0 a0, CP0_STATUS
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| 289 | li v1, 0xff00
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| 290 | and a0, v1
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| 291 | LONG_L v0, PT_STATUS(sp)
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| 292 | nor v1, $0, v1
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| 293 | and v0, v1
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| 294 | or v0, a0
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| 295 | mtc0 v0, CP0_STATUS
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| 296 | #ifdef CONFIG_MIPS_MT_SMTC
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| 297 | |
| 298 | * Only after EXL/ERL have been restored to status can we
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| 299 | * restore TCStatus.IXMT.
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| 300 |
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| 301 | LONG_L v1, PT_TCSTATUS(sp)
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| 302 | _ehb
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| 303 | mfc0 v0, CP0_TCSTATUS
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| 304 | andi v1, TCSTATUS_IXMT
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| 305 |
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| 306 | xori v0, v0, TCSTATUS_IXMT
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| 307 | or v0, v0, v1
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| 308 | mtc0 v0, CP0_TCSTATUS
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| 309 | _ehb
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| 310 | andi a1, a1, VPECONTROL_TE
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| 311 | beqz a1, 1f
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| 312 | emt
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| 313 | 1:
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| 314 | .set mips0
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| 315 | #endif
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| 316 | LONG_L v1, PT_EPC(sp)
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| 317 | MTC0 v1, CP0_EPC
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| 318 | LONG_L $31, PT_R31(sp)
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| 319 | LONG_L $28, PT_R28(sp)
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| 320 | LONG_L $25, PT_R25(sp)
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| 321 | #ifdef CONFIG_64BIT
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| 322 | LONG_L $8, PT_R8(sp)
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| 323 | LONG_L $9, PT_R9(sp)
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| 324 | #endif
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| 325 | LONG_L $7, PT_R7(sp)
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| 326 | LONG_L $6, PT_R6(sp)
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| 327 | LONG_L $5, PT_R5(sp)
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| 328 | LONG_L $4, PT_R4(sp)
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| 329 | LONG_L $3, PT_R3(sp)
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| 330 | LONG_L $2, PT_R2(sp)
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| 331 | .set pop
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| 332 | .endm
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| 333 |
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| 334 | .macro RESTORE_SP_AND_RET
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| 335 | LONG_L sp, PT_R29(sp)
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| 336 | .set mips3
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| 337 | eret
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| 338 | .set mips0
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| 339 | .endm
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| 340 |
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| 341 | #endif
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| 342 |
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| 343 | .macro RESTORE_SP
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| 344 | LONG_L sp, PT_R29(sp)
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| 345 | .endm
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| 346 |
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| 347 | .macro RESTORE_ALL
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| 348 | RESTORE_TEMP
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| 349 | RESTORE_STATIC
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| 350 | RESTORE_AT
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| 351 | RESTORE_SOME
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| 352 | RESTORE_SP
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| 353 | .endm
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| 354 |
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| 355 | .macro RESTORE_ALL_AND_RET
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| 356 | RESTORE_TEMP
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| 357 | RESTORE_STATIC
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| 358 | RESTORE_AT
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| 359 | RESTORE_SOME
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| 360 | RESTORE_SP_AND_RET
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| 361 | .endm
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| 362 |
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| 363 | |
| 364 | * Move to kernel mode and disable interrupts.
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| 365 | * Set cp0 enable bit as sign that we're running on the kernel stack
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| 366 |
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| 367 | .macro CLI
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| 368 | #if !defined(CONFIG_MIPS_MT_SMTC)
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| 369 | mfc0 t0, CP0_STATUS
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| 370 | li t1, ST0_CU0 | 0x1f
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| 371 | or t0, t1
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| 372 | xori t0, 0x1f
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| 373 | mtc0 t0, CP0_STATUS
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| 374 | #else
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| 375 | |
| 376 | * For SMTC, we need to set privilege
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| 377 | * and disable interrupts only for the
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| 378 | * current TC, using the TCStatus register.
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| 379 |
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| 380 | mfc0 t0,CP0_TCSTATUS
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| 381 |
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| 382 |
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| 383 | li t1, ST0_CU0 | 0x08001c00
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| 384 | or t0,t1
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| 385 |
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| 386 | xori t0, 0x00001800
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| 387 | mtc0 t0, CP0_TCSTATUS
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| 388 | _ehb
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| 389 |
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| 390 | mfc0 t0, CP0_STATUS
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| 391 | ori t0, ST0_EXL | ST0_ERL
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| 392 | xori t0, ST0_EXL | ST0_ERL
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| 393 | mtc0 t0, CP0_STATUS
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| 394 | #endif
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| 395 | irq_disable_hazard
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| 396 | .endm
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| 397 |
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| 398 | |
| 399 | * Move to kernel mode and enable interrupts.
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| 400 | * Set cp0 enable bit as sign that we're running on the kernel stack
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| 401 |
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| 402 | .macro STI
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| 403 | #if !defined(CONFIG_MIPS_MT_SMTC)
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| 404 | mfc0 t0, CP0_STATUS
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| 405 | li t1, ST0_CU0 | 0x1f
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| 406 | or t0, t1
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| 407 | xori t0, 0x1e
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| 408 | mtc0 t0, CP0_STATUS
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| 409 | #else
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| 410 | |
| 411 | * For SMTC, we need to set privilege
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| 412 | * and enable interrupts only for the
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| 413 | * current TC, using the TCStatus register.
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| 414 |
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| 415 | _ehb
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| 416 | mfc0 t0,CP0_TCSTATUS
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| 417 |
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| 418 |
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| 419 | li t1, ST0_CU0 | 0x08001c00
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| 420 | or t0,t1
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| 421 |
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| 422 | xori t0, 0x00001c00
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| 423 | mtc0 t0, CP0_TCSTATUS
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| 424 | _ehb
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| 425 |
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| 426 | mfc0 t0, CP0_STATUS
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| 427 | ori t0, ST0_EXL
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| 428 | xori t0, ST0_EXL
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| 429 | mtc0 t0, CP0_STATUS
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| 430 |
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| 431 | #endif
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| 432 | irq_enable_hazard
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| 433 | .endm
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| 434 |
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| 435 | |
| 436 | * Just move to kernel mode and leave interrupts as they are.
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| 437 | * Set cp0 enable bit as sign that we're running on the kernel stack
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| 438 |
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| 439 | .macro KMODE
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| 440 | #ifdef CONFIG_MIPS_MT_SMTC
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| 441 | |
| 442 | * This gets baroque in SMTC. We want to
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| 443 | * protect the non-atomic clearing of EXL
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| 444 | * with DMT/EMT, but we don't want to take
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| 445 | * an interrupt while DMT is still in effect.
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| 446 |
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| 447 |
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| 448 |
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| 449 | .set push
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| 450 | .set mips32r2
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| 451 | .set noreorder
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| 452 | mfc0 v0, CP0_TCSTATUS
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| 453 | andi v1, v0, TCSTATUS_IXMT
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| 454 | ori v0, TCSTATUS_IXMT
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| 455 | mtc0 v0, CP0_TCSTATUS
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| 456 | _ehb
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| 457 | DMT 2 # dmt v0
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| 458 | |
| 459 | * We don't know a priori if ra is "live"
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| 460 |
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| 461 | move t0, ra
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| 462 | jal mips_ihb
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| 463 | nop
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| 464 | move ra, t0
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| 465 | #endif
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| 466 | mfc0 t0, CP0_STATUS
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| 467 | li t1, ST0_CU0 | 0x1e
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| 468 | or t0, t1
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| 469 | xori t0, 0x1e
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| 470 | mtc0 t0, CP0_STATUS
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| 471 | #ifdef CONFIG_MIPS_MT_SMTC
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| 472 | _ehb
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| 473 | andi v0, v0, VPECONTROL_TE
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| 474 | beqz v0, 2f
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| 475 | nop
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| 476 | emt
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| 477 | 2:
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| 478 | mfc0 v0, CP0_TCSTATUS
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| 479 |
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| 480 | ori v0, TCSTATUS_IXMT
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| 481 | xori v0, TCSTATUS_IXMT
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| 482 | or v0, v1, v0
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| 483 | mtc0 v0, CP0_TCSTATUS
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| 484 | |
| 485 | * irq_disable_hazard below should expand to EHB
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| 486 | * on 24K/34K CPUS
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| 487 |
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| 488 | .set pop
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| 489 | #endif
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| 490 | irq_disable_hazard
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| 491 | .endm
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| 492 |
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| 493 | #endif
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