| 1 | |
| 2 | * This file is subject to the terms and conditions of the GNU General Public
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| 3 | * License. See the file "COPYING" in the main directory of this archive
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| 4 | * for more details.
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| 5 | *
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| 6 | * Copyright (C) 1994 - 2002 by Ralf Baechle
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| 7 | * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
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| 8 | * Copyright (C) 2002 Maciej W. Rozycki
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| 9 |
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| 10 | #ifndef _ASM_PGTABLE_BITS_H
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| 11 | #define _ASM_PGTABLE_BITS_H
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| 12 |
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| 13 |
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| 14 | |
| 15 | * Note that we shift the lower 32bits of each EntryLo[01] entry
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| 16 | * 6 bits to the left. That way we can convert the PFN into the
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| 17 | * physical address by a single 'and' operation and gain 6 additional
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| 18 | * bits for storing information which isn't present in a normal
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| 19 | * MIPS page table.
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| 20 | *
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| 21 | * Similar to the Alpha port, we need to keep track of the ref
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| 22 | * and mod bits in software. We have a software "yeah you can read
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| 23 | * from this page" bit, and a hardware one which actually lets the
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| 24 | * process read from the page. On the same token we have a software
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| 25 | * writable bit and the real hardware one which actually lets the
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| 26 | * process write to the page, this keeps a mod bit via the hardware
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| 27 | * dirty bit.
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| 28 | *
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| 29 | * Certain revisions of the R4000 and R5000 have a bug where if a
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| 30 | * certain sequence occurs in the last 3 instructions of an executable
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| 31 | * page, and the following page is not mapped, the cpu can do
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| 32 | * unpredictable things. The code (when it is written) to deal with
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| 33 | * this problem will be in the update_mmu_cache() code for the r4k.
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| 34 |
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| 35 | #if defined(CONFIG_CPU_MIPS32_R1) && defined(CONFIG_64BIT_PHYS_ADDR)
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| 36 |
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| 37 | #define _PAGE_PRESENT (1<<6)
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| 38 | #define _PAGE_READ (1<<7)
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| 39 | #define _PAGE_WRITE (1<<8)
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| 40 | #define _PAGE_ACCESSED (1<<9)
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| 41 | #define _PAGE_MODIFIED (1<<10)
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| 42 | #define _PAGE_FILE (1<<10)
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| 43 |
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| 44 | #define _PAGE_R4KBUG (1<<0)
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| 45 | #define _PAGE_GLOBAL (1<<0)
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| 46 | #define _PAGE_VALID (1<<1)
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| 47 | #define _PAGE_SILENT_READ (1<<1)
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| 48 | #define _PAGE_DIRTY (1<<2)
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| 49 | #define _PAGE_SILENT_WRITE (1<<2)
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| 50 | #define _CACHE_MASK (7<<3)
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| 51 |
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| 52 | |
| 53 | * dependent.
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| 54 |
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| 55 | #define _CACHE_UNCACHED (2<<3)
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| 56 | #define _CACHE_CACHABLE_NONCOHERENT (3<<3)
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| 57 | #define _CACHE_CACHABLE_COW (3<<3)
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| 58 |
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| 59 | #else
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| 60 |
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| 61 | #define _PAGE_PRESENT (1<<0)
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| 62 | #define _PAGE_READ (1<<1)
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| 63 | #define _PAGE_WRITE (1<<2)
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| 64 | #define _PAGE_ACCESSED (1<<3)
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| 65 | #define _PAGE_MODIFIED (1<<4)
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| 66 | #define _PAGE_FILE (1<<4)
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| 67 |
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| 68 | #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
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| 69 |
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| 70 | #define _PAGE_GLOBAL (1<<8)
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| 71 | #define _PAGE_VALID (1<<9)
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| 72 | #define _PAGE_SILENT_READ (1<<9)
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| 73 | #define _PAGE_DIRTY (1<<10)
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| 74 | #define _PAGE_SILENT_WRITE (1<<10)
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| 75 | #define _CACHE_UNCACHED (1<<11)
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| 76 | #define _CACHE_MASK (1<<11)
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| 77 | #define _CACHE_CACHABLE_NONCOHERENT 0
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| 78 |
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| 79 | #else
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| 80 | #define _PAGE_R4KBUG (1<<5)
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| 81 | #define _PAGE_GLOBAL (1<<6)
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| 82 | #define _PAGE_VALID (1<<7)
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| 83 | #define _PAGE_SILENT_READ (1<<7)
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| 84 | #define _PAGE_DIRTY (1<<8)
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| 85 | #define _PAGE_SILENT_WRITE (1<<8)
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| 86 | #define _CACHE_MASK (7<<9)
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| 87 |
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| 88 | #ifdef CONFIG_CPU_SB1
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| 89 |
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| 90 | |
| 91 | use it for "noncoherent" spaces, too. Shouldn't hurt.
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| 92 |
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| 93 | #define _CACHE_UNCACHED (2<<9)
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| 94 | #define _CACHE_CACHABLE_COW (5<<9)
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| 95 | #define _CACHE_CACHABLE_NONCOHERENT (5<<9)
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| 96 | #define _CACHE_UNCACHED_ACCELERATED (7<<9)
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| 97 |
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| 98 | #elif defined(CONFIG_CPU_RM9000)
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| 99 |
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| 100 | #define _CACHE_WT (0 << 9)
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| 101 | #define _CACHE_WTWA (1 << 9)
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| 102 | #define _CACHE_UC_B (2 << 9)
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| 103 | #define _CACHE_WB (3 << 9)
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| 104 | #define _CACHE_CWBEA (4 << 9)
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| 105 | #define _CACHE_CWB (5 << 9)
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| 106 | #define _CACHE_UCNB (6 << 9)
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| 107 | #define _CACHE_FPC (7 << 9)
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| 108 |
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| 109 | #define _CACHE_UNCACHED _CACHE_UC_B
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| 110 | #define _CACHE_CACHABLE_NONCOHERENT _CACHE_WB
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| 111 |
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| 112 | #else
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| 113 |
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| 114 | #define _CACHE_CACHABLE_NO_WA (0<<9)
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| 115 | #define _CACHE_CACHABLE_WA (1<<9)
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| 116 | #define _CACHE_UNCACHED (2<<9)
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| 117 | #define _CACHE_CACHABLE_NONCOHERENT (3<<9)
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| 118 | #define _CACHE_CACHABLE_CE (4<<9)
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| 119 | #define _CACHE_CACHABLE_COW (5<<9)
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| 120 | #define _CACHE_CACHABLE_CUW (6<<9)
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| 121 | #define _CACHE_UNCACHED_ACCELERATED (7<<9)
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| 122 |
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| 123 | #endif
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| 124 | #endif
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| 125 | #endif
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| 126 |
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| 127 | #define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED)
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| 128 | #define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED)
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| 129 |
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| 130 | #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK)
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| 131 |
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| 132 | #ifdef CONFIG_MIPS_UNCACHED
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| 133 | #define PAGE_CACHABLE_DEFAULT _CACHE_UNCACHED
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| 134 | #elif defined(CONFIG_DMA_NONCOHERENT)
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| 135 | #define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_NONCOHERENT
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| 136 | #elif defined(CONFIG_CPU_RM9000)
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| 137 | #define PAGE_CACHABLE_DEFAULT _CACHE_CWB
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| 138 | #else
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| 139 | #define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_COW
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| 140 | #endif
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| 141 |
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| 142 | #if defined(CONFIG_CPU_MIPS32_R1) && defined(CONFIG_64BIT_PHYS_ADDR)
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| 143 | #define CONF_CM_DEFAULT (PAGE_CACHABLE_DEFAULT >> 3)
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| 144 | #else
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| 145 | #define CONF_CM_DEFAULT (PAGE_CACHABLE_DEFAULT >> 9)
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| 146 | #endif
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| 147 |
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| 148 | #endif
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