| 1 | |
| 2 | * include/asm-parisc/cache.h
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| 3 |
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| 4 |
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| 5 | #ifndef __ARCH_PARISC_CACHE_H
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| 6 | #define __ARCH_PARISC_CACHE_H
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| 7 |
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| 8 |
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| 9 | |
| 10 | * PA 2.0 processors have 64-byte cachelines; PA 1.1 processors have
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| 11 | * 32-byte cachelines. The default configuration is not for SMP anyway,
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| 12 | * so if you're building for SMP, you should select the appropriate
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| 13 | * processor type. There is a potential livelock danger when running
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| 14 | * a machine with this value set too small, but it's more probable you'll
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| 15 | * just ruin performance.
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| 16 |
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| 17 | #ifdef CONFIG_PA20
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| 18 | #define L1_CACHE_BYTES 64
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| 19 | #define L1_CACHE_SHIFT 6
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| 20 | #else
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| 21 | #define L1_CACHE_BYTES 32
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| 22 | #define L1_CACHE_SHIFT 5
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| 23 | #endif
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| 24 |
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| 25 | #ifndef __ASSEMBLY__
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| 26 |
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| 27 | #define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
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| 28 |
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| 29 | #define SMP_CACHE_BYTES L1_CACHE_BYTES
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| 30 |
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| 31 | #define __read_mostly __attribute__((__section__(".data.read_mostly")))
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| 32 |
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| 33 | void parisc_cache_init(void);
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| 34 | void disable_sr_hashing_asm(int);
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| 35 | void disable_sr_hashing(void);
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| 36 | void free_sid(unsigned long);
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| 37 | unsigned long alloc_sid(void);
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| 38 |
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| 39 | struct seq_file;
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| 40 | extern void show_cache_info(struct seq_file *m);
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| 41 |
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| 42 | extern int split_tlb;
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| 43 | extern int dcache_stride;
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| 44 | extern int icache_stride;
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| 45 | extern struct pdc_cache_info cache_info;
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| 46 | void parisc_setup_cache_timing(void);
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| 47 |
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| 48 | #define pdtlb(addr) asm volatile("pdtlb 0(%%sr1,%0)" : : "r" (addr));
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| 49 | #define pitlb(addr) asm volatile("pitlb 0(%%sr1,%0)" : : "r" (addr));
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| 50 | #define pdtlb_kernel(addr) asm volatile("pdtlb 0(%0)" : : "r" (addr));
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| 51 |
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| 52 | #endif
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| 53 |
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| 54 |
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| 55 |
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| 56 | #define SRHASH_PCXST 0
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| 57 | #define SRHASH_PCXL 1
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| 58 | #define SRHASH_PA20 2
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| 59 |
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| 60 | #endif
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