| 1 | #ifdef __KERNEL__
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| 2 | #ifndef _PPC_PGTABLE_H
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| 3 | #define _PPC_PGTABLE_H
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| 4 |
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| 5 | #include <asm-generic/4level-fixup.h>
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| 6 |
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| 7 |
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| 8 | #ifndef __ASSEMBLY__
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| 9 | #include <linux/sched.h>
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| 10 | #include <linux/threads.h>
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| 11 | #include <asm/processor.h>
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| 12 | #include <asm/mmu.h>
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| 13 | #include <asm/page.h>
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| 14 | #include <asm/io.h>
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| 15 | struct mm_struct;
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| 16 |
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| 17 | extern unsigned long va_to_phys(unsigned long address);
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| 18 | extern pte_t *va_to_pte(unsigned long address);
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| 19 | extern unsigned long ioremap_bot, ioremap_base;
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| 20 | #endif
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| 21 |
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| 22 | |
| 23 | * The PowerPC MMU uses a hash table containing PTEs, together with
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| 24 | * a set of 16 segment registers (on 32-bit implementations), to define
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| 25 | * the virtual to physical address mapping.
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| 26 | *
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| 27 | * We use the hash table as an extended TLB, i.e. a cache of currently
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| 28 | * active mappings. We maintain a two-level page table tree, much
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| 29 | * like that used by the i386, for the sake of the Linux memory
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| 30 | * management code. Low-level assembler code in hashtable.S
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| 31 | * (procedure hash_page) is responsible for extracting ptes from the
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| 32 | * tree and putting them into the hash table when necessary, and
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| 33 | * updating the accessed and modified bits in the page table tree.
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| 34 |
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| 35 |
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| 36 | |
| 37 | * The PowerPC MPC8xx uses a TLB with hardware assisted, software tablewalk.
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| 38 | * We also use the two level tables, but we can put the real bits in them
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| 39 | * needed for the TLB and tablewalk. These definitions require Mx_CTR.PPM = 0,
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| 40 | * Mx_CTR.PPCS = 0, and MD_CTR.TWAM = 1. The level 2 descriptor has
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| 41 | * additional page protection (when Mx_CTR.PPCS = 1) that allows TLB hit
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| 42 | * based upon user/super access. The TLB does not have accessed nor write
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| 43 | * protect. We assume that if the TLB get loaded with an entry it is
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| 44 | * accessed, and overload the changed bit for write protect. We use
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| 45 | * two bits in the software pte that are supposed to be set to zero in
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| 46 | * the TLB entry (24 and 25) for these indicators. Although the level 1
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| 47 | * descriptor contains the guarded and writethrough/copyback bits, we can
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| 48 | * set these at the page level since they get copied from the Mx_TWC
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| 49 | * register when the TLB entry is loaded. We will use bit 27 for guard, since
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| 50 | * that is where it exists in the MD_TWC, and bit 26 for writethrough.
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| 51 | * These will get masked from the level 2 descriptor at TLB load time, and
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| 52 | * copied to the MD_TWC before it gets loaded.
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| 53 | * Large page sizes added. We currently support two sizes, 4K and 8M.
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| 54 | * This also allows a TLB hander optimization because we can directly
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| 55 | * load the PMD into MD_TWC. The 8M pages are only used for kernel
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| 56 | * mapping of well known areas. The PMD (PGD) entries contain control
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| 57 | * flags in addition to the address, so care must be taken that the
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| 58 | * software no longer assumes these are only pointers.
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| 59 |
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| 60 |
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| 61 | |
| 62 | * At present, all PowerPC 400-class processors share a similar TLB
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| 63 | * architecture. The instruction and data sides share a unified,
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| 64 | * 64-entry, fully-associative TLB which is maintained totally under
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| 65 | * software control. In addition, the instruction side has a
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| 66 | * hardware-managed, 4-entry, fully-associative TLB which serves as a
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| 67 | * first level to the shared TLB. These two TLBs are known as the UTLB
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| 68 | * and ITLB, respectively (see "mmu.h" for definitions).
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| 69 |
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| 70 |
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| 71 | |
| 72 | * The normal case is that PTEs are 32-bits and we have a 1-page
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| 73 | * 1024-entry pgdir pointing to 1-page 1024-entry PTE pages. -- paulus
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| 74 | *
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| 75 | * For any >32-bit physical address platform, we can use the following
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| 76 | * two level page table layout where the pgdir is 8KB and the MS 13 bits
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| 77 | * are an index to the second level table. The combined pgdir/pmd first
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| 78 | * level has 2048 entries and the second level has 512 64-bit PTE entries.
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| 79 | * -Matt
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| 80 |
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| 81 |
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| 82 | #define PMD_SHIFT (PAGE_SHIFT + PTE_SHIFT)
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| 83 | #define PMD_SIZE (1UL << PMD_SHIFT)
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| 84 | #define PMD_MASK (~(PMD_SIZE-1))
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| 85 |
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| 86 |
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| 87 | #define PGDIR_SHIFT PMD_SHIFT
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| 88 | #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
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| 89 | #define PGDIR_MASK (~(PGDIR_SIZE-1))
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| 90 |
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| 91 | |
| 92 | * entries per page directory level: our page-table tree is two-level, so
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| 93 | * we don't really have any PMD directory.
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| 94 |
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| 95 | #define PTRS_PER_PTE (1 << PTE_SHIFT)
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| 96 | #define PTRS_PER_PMD 1
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| 97 | #define PTRS_PER_PGD (1 << (32 - PGDIR_SHIFT))
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| 98 |
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| 99 | #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
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| 100 | #define FIRST_USER_ADDRESS 0
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| 101 |
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| 102 | #define USER_PGD_PTRS (PAGE_OFFSET >> PGDIR_SHIFT)
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| 103 | #define KERNEL_PGD_PTRS (PTRS_PER_PGD-USER_PGD_PTRS)
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| 104 |
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| 105 | #define pte_ERROR(e) \
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| 106 | printk("%s:%d: bad pte "PTE_FMT".\n", __FILE__, __LINE__, pte_val(e))
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| 107 | #define pmd_ERROR(e) \
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| 108 | printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
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| 109 | #define pgd_ERROR(e) \
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| 110 | printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
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| 111 |
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| 112 | |
| 113 | * Just any arbitrary offset to the start of the vmalloc VM area: the
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| 114 | * current 64MB value just means that there will be a 64MB "hole" after the
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| 115 | * physical memory until the kernel virtual memory starts. That means that
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| 116 | * any out-of-bounds memory accesses will hopefully be caught.
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| 117 | * The vmalloc() routines leaves a hole of 4kB between each vmalloced
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| 118 | * area for the same reason. ;)
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| 119 | *
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| 120 | * We no longer map larger than phys RAM with the BATs so we don't have
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| 121 | * to worry about the VMALLOC_OFFSET causing problems. We do have to worry
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| 122 | * about clashes between our early calls to ioremap() that start growing down
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| 123 | * from ioremap_base being run into the VM area allocations (growing upwards
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| 124 | * from VMALLOC_START). For this reason we have ioremap_bot to check when
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| 125 | * we actually run into our mappings setup in the early boot with the VM
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| 126 | * system. This really does become a problem for machines with good amounts
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| 127 | * of RAM. -- Cort
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| 128 |
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| 129 | #define VMALLOC_OFFSET (0x1000000)
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| 130 | #ifdef PPC_PIN_SIZE
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| 131 | #define VMALLOC_START (((_ALIGN((long)high_memory, PPC_PIN_SIZE) + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
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| 132 | #else
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| 133 | #define VMALLOC_START ((((long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
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| 134 | #endif
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| 135 | #define VMALLOC_END ioremap_bot
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| 136 |
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| 137 | |
| 138 | * Bits in a linux-style PTE. These match the bits in the
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| 139 | * (hardware-defined) PowerPC PTE as closely as possible.
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| 140 |
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| 141 |
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| 142 | #if defined(CONFIG_40x)
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| 143 |
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| 144 | |
| 145 | field looks like this:
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| 146 |
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| 147 | 0 1 2 3 4 ... 18 19 20 21 22 23 24 25 26 27 28 29 30 31
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| 148 | RPN..................... 0 0 EX WR ZSEL....... W I M G
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| 149 |
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| 150 | Where possible we make the Linux PTE bits match up with this
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| 151 |
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| 152 | - bits 20 and 21 must be cleared, because we use 4k pages (40x can
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| 153 | support down to 1k pages), this is done in the TLBMiss exception
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| 154 | handler.
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| 155 | - We use only zones 0 (for kernel pages) and 1 (for user pages)
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| 156 | of the 16 available. Bit 24-26 of the TLB are cleared in the TLB
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| 157 | miss handler. Bit 27 is PAGE_USER, thus selecting the correct
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| 158 | zone.
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| 159 | - PRESENT *must* be in the bottom two bits because swap cache
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| 160 | entries use the top 30 bits. Because 40x doesn't support SMP
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| 161 | anyway, M is irrelevant so we borrow it for PAGE_PRESENT. Bit 30
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| 162 | is cleared in the TLB miss handler before the TLB entry is loaded.
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| 163 | - All other bits of the PTE are loaded into TLBLO without
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| 164 | modification, leaving us only the bits 20, 21, 24, 25, 26, 30 for
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| 165 | software PTE bits. We actually use use bits 21, 24, 25, and
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| 166 | 30 respectively for the software bits: ACCESSED, DIRTY, RW, and
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| 167 | PRESENT.
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| 168 |
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| 169 |
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| 170 |
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| 171 | #define _PAGE_GUARDED 0x001
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| 172 | #define _PAGE_FILE 0x001
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| 173 | #define _PAGE_PRESENT 0x002
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| 174 | #define _PAGE_NO_CACHE 0x004
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| 175 | #define _PAGE_WRITETHRU 0x008
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| 176 | #define _PAGE_USER 0x010
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| 177 | #define _PAGE_RW 0x040
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| 178 | #define _PAGE_DIRTY 0x080
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| 179 | #define _PAGE_HWWRITE 0x100
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| 180 | #define _PAGE_HWEXEC 0x200
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| 181 | #define _PAGE_ACCESSED 0x400
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| 182 |
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| 183 | #define _PMD_PRESENT 0x400
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| 184 | #define _PMD_BAD 0x802
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| 185 | #define _PMD_SIZE 0x0e0
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| 186 | #define _PMD_SIZE_4M 0x0c0
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| 187 | #define _PMD_SIZE_16M 0x0e0
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| 188 | #define PMD_PAGE_SIZE(pmdval) (1024 << (((pmdval) & _PMD_SIZE) >> 4))
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| 189 |
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| 190 | #elif defined(CONFIG_44x)
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| 191 | |
| 192 | * Definitions for PPC440
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| 193 | *
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| 194 | * Because of the 3 word TLB entries to support 36-bit addressing,
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| 195 | * the attribute are difficult to map in such a fashion that they
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| 196 | * are easily loaded during exception processing. I decided to
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| 197 | * organize the entry so the ERPN is the only portion in the
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| 198 | * upper word of the PTE and the attribute bits below are packed
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| 199 | * in as sensibly as they can be in the area below a 4KB page size
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| 200 | * oriented RPN. This at least makes it easy to load the RPN and
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| 201 | * ERPN fields in the TLB. -Matt
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| 202 | *
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| 203 | * Note that these bits preclude future use of a page size
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| 204 | * less than 4KB.
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| 205 | *
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| 206 | *
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| 207 | * PPC 440 core has following TLB attribute fields;
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| 208 | *
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| 209 | * TLB1:
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| 210 | * 0 1 2 3 4 ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
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| 211 | * RPN................................. - - - - - - ERPN.......
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| 212 | *
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| 213 | * TLB2:
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| 214 | * 0 1 2 3 4 ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
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| 215 | * - - - - - - U0 U1 U2 U3 W I M G E - UX UW UR SX SW SR
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| 216 | *
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| 217 | * There are some constrains and options, to decide mapping software bits
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| 218 | * into TLB entry.
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| 219 | *
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| 220 | * - PRESENT *must* be in the bottom three bits because swap cache
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| 221 | * entries use the top 29 bits for TLB2.
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| 222 | *
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| 223 | * - FILE *must* be in the bottom three bits because swap cache
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| 224 | * entries use the top 29 bits for TLB2.
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| 225 | *
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| 226 | * - CACHE COHERENT bit (M) has no effect on PPC440 core, because it
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| 227 | * doesn't support SMP. So we can use this as software bit, like
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| 228 | * DIRTY.
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| 229 | *
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| 230 | * With the PPC 44x Linux implementation, the 0-11th LSBs of the PTE are used
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| 231 | * for memory protection related functions (see PTE structure in
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| 232 | * include/asm-ppc/mmu.h). The _PAGE_XXX definitions in this file map to the
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| 233 | * above bits. Note that the bit values are CPU specific, not architecture
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| 234 | * specific.
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| 235 | *
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| 236 | * The kernel PTE entry holds an arch-dependent swp_entry structure under
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| 237 | * certain situations. In other words, in such situations some portion of
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| 238 | * the PTE bits are used as a swp_entry. In the PPC implementation, the
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| 239 | * 3-24th LSB are shared with swp_entry, however the 0-2nd three LSB still
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| 240 | * hold protection values. That means the three protection bits are
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| 241 | * reserved for both PTE and SWAP entry at the most significant three
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| 242 | * LSBs.
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| 243 | *
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| 244 | * There are three protection bits available for SWAP entry:
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| 245 | * _PAGE_PRESENT
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| 246 | * _PAGE_FILE
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| 247 | * _PAGE_HASHPTE (if HW has)
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| 248 | *
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| 249 | * So those three bits have to be inside of 0-2nd LSB of PTE.
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| 250 | *
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| 251 |
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| 252 |
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| 253 | #define _PAGE_PRESENT 0x00000001
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| 254 | #define _PAGE_RW 0x00000002
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| 255 | #define _PAGE_FILE 0x00000004
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| 256 | #define _PAGE_ACCESSED 0x00000008
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| 257 | #define _PAGE_HWWRITE 0x00000010
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| 258 | #define _PAGE_HWEXEC 0x00000020
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| 259 | #define _PAGE_USER 0x00000040
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| 260 | #define _PAGE_ENDIAN 0x00000080
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| 261 | #define _PAGE_GUARDED 0x00000100
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| 262 | #define _PAGE_DIRTY 0x00000200
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| 263 | #define _PAGE_NO_CACHE 0x00000400
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| 264 | #define _PAGE_WRITETHRU 0x00000800
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| 265 |
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| 266 |
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| 267 | #define _PMD_PRESENT 0
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| 268 | #define _PMD_PRESENT_MASK (PAGE_MASK)
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| 269 | #define _PMD_BAD (~PAGE_MASK)
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| 270 |
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| 271 |
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| 272 | #define _PTE_NONE_MASK 0xffffffff00000000ULL
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| 273 |
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| 274 | #elif defined(CONFIG_FSL_BOOKE)
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| 275 | |
| 276 | MMU Assist Register 3:
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| 277 |
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| 278 | 32 33 34 35 36 ... 50 51 52 53 54 55 56 57 58 59 60 61 62 63
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| 279 | RPN...................... 0 0 U0 U1 U2 U3 UX SX UW SW UR SR
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| 280 |
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| 281 | - PRESENT *must* be in the bottom three bits because swap cache
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| 282 | entries use the top 29 bits.
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| 283 |
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| 284 | - FILE *must* be in the bottom three bits because swap cache
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| 285 | entries use the top 29 bits.
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| 286 |
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| 287 |
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| 288 |
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| 289 | #define _PAGE_PRESENT 0x00001
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| 290 | #define _PAGE_USER 0x00002
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| 291 | #define _PAGE_FILE 0x00002
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| 292 | #define _PAGE_ACCESSED 0x00004
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| 293 | #define _PAGE_HWWRITE 0x00008
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| 294 | #define _PAGE_RW 0x00010
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| 295 | #define _PAGE_HWEXEC 0x00020
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| 296 |
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| 297 | #define _PAGE_ENDIAN 0x00040
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| 298 | #define _PAGE_GUARDED 0x00080
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| 299 | #define _PAGE_COHERENT 0x00100
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| 300 | #define _PAGE_NO_CACHE 0x00200
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| 301 | #define _PAGE_WRITETHRU 0x00400
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| 302 |
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| 303 | #ifdef CONFIG_PTE_64BIT
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| 304 | #define _PAGE_DIRTY 0x08000
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| 305 |
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| 306 |
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| 307 | #define _PTE_NONE_MASK 0xffffffffffff0000ULL
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| 308 | #else
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| 309 | #define _PAGE_DIRTY 0x00800
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| 310 | #endif
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| 311 |
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| 312 | #define _PMD_PRESENT 0
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| 313 | #define _PMD_PRESENT_MASK (PAGE_MASK)
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| 314 | #define _PMD_BAD (~PAGE_MASK)
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| 315 |
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| 316 | #elif defined(CONFIG_8xx)
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| 317 |
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| 318 | #define _PAGE_PRESENT 0x0001
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| 319 | #define _PAGE_FILE 0x0002
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| 320 | #define _PAGE_NO_CACHE 0x0002
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| 321 | #define _PAGE_SHARED 0x0004
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| 322 |
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| 323 | |
| 324 | * into the TLB.
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| 325 |
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| 326 | #define _PAGE_EXEC 0x0008
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| 327 | #define _PAGE_GUARDED 0x0010
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| 328 | #define _PAGE_DIRTY 0x0020
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| 329 | #define _PAGE_RW 0x0040
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| 330 | #define _PAGE_ACCESSED 0x0080
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| 331 |
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| 332 | |
| 333 | * require a TLB exception handler change. It is assumed unused bits
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| 334 | * are always zero.
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| 335 |
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| 336 | #define _PAGE_HWWRITE 0x0100
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| 337 | #define _PAGE_USER 0x0800
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| 338 |
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| 339 | #define _PMD_PRESENT 0x0001
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| 340 | #define _PMD_BAD 0x0ff0
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| 341 | #define _PMD_PAGE_MASK 0x000c
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| 342 | #define _PMD_PAGE_8M 0x000c
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| 343 |
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| 344 | |
| 345 | * The 8xx TLB miss handler allegedly sets _PAGE_ACCESSED in the PTE
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| 346 | * for an address even if _PAGE_PRESENT is not set, as a performance
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| 347 | * optimization. This is a bug if you ever want to use swap unless
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| 348 | * _PAGE_ACCESSED is 2, which it isn't, or unless you have 8xx-specific
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| 349 | * definitions for __swp_entry etc. below, which would be gross.
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| 350 | * -- paulus
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| 351 |
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| 352 | #define _PTE_NONE_MASK _PAGE_ACCESSED
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| 353 |
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| 354 | #else
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| 355 |
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| 356 | #define _PAGE_PRESENT 0x001
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| 357 | #define _PAGE_HASHPTE 0x002
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| 358 | #define _PAGE_FILE 0x004
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| 359 | #define _PAGE_USER 0x004
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| 360 | #define _PAGE_GUARDED 0x008
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| 361 | #define _PAGE_COHERENT 0x010
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| 362 | #define _PAGE_NO_CACHE 0x020
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| 363 | #define _PAGE_WRITETHRU 0x040
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| 364 | #define _PAGE_DIRTY 0x080
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| 365 | #define _PAGE_ACCESSED 0x100
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| 366 | #define _PAGE_EXEC 0x200
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| 367 | #define _PAGE_RW 0x400
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| 368 |
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| 369 | #define _PTE_NONE_MASK _PAGE_HASHPTE
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| 370 |
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| 371 | #define _PMD_PRESENT 0
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| 372 | #define _PMD_PRESENT_MASK (PAGE_MASK)
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| 373 | #define _PMD_BAD (~PAGE_MASK)
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| 374 | #endif
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| 375 |
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| 376 | |
| 377 | * Some bits are only used on some cpu families...
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| 378 |
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| 379 | #ifndef _PAGE_HASHPTE
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| 380 | #define _PAGE_HASHPTE 0
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| 381 | #endif
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| 382 | #ifndef _PTE_NONE_MASK
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| 383 | #define _PTE_NONE_MASK 0
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| 384 | #endif
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| 385 | #ifndef _PAGE_SHARED
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| 386 | #define _PAGE_SHARED 0
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| 387 | #endif
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| 388 | #ifndef _PAGE_HWWRITE
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| 389 | #define _PAGE_HWWRITE 0
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| 390 | #endif
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| 391 | #ifndef _PAGE_HWEXEC
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| 392 | #define _PAGE_HWEXEC 0
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| 393 | #endif
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| 394 | #ifndef _PAGE_EXEC
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| 395 | #define _PAGE_EXEC 0
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| 396 | #endif
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| 397 | #ifndef _PMD_PRESENT_MASK
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| 398 | #define _PMD_PRESENT_MASK _PMD_PRESENT
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| 399 | #endif
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| 400 | #ifndef _PMD_SIZE
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| 401 | #define _PMD_SIZE 0
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| 402 | #define PMD_PAGE_SIZE(pmd) bad_call_to_PMD_PAGE_SIZE()
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| 403 | #endif
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| 404 |
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| 405 | #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
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| 406 |
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| 407 | |
| 408 | * Note: the _PAGE_COHERENT bit automatically gets set in the hardware
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| 409 | * PTE if CONFIG_SMP is defined (hash_page does this); there is no need
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| 410 | * to have it in the Linux PTE, and in fact the bit could be reused for
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| 411 | * another purpose. -- paulus.
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| 412 |
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| 413 |
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| 414 | #ifdef CONFIG_44x
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| 415 | #define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_GUARDED)
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| 416 | #else
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| 417 | #define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED)
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| 418 | #endif
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| 419 | #define _PAGE_WRENABLE (_PAGE_RW | _PAGE_DIRTY | _PAGE_HWWRITE)
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| 420 | #define _PAGE_KERNEL (_PAGE_BASE | _PAGE_SHARED | _PAGE_WRENABLE)
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| 421 |
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| 422 | #ifdef CONFIG_PPC_STD_MMU
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| 423 | |
| 424 | * so to write-protect kernel memory we must turn on user access
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| 425 | #define _PAGE_KERNEL_RO (_PAGE_BASE | _PAGE_SHARED | _PAGE_USER)
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| 426 | #else
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| 427 | #define _PAGE_KERNEL_RO (_PAGE_BASE | _PAGE_SHARED)
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| 428 | #endif
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| 429 |
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| 430 | #define _PAGE_IO (_PAGE_KERNEL | _PAGE_NO_CACHE | _PAGE_GUARDED)
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| 431 | #define _PAGE_RAM (_PAGE_KERNEL | _PAGE_HWEXEC)
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| 432 |
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| 433 | #if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH)
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| 434 | |
| 435 | * don't write protect the kernel text
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| 436 | #define _PAGE_RAM_TEXT _PAGE_RAM
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| 437 | #else
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| 438 | #define _PAGE_RAM_TEXT (_PAGE_KERNEL_RO | _PAGE_HWEXEC)
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| 439 | #endif
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| 440 |
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| 441 | #define PAGE_NONE __pgprot(_PAGE_BASE)
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| 442 | #define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_USER)
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| 443 | #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
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| 444 | #define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW)
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| 445 | #define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW | _PAGE_EXEC)
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| 446 | #define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_USER)
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| 447 | #define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
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| 448 |
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| 449 | #define PAGE_KERNEL __pgprot(_PAGE_RAM)
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| 450 | #define PAGE_KERNEL_NOCACHE __pgprot(_PAGE_IO)
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| 451 |
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| 452 | |
| 453 | * The PowerPC can only do execute protection on a segment (256MB) basis,
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| 454 | * not on a page basis. So we consider execute permission the same as read.
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| 455 | * Also, write permissions imply read permissions.
|
| 456 | * This is the closest we can get..
|
| 457 |
|
| 458 | #define __P000 PAGE_NONE
|
| 459 | #define __P001 PAGE_READONLY_X
|
| 460 | #define __P010 PAGE_COPY
|
| 461 | #define __P011 PAGE_COPY_X
|
| 462 | #define __P100 PAGE_READONLY
|
| 463 | #define __P101 PAGE_READONLY_X
|
| 464 | #define __P110 PAGE_COPY
|
| 465 | #define __P111 PAGE_COPY_X
|
| 466 |
|
| 467 | #define __S000 PAGE_NONE
|
| 468 | #define __S001 PAGE_READONLY_X
|
| 469 | #define __S010 PAGE_SHARED
|
| 470 | #define __S011 PAGE_SHARED_X
|
| 471 | #define __S100 PAGE_READONLY
|
| 472 | #define __S101 PAGE_READONLY_X
|
| 473 | #define __S110 PAGE_SHARED
|
| 474 | #define __S111 PAGE_SHARED_X
|
| 475 |
|
| 476 | #ifndef __ASSEMBLY__
|
| 477 | |
| 478 | * kernel without large page PMD support
|
| 479 | extern unsigned long bad_call_to_PMD_PAGE_SIZE(void);
|
| 480 |
|
| 481 | |
| 482 | * Conversions between PTE values and page frame numbers.
|
| 483 |
|
| 484 |
|
| 485 | |
| 486 | * allow room for more flags
|
| 487 | #if defined(CONFIG_FSL_BOOKE) && defined(CONFIG_PTE_64BIT)
|
| 488 | #define PFN_SHIFT_OFFSET (PAGE_SHIFT + 8)
|
| 489 | #else
|
| 490 | #define PFN_SHIFT_OFFSET (PAGE_SHIFT)
|
| 491 | #endif
|
| 492 |
|
| 493 | #define pte_pfn(x) (pte_val(x) >> PFN_SHIFT_OFFSET)
|
| 494 | #define pte_page(x) pfn_to_page(pte_pfn(x))
|
| 495 |
|
| 496 | #define pfn_pte(pfn, prot) __pte(((pte_basic_t)(pfn) << PFN_SHIFT_OFFSET) |\
|
| 497 | pgprot_val(prot))
|
| 498 | #define mk_pte(page, prot) pfn_pte(page_to_pfn(page), prot)
|
| 499 |
|
| 500 | |
| 501 | * ZERO_PAGE is a global shared page that is always zero: used
|
| 502 | * for zero-mapped memory areas etc..
|
| 503 |
|
| 504 | extern unsigned long empty_zero_page[1024];
|
| 505 | #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
|
| 506 |
|
| 507 | #endif
|
| 508 |
|
| 509 | #define pte_none(pte) ((pte_val(pte) & ~_PTE_NONE_MASK) == 0)
|
| 510 | #define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT)
|
| 511 | #define pte_clear(mm,addr,ptep) do { set_pte_at((mm), (addr), (ptep), __pte(0)); } while (0)
|
| 512 |
|
| 513 | #define pmd_none(pmd) (!pmd_val(pmd))
|
| 514 | #define pmd_bad(pmd) (pmd_val(pmd) & _PMD_BAD)
|
| 515 | #define pmd_present(pmd) (pmd_val(pmd) & _PMD_PRESENT_MASK)
|
| 516 | #define pmd_clear(pmdp) do { pmd_val(*(pmdp)) = 0; } while (0)
|
| 517 |
|
| 518 | #ifndef __ASSEMBLY__
|
| 519 | |
| 520 | * The "pgd_xxx()" functions here are trivial for a folded two-level
|
| 521 | * setup: the pgd is never bad, and a pmd always exists (as it's folded
|
| 522 | * into the pgd entry)
|
| 523 |
|
| 524 | static inline int pgd_none(pgd_t pgd) { return 0; }
|
| 525 | static inline int pgd_bad(pgd_t pgd) { return 0; }
|
| 526 | static inline int pgd_present(pgd_t pgd) { return 1; }
|
| 527 | #define pgd_clear(xp) do { } while (0)
|
| 528 |
|
| 529 | #define pgd_page_vaddr(pgd) \
|
| 530 | ((unsigned long) __va(pgd_val(pgd) & PAGE_MASK))
|
| 531 |
|
| 532 | |
| 533 | * The following only work if pte_present() is true.
|
| 534 | * Undefined behaviour if not..
|
| 535 |
|
| 536 | static inline int pte_read(pte_t pte) { return pte_val(pte) & _PAGE_USER; }
|
| 537 | static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_RW; }
|
| 538 | static inline int pte_exec(pte_t pte) { return pte_val(pte) & _PAGE_EXEC; }
|
| 539 | static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
|
| 540 | static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
|
| 541 | static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE; }
|
| 542 |
|
| 543 | static inline void pte_uncache(pte_t pte) { pte_val(pte) |= _PAGE_NO_CACHE; }
|
| 544 | static inline void pte_cache(pte_t pte) { pte_val(pte) &= ~_PAGE_NO_CACHE; }
|
| 545 |
|
| 546 | static inline pte_t pte_rdprotect(pte_t pte) {
|
| 547 | pte_val(pte) &= ~_PAGE_USER; return pte; }
|
| 548 | static inline pte_t pte_wrprotect(pte_t pte) {
|
| 549 | pte_val(pte) &= ~(_PAGE_RW | _PAGE_HWWRITE); return pte; }
|
| 550 | static inline pte_t pte_exprotect(pte_t pte) {
|
| 551 | pte_val(pte) &= ~_PAGE_EXEC; return pte; }
|
| 552 | static inline pte_t pte_mkclean(pte_t pte) {
|
| 553 | pte_val(pte) &= ~(_PAGE_DIRTY | _PAGE_HWWRITE); return pte; }
|
| 554 | static inline pte_t pte_mkold(pte_t pte) {
|
| 555 | pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
|
| 556 |
|
| 557 | static inline pte_t pte_mkread(pte_t pte) {
|
| 558 | pte_val(pte) |= _PAGE_USER; return pte; }
|
| 559 | static inline pte_t pte_mkexec(pte_t pte) {
|
| 560 | pte_val(pte) |= _PAGE_USER | _PAGE_EXEC; return pte; }
|
| 561 | static inline pte_t pte_mkwrite(pte_t pte) {
|
| 562 | pte_val(pte) |= _PAGE_RW; return pte; }
|
| 563 | static inline pte_t pte_mkdirty(pte_t pte) {
|
| 564 | pte_val(pte) |= _PAGE_DIRTY; return pte; }
|
| 565 | static inline pte_t pte_mkyoung(pte_t pte) {
|
| 566 | pte_val(pte) |= _PAGE_ACCESSED; return pte; }
|
| 567 |
|
| 568 | static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
|
| 569 | {
|
| 570 | pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot);
|
| 571 | return pte;
|
| 572 | }
|
| 573 |
|
| 574 | |
| 575 | * When flushing the tlb entry for a page, we also need to flush the hash
|
| 576 | * table entry. flush_hash_pages is assembler (for speed) in hashtable.S.
|
| 577 |
|
| 578 | extern int flush_hash_pages(unsigned context, unsigned long va,
|
| 579 | unsigned long pmdval, int count);
|
| 580 |
|
| 581 |
|
| 582 | extern void add_hash_page(unsigned context, unsigned long va,
|
| 583 | unsigned long pmdval);
|
| 584 |
|
| 585 | |
| 586 | * Atomic PTE updates.
|
| 587 | *
|
| 588 | * pte_update clears and sets bit atomically, and returns
|
| 589 | * the old pte value. In the 64-bit PTE case we lock around the
|
| 590 | * low PTE word since we expect ALL flag bits to be there
|
| 591 |
|
| 592 | #ifndef CONFIG_PTE_64BIT
|
| 593 | static inline unsigned long pte_update(pte_t *p, unsigned long clr,
|
| 594 | unsigned long set)
|
| 595 | {
|
| 596 | unsigned long old, tmp;
|
| 597 |
|
| 598 | __asm__ __volatile__("\
|
| 599 | 1: lwarx %0,0,%3\n\
|
| 600 | andc %1,%0,%4\n\
|
| 601 | or %1,%1,%5\n"
|
| 602 | PPC405_ERR77(0,%3)
|
| 603 | " stwcx. %1,0,%3\n\
|
| 604 | bne- 1b"
|
| 605 | : "=&r" (old), "=&r" (tmp), "=m" (*p)
|
| 606 | : "r" (p), "r" (clr), "r" (set), "m" (*p)
|
| 607 | : "cc" );
|
| 608 | return old;
|
| 609 | }
|
| 610 | #else
|
| 611 | static inline unsigned long long pte_update(pte_t *p, unsigned long clr,
|
| 612 | unsigned long set)
|
| 613 | {
|
| 614 | unsigned long long old;
|
| 615 | unsigned long tmp;
|
| 616 |
|
| 617 | __asm__ __volatile__("\
|
| 618 | 1: lwarx %L0,0,%4\n\
|
| 619 | lwzx %0,0,%3\n\
|
| 620 | andc %1,%L0,%5\n\
|
| 621 | or %1,%1,%6\n"
|
| 622 | PPC405_ERR77(0,%3)
|
| 623 | " stwcx. %1,0,%4\n\
|
| 624 | bne- 1b"
|
| 625 | : "=&r" (old), "=&r" (tmp), "=m" (*p)
|
| 626 | : "r" (p), "r" ((unsigned long)(p) + 4), "r" (clr), "r" (set), "m" (*p)
|
| 627 | : "cc" );
|
| 628 | return old;
|
| 629 | }
|
| 630 | #endif
|
| 631 |
|
| 632 | |
| 633 | * set_pte stores a linux PTE into the linux page table.
|
| 634 | * On machines which use an MMU hash table we avoid changing the
|
| 635 | * _PAGE_HASHPTE bit.
|
| 636 |
|
| 637 | static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
|
| 638 | pte_t *ptep, pte_t pte)
|
| 639 | {
|
| 640 | #if _PAGE_HASHPTE != 0
|
| 641 | pte_update(ptep, ~_PAGE_HASHPTE, pte_val(pte) & ~_PAGE_HASHPTE);
|
| 642 | #else
|
| 643 | *ptep = pte;
|
| 644 | #endif
|
| 645 | }
|
| 646 |
|
| 647 | |
| 648 | * 2.6 calles this without flushing the TLB entry, this is wrong
|
| 649 | * for our hash-based implementation, we fix that up here
|
| 650 |
|
| 651 | #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
|
| 652 | static inline int __ptep_test_and_clear_young(unsigned int context, unsigned long addr, pte_t *ptep)
|
| 653 | {
|
| 654 | unsigned long old;
|
| 655 | old = pte_update(ptep, _PAGE_ACCESSED, 0);
|
| 656 | #if _PAGE_HASHPTE != 0
|
| 657 | if (old & _PAGE_HASHPTE) {
|
| 658 | unsigned long ptephys = __pa(ptep) & PAGE_MASK;
|
| 659 | flush_hash_pages(context, addr, ptephys, 1);
|
| 660 | }
|
| 661 | #endif
|
| 662 | return (old & _PAGE_ACCESSED) != 0;
|
| 663 | }
|
| 664 | #define ptep_test_and_clear_young(__vma, __addr, __ptep) \
|
| 665 | __ptep_test_and_clear_young((__vma)->vm_mm->context.id, __addr, __ptep)
|
| 666 |
|
| 667 | #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_DIRTY
|
| 668 | static inline int ptep_test_and_clear_dirty(struct vm_area_struct *vma,
|
| 669 | unsigned long addr, pte_t *ptep)
|
| 670 | {
|
| 671 | return (pte_update(ptep, (_PAGE_DIRTY | _PAGE_HWWRITE), 0) & _PAGE_DIRTY) != 0;
|
| 672 | }
|
| 673 |
|
| 674 | #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
|
| 675 | static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr,
|
| 676 | pte_t *ptep)
|
| 677 | {
|
| 678 | return __pte(pte_update(ptep, ~_PAGE_HASHPTE, 0));
|
| 679 | }
|
| 680 |
|
| 681 | #define __HAVE_ARCH_PTEP_SET_WRPROTECT
|
| 682 | static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
|
| 683 | pte_t *ptep)
|
| 684 | {
|
| 685 | pte_update(ptep, (_PAGE_RW | _PAGE_HWWRITE), 0);
|
| 686 | }
|
| 687 |
|
| 688 | #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
|
| 689 | static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry, int dirty)
|
| 690 | {
|
| 691 | unsigned long bits = pte_val(entry) &
|
| 692 | (_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW);
|
| 693 | pte_update(ptep, 0, bits);
|
| 694 | }
|
| 695 |
|
| 696 | #define ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
|
| 697 | do { \
|
| 698 | __ptep_set_access_flags(__ptep, __entry, __dirty); \
|
| 699 | flush_tlb_page_nohash(__vma, __address); \
|
| 700 | } while(0)
|
| 701 |
|
| 702 | |
| 703 | * Macro to mark a page protection value as "uncacheable".
|
| 704 |
|
| 705 | #define pgprot_noncached(prot) (__pgprot(pgprot_val(prot) | _PAGE_NO_CACHE | _PAGE_GUARDED))
|
| 706 |
|
| 707 | struct file;
|
| 708 | extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
|
| 709 | unsigned long size, pgprot_t vma_prot);
|
| 710 | #define __HAVE_PHYS_MEM_ACCESS_PROT
|
| 711 |
|
| 712 | #define __HAVE_ARCH_PTE_SAME
|
| 713 | #define pte_same(A,B) (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HASHPTE) == 0)
|
| 714 |
|
| 715 | |
| 716 | * Note that on Book E processors, the pmd contains the kernel virtual
|
| 717 | * (lowmem) address of the pte page. The physical address is less useful
|
| 718 | * because everything runs with translation enabled (even the TLB miss
|
| 719 | * handler). On everything else the pmd contains the physical address
|
| 720 | * of the pte page. -- paulus
|
| 721 |
|
| 722 | #ifndef CONFIG_BOOKE
|
| 723 | #define pmd_page_vaddr(pmd) \
|
| 724 | ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
|
| 725 | #define pmd_page(pmd) \
|
| 726 | (mem_map + (pmd_val(pmd) >> PAGE_SHIFT))
|
| 727 | #else
|
| 728 | #define pmd_page_vaddr(pmd) \
|
| 729 | ((unsigned long) (pmd_val(pmd) & PAGE_MASK))
|
| 730 | #define pmd_page(pmd) \
|
| 731 | (mem_map + (__pa(pmd_val(pmd)) >> PAGE_SHIFT))
|
| 732 | #endif
|
| 733 |
|
| 734 |
|
| 735 | #define pgd_offset_k(address) pgd_offset(&init_mm, address)
|
| 736 |
|
| 737 |
|
| 738 | #define pgd_index(address) ((address) >> PGDIR_SHIFT)
|
| 739 | #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
|
| 740 |
|
| 741 |
|
| 742 | static inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address)
|
| 743 | {
|
| 744 | return (pmd_t *) dir;
|
| 745 | }
|
| 746 |
|
| 747 |
|
| 748 | #define pte_index(address) \
|
| 749 | (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
|
| 750 | #define pte_offset_kernel(dir, addr) \
|
| 751 | ((pte_t *) pmd_page_vaddr(*(dir)) + pte_index(addr))
|
| 752 | #define pte_offset_map(dir, addr) \
|
| 753 | ((pte_t *) kmap_atomic(pmd_page(*(dir)), KM_PTE0) + pte_index(addr))
|
| 754 | #define pte_offset_map_nested(dir, addr) \
|
| 755 | ((pte_t *) kmap_atomic(pmd_page(*(dir)), KM_PTE1) + pte_index(addr))
|
| 756 |
|
| 757 | #define pte_unmap(pte) kunmap_atomic(pte, KM_PTE0)
|
| 758 | #define pte_unmap_nested(pte) kunmap_atomic(pte, KM_PTE1)
|
| 759 |
|
| 760 | extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
|
| 761 |
|
| 762 | extern void paging_init(void);
|
| 763 |
|
| 764 | |
| 765 | * Encode and decode a swap entry.
|
| 766 | * Note that the bits we use in a PTE for representing a swap entry
|
| 767 | * must not include the _PAGE_PRESENT bit, the _PAGE_FILE bit, or the
|
| 768 | *_PAGE_HASHPTE bit (if used). -- paulus
|
| 769 |
|
| 770 | #define __swp_type(entry) ((entry).val & 0x1f)
|
| 771 | #define __swp_offset(entry) ((entry).val >> 5)
|
| 772 | #define __swp_entry(type, offset) ((swp_entry_t) { (type) | ((offset) << 5) })
|
| 773 | #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) >> 3 })
|
| 774 | #define __swp_entry_to_pte(x) ((pte_t) { (x).val << 3 })
|
| 775 |
|
| 776 |
|
| 777 | #define PTE_FILE_MAX_BITS 29
|
| 778 | #define pte_to_pgoff(pte) (pte_val(pte) >> 3)
|
| 779 | #define pgoff_to_pte(off) ((pte_t) { ((off) << 3) | _PAGE_FILE })
|
| 780 |
|
| 781 |
|
| 782 |
|
| 783 | extern void cache_clear(__u32 addr, int length);
|
| 784 | extern void cache_push(__u32 addr, int length);
|
| 785 | extern int mm_end_of_chunk (unsigned long addr, int len);
|
| 786 | extern unsigned long iopa(unsigned long addr);
|
| 787 | extern unsigned long mm_ptov(unsigned long addr) __attribute_const__;
|
| 788 |
|
| 789 |
|
| 790 | |
| 791 | compilation errors.
|
| 792 | #define KERNELMAP_FULL_CACHING 0
|
| 793 | #define KERNELMAP_NOCACHE_SER 1
|
| 794 | #define KERNELMAP_NOCACHE_NONSER 2
|
| 795 | #define KERNELMAP_NO_COPYBACK 3
|
| 796 |
|
| 797 | |
| 798 | * Map some physical address range into the kernel address space.
|
| 799 |
|
| 800 | extern unsigned long kernel_map(unsigned long paddr, unsigned long size,
|
| 801 | int nocacheflag, unsigned long *memavailp );
|
| 802 |
|
| 803 | |
| 804 | * Set cache mode of (kernel space) address range.
|
| 805 |
|
| 806 | extern void kernel_set_cachemode (unsigned long address, unsigned long size,
|
| 807 | unsigned int cmode);
|
| 808 |
|
| 809 |
|
| 810 | #define kern_addr_valid(addr) (1)
|
| 811 |
|
| 812 | #ifdef CONFIG_PHYS_64BIT
|
| 813 | extern int remap_pfn_range(struct vm_area_struct *vma, unsigned long from,
|
| 814 | unsigned long paddr, unsigned long size, pgprot_t prot);
|
| 815 |
|
| 816 | static inline int io_remap_pfn_range(struct vm_area_struct *vma,
|
| 817 | unsigned long vaddr,
|
| 818 | unsigned long pfn,
|
| 819 | unsigned long size,
|
| 820 | pgprot_t prot)
|
| 821 | {
|
| 822 | phys_addr_t paddr64 = fixup_bigphys_addr(pfn << PAGE_SHIFT, size);
|
| 823 | return remap_pfn_range(vma, vaddr, paddr64 >> PAGE_SHIFT, size, prot);
|
| 824 | }
|
| 825 | #else
|
| 826 | #define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
|
| 827 | remap_pfn_range(vma, vaddr, pfn, size, prot)
|
| 828 | #endif
|
| 829 |
|
| 830 | #define MK_IOSPACE_PFN(space, pfn) (pfn)
|
| 831 | #define GET_IOSPACE(pfn) 0
|
| 832 | #define GET_PFN(pfn) (pfn)
|
| 833 |
|
| 834 | |
| 835 | * No page table caches to initialise
|
| 836 |
|
| 837 | #define pgtable_cache_init() do { } while (0)
|
| 838 |
|
| 839 | extern int get_pteptr(struct mm_struct *mm, unsigned long addr, pte_t **ptep,
|
| 840 | pmd_t **pmdp);
|
| 841 |
|
| 842 | #include <asm-generic/pgtable.h>
|
| 843 |
|
| 844 | #endif
|
| 845 |
|
| 846 | #endif
|
| 847 | #endif
|