projects/linux·blob v2.6.21 · refs

252 lines · 7.0 KiB

1/*
2 * Copyright (C) 1999 Cort Dougan <[email protected]>
3 */
4#ifndef __PPC_SYSTEM_H
5#define __PPC_SYSTEM_H
6
7#include <linux/kernel.h>
8
9#include <asm/atomic.h>
10#include <asm/hw_irq.h>
11
12/*
13 * Memory barrier.
14 * The sync instruction guarantees that all memory accesses initiated
15 * by this processor have been performed (with respect to all other
16 * mechanisms that access memory). The eieio instruction is a barrier
17 * providing an ordering (separately) for (a) cacheable stores and (b)
18 * loads and stores to non-cacheable memory (e.g. I/O devices).
19 *
20 * mb() prevents loads and stores being reordered across this point.
21 * rmb() prevents loads being reordered across this point.
22 * wmb() prevents stores being reordered across this point.
23 * read_barrier_depends() prevents data-dependent loads being reordered
24 * across this point (nop on PPC).
25 *
26 * We can use the eieio instruction for wmb, but since it doesn't
27 * give any ordering guarantees about loads, we have to use the
28 * stronger but slower sync instruction for mb and rmb.
29 */
30#define mb() __asm__ __volatile__ ("sync" : : : "memory")
31#define rmb() __asm__ __volatile__ ("sync" : : : "memory")
32#define wmb() __asm__ __volatile__ ("eieio" : : : "memory")
33#define read_barrier_depends() do { } while(0)
34
35#define set_mb(var, value) do { var = value; mb(); } while (0)
36
37#ifdef CONFIG_SMP
38#define smp_mb() mb()
39#define smp_rmb() rmb()
40#define smp_wmb() __asm__ __volatile__ ("eieio" : : : "memory")
41#define smp_read_barrier_depends() read_barrier_depends()
42#else
43#define smp_mb() barrier()
44#define smp_rmb() barrier()
45#define smp_wmb() barrier()
46#define smp_read_barrier_depends() do { } while(0)
47#endif /* CONFIG_SMP */
48
49#ifdef __KERNEL__
50struct task_struct;
51struct pt_regs;
52
53extern void print_backtrace(unsigned long *);
54extern void show_regs(struct pt_regs * regs);
55extern void flush_instruction_cache(void);
56extern void hard_reset_now(void);
57extern void poweroff_now(void);
58#ifdef CONFIG_6xx
59extern long _get_L2CR(void);
60extern long _get_L3CR(void);
61extern void _set_L2CR(unsigned long);
62extern void _set_L3CR(unsigned long);
63#else
64#define _get_L2CR() 0L
65#define _get_L3CR() 0L
66#define _set_L2CR(val) do { } while(0)
67#define _set_L3CR(val) do { } while(0)
68#endif
69extern void via_cuda_init(void);
70extern void pmac_nvram_init(void);
71extern void chrp_nvram_init(void);
72extern void read_rtc_time(void);
73extern void pmac_find_display(void);
74extern void giveup_fpu(struct task_struct *);
75extern void disable_kernel_fp(void);
76extern void enable_kernel_fp(void);
77extern void flush_fp_to_thread(struct task_struct *);
78extern void enable_kernel_altivec(void);
79extern void giveup_altivec(struct task_struct *);
80extern void load_up_altivec(struct task_struct *);
81extern int emulate_altivec(struct pt_regs *);
82extern void giveup_spe(struct task_struct *);
83extern void load_up_spe(struct task_struct *);
84extern int fix_alignment(struct pt_regs *);
85extern void cvt_fd(float *from, double *to, struct thread_struct *thread);
86extern void cvt_df(double *from, float *to, struct thread_struct *thread);
87
88#ifndef CONFIG_SMP
89extern void discard_lazy_cpu_state(void);
90#else
91static inline void discard_lazy_cpu_state(void)
92{
93}
94#endif
95
96#ifdef CONFIG_ALTIVEC
97extern void flush_altivec_to_thread(struct task_struct *);
98#else
99static inline void flush_altivec_to_thread(struct task_struct *t)
100{
101}
102#endif
103
104#ifdef CONFIG_SPE
105extern void flush_spe_to_thread(struct task_struct *);
106#else
107static inline void flush_spe_to_thread(struct task_struct *t)
108{
109}
110#endif
111
112extern int call_rtas(const char *, int, int, unsigned long *, ...);
113extern void cacheable_memzero(void *p, unsigned int nb);
114extern void *cacheable_memcpy(void *, const void *, unsigned int);
115extern int do_page_fault(struct pt_regs *, unsigned long, unsigned long);
116extern void bad_page_fault(struct pt_regs *, unsigned long, int);
117extern int die(const char *, struct pt_regs *, long);
118extern void _exception(int, struct pt_regs *, int, unsigned long);
119void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
120
121#ifdef CONFIG_BOOKE_WDT
122extern u32 booke_wdt_enabled;
123extern u32 booke_wdt_period;
124#endif /* CONFIG_BOOKE_WDT */
125
126struct device_node;
127extern void note_scsi_host(struct device_node *, void *);
128
129extern struct task_struct *__switch_to(struct task_struct *,
130 struct task_struct *);
131#define switch_to(prev, next, last) ((last) = __switch_to((prev), (next)))
132
133/*
134 * On SMP systems, when the scheduler does migration-cost autodetection,
135 * it needs a way to flush as much of the CPU's caches as possible.
136 *
137 * TODO: fill this in!
138 */
139static inline void sched_cacheflush(void)
140{
141}
142
143struct thread_struct;
144extern struct task_struct *_switch(struct thread_struct *prev,
145 struct thread_struct *next);
146
147extern unsigned int rtas_data;
148
149static __inline__ unsigned long
150xchg_u32(volatile void *p, unsigned long val)
151{
152 unsigned long prev;
153
154 __asm__ __volatile__ ("\n\
1551: lwarx %0,0,%2 \n"
156 PPC405_ERR77(0,%2)
157" stwcx. %3,0,%2 \n\
158 bne- 1b"
159 : "=&r" (prev), "=m" (*(volatile unsigned long *)p)
160 : "r" (p), "r" (val), "m" (*(volatile unsigned long *)p)
161 : "cc", "memory");
162
163 return prev;
164}
165
166/*
167 * This function doesn't exist, so you'll get a linker error
168 * if something tries to do an invalid xchg().
169 */
170extern void __xchg_called_with_bad_pointer(void);
171
172#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
173#define tas(ptr) (xchg((ptr),1))
174
175static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size)
176{
177 switch (size) {
178 case 4:
179 return (unsigned long) xchg_u32(ptr, x);
180#if 0 /* xchg_u64 doesn't exist on 32-bit PPC */
181 case 8:
182 return (unsigned long) xchg_u64(ptr, x);
183#endif /* 0 */
184 }
185 __xchg_called_with_bad_pointer();
186 return x;
187
188
189}
190
191extern inline void * xchg_ptr(void * m, void * val)
192{
193 return (void *) xchg_u32(m, (unsigned long) val);
194}
195
196
197#define __HAVE_ARCH_CMPXCHG 1
198
199static __inline__ unsigned long
200__cmpxchg_u32(volatile unsigned int *p, unsigned int old, unsigned int new)
201{
202 unsigned int prev;
203
204 __asm__ __volatile__ ("\n\
2051: lwarx %0,0,%2 \n\
206 cmpw 0,%0,%3 \n\
207 bne 2f \n"
208 PPC405_ERR77(0,%2)
209" stwcx. %4,0,%2 \n\
210 bne- 1b\n"
211#ifdef CONFIG_SMP
212" sync\n"
213#endif /* CONFIG_SMP */
214"2:"
215 : "=&r" (prev), "=m" (*p)
216 : "r" (p), "r" (old), "r" (new), "m" (*p)
217 : "cc", "memory");
218
219 return prev;
220}
221
222/* This function doesn't exist, so you'll get a linker error
223 if something tries to do an invalid cmpxchg(). */
224extern void __cmpxchg_called_with_bad_pointer(void);
225
226static __inline__ unsigned long
227__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
228{
229 switch (size) {
230 case 4:
231 return __cmpxchg_u32(ptr, old, new);
232#if 0 /* we don't have __cmpxchg_u64 on 32-bit PPC */
233 case 8:
234 return __cmpxchg_u64(ptr, old, new);
235#endif /* 0 */
236 }
237 __cmpxchg_called_with_bad_pointer();
238 return old;
239}
240
241#define cmpxchg(ptr,o,n) \
242 ({ \
243 __typeof__(*(ptr)) _o_ = (o); \
244 __typeof__(*(ptr)) _n_ = (n); \
245 (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
246 (unsigned long)_n_, sizeof(*(ptr))); \
247 })
248
249#define arch_align_stack(x) (x)
250
251#endif /* __KERNEL__ */
252#endif /* __PPC_SYSTEM_H */