| 1 | |
| 2 | * include/asm-xtensa/cacheasm.h
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| 3 | *
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| 4 | * This file is subject to the terms and conditions of the GNU General Public
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| 5 | * License. See the file "COPYING" in the main directory of this archive
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| 6 | * for more details.
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| 7 | *
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| 8 | * Copyright (C) 2006 Tensilica Inc.
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| 9 |
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| 10 |
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| 11 | #include <asm/cache.h>
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| 12 | #include <asm/asmmacro.h>
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| 13 | #include <linux/stringify.h>
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| 14 |
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| 15 | |
| 16 | * Define cache functions as macros here so that they can be used
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| 17 | * by the kernel and boot loader. We should consider moving them to a
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| 18 | * library that can be linked by both.
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| 19 | *
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| 20 | * Locking
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| 21 | *
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| 22 | * ___unlock_dcache_all
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| 23 | * ___unlock_icache_all
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| 24 | *
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| 25 | * Flush and invaldating
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| 26 | *
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| 27 | * ___flush_invalidate_dcache_{all|range|page}
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| 28 | * ___flush_dcache_{all|range|page}
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| 29 | * ___invalidate_dcache_{all|range|page}
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| 30 | * ___invalidate_icache_{all|range|page}
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| 31 | *
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| 32 |
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| 33 |
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| 34 | .macro __loop_cache_all ar at insn size line_width
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| 35 |
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| 36 | movi \ar, 0
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| 37 |
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| 38 | __loopi \ar, \at, \size, (4 << (\line_width))
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| 39 | \insn \ar, 0 << (\line_width)
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| 40 | \insn \ar, 1 << (\line_width)
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| 41 | \insn \ar, 2 << (\line_width)
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| 42 | \insn \ar, 3 << (\line_width)
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| 43 | __endla \ar, \at, 4 << (\line_width)
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| 44 |
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| 45 | .endm
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| 46 |
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| 47 |
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| 48 | .macro __loop_cache_range ar as at insn line_width
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| 49 |
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| 50 | extui \at, \ar, 0, \line_width
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| 51 | add \as, \as, \at
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| 52 |
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| 53 | __loops \ar, \as, \at, \line_width
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| 54 | \insn \ar, 0
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| 55 | __endla \ar, \at, (1 << (\line_width))
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| 56 |
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| 57 | .endm
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| 58 |
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| 59 |
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| 60 | .macro __loop_cache_page ar at insn line_width
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| 61 |
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| 62 | __loopi \ar, \at, PAGE_SIZE, 4 << (\line_width)
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| 63 | \insn \ar, 0 << (\line_width)
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| 64 | \insn \ar, 1 << (\line_width)
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| 65 | \insn \ar, 2 << (\line_width)
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| 66 | \insn \ar, 3 << (\line_width)
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| 67 | __endla \ar, \at, 4 << (\line_width)
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| 68 |
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| 69 | .endm
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| 70 |
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| 71 |
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| 72 | #if XCHAL_DCACHE_LINE_LOCKABLE
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| 73 |
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| 74 | .macro ___unlock_dcache_all ar at
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| 75 |
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| 76 | __loop_cache_all \ar \at diu XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH
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| 77 |
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| 78 | .endm
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| 79 |
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| 80 | #endif
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| 81 |
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| 82 | #if XCHAL_ICACHE_LINE_LOCKABLE
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| 83 |
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| 84 | .macro ___unlock_icache_all ar at
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| 85 |
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| 86 | __loop_cache_all \ar \at iiu XCHAL_ICACHE_SIZE XCHAL_ICACHE_LINEWIDTH
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| 87 |
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| 88 | .endm
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| 89 | #endif
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| 90 |
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| 91 | .macro ___flush_invalidate_dcache_all ar at
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| 92 |
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| 93 | __loop_cache_all \ar \at diwbi XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH
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| 94 |
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| 95 | .endm
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| 96 |
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| 97 |
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| 98 | .macro ___flush_dcache_all ar at
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| 99 |
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| 100 | __loop_cache_all \ar \at diwb XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH
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| 101 |
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| 102 | .endm
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| 103 |
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| 104 |
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| 105 | .macro ___invalidate_dcache_all ar at
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| 106 |
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| 107 | __loop_cache_all \ar \at dii __stringify(DCACHE_WAY_SIZE) \
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| 108 | XCHAL_DCACHE_LINEWIDTH
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| 109 |
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| 110 | .endm
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| 111 |
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| 112 |
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| 113 | .macro ___invalidate_icache_all ar at
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| 114 |
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| 115 | __loop_cache_all \ar \at iii __stringify(ICACHE_WAY_SIZE) \
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| 116 | XCHAL_ICACHE_LINEWIDTH
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| 117 |
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| 118 | .endm
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| 119 |
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| 120 |
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| 121 |
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| 122 | .macro ___flush_invalidate_dcache_range ar as at
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| 123 |
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| 124 | __loop_cache_range \ar \as \at dhwbi XCHAL_DCACHE_LINEWIDTH
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| 125 |
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| 126 | .endm
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| 127 |
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| 128 |
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| 129 | .macro ___flush_dcache_range ar as at
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| 130 |
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| 131 | __loop_cache_range \ar \as \at dhwb XCHAL_DCACHE_LINEWIDTH
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| 132 |
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| 133 | .endm
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| 134 |
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| 135 |
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| 136 | .macro ___invalidate_dcache_range ar as at
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| 137 |
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| 138 | __loop_cache_range \ar \as \at dhi XCHAL_DCACHE_LINEWIDTH
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| 139 |
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| 140 | .endm
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| 141 |
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| 142 |
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| 143 | .macro ___invalidate_icache_range ar as at
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| 144 |
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| 145 | __loop_cache_range \ar \as \at ihi XCHAL_ICACHE_LINEWIDTH
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| 146 |
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| 147 | .endm
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| 148 |
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| 149 |
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| 150 |
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| 151 | .macro ___flush_invalidate_dcache_page ar as
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| 152 |
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| 153 | __loop_cache_page \ar \as dhwbi XCHAL_DCACHE_LINEWIDTH
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| 154 |
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| 155 | .endm
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| 156 |
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| 157 |
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| 158 | .macro ___flush_dcache_page ar as
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| 159 |
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| 160 | __loop_cache_page \ar \as dhwb XCHAL_DCACHE_LINEWIDTH
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| 161 |
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| 162 | .endm
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| 163 |
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| 164 |
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| 165 | .macro ___invalidate_dcache_page ar as
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| 166 |
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| 167 | __loop_cache_page \ar \as dhi XCHAL_DCACHE_LINEWIDTH
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| 168 |
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| 169 | .endm
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| 170 |
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| 171 |
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| 172 | .macro ___invalidate_icache_page ar as
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| 173 |
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| 174 | __loop_cache_page \ar \as ihi XCHAL_ICACHE_LINEWIDTH
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| 175 |
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| 176 | .endm
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| 177 |
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