| 1 | |
| 2 | * linux/include/asm-xtensa/pgalloc.h
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| 3 | *
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| 4 | * This program is free software; you can redistribute it and/or modify
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| 5 | * it under the terms of the GNU General Public License version 2 as
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| 6 | * published by the Free Software Foundation.
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| 7 | *
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| 8 | * Copyright (C) 2001-2005 Tensilica Inc.
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| 9 |
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| 10 |
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| 11 | #ifndef _XTENSA_PGALLOC_H
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| 12 | #define _XTENSA_PGALLOC_H
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| 13 |
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| 14 | #ifdef __KERNEL__
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| 15 |
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| 16 | #include <linux/threads.h>
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| 17 | #include <linux/highmem.h>
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| 18 | #include <asm/processor.h>
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| 19 | #include <asm/cacheflush.h>
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| 20 |
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| 21 |
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| 22 | |
| 23 | *
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| 24 | * If the cache size for one way is greater than the page size, we have to
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| 25 | * deal with cache aliasing. The cache index is wider than the page size:
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| 26 | *
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| 27 | * |cache |
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| 28 | * |pgnum |page| virtual address
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| 29 | * |xxxxxX|zzzz|
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| 30 | * | | |
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| 31 | * \ / | |
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| 32 | * trans.| |
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| 33 | * / \ | |
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| 34 | * |yyyyyY|zzzz| physical address
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| 35 | *
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| 36 | * When the page number is translated to the physical page address, the lowest
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| 37 | * bit(s) (X) that are also part of the cache index are also translated (Y).
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| 38 | * If this translation changes this bit (X), the cache index is also afected,
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| 39 | * thus resulting in a different cache line than before.
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| 40 | * The kernel does not provide a mechanism to ensure that the page color
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| 41 | * (represented by this bit) remains the same when allocated or when pages
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| 42 | * are remapped. When user pages are mapped into kernel space, the color of
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| 43 | * the page might also change.
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| 44 | *
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| 45 | * We use the address space VMALLOC_END ... VMALLOC_END + DCACHE_WAY_SIZE * 2
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| 46 | * to temporarily map a patch so we can match the color.
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| 47 |
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| 48 |
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| 49 | #if (DCACHE_WAY_SIZE > PAGE_SIZE)
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| 50 | # define PAGE_COLOR_MASK (PAGE_MASK & (DCACHE_WAY_SIZE-1))
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| 51 | # define PAGE_COLOR(a) \
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| 52 | (((unsigned long)(a)&PAGE_COLOR_MASK) >> PAGE_SHIFT)
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| 53 | # define PAGE_COLOR_EQ(a,b) \
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| 54 | ((((unsigned long)(a) ^ (unsigned long)(b)) & PAGE_COLOR_MASK) == 0)
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| 55 | # define PAGE_COLOR_MAP0(v) \
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| 56 | (VMALLOC_END + ((unsigned long)(v) & PAGE_COLOR_MASK))
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| 57 | # define PAGE_COLOR_MAP1(v) \
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| 58 | (VMALLOC_END + ((unsigned long)(v) & PAGE_COLOR_MASK) + DCACHE_WAY_SIZE)
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| 59 | #endif
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| 60 |
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| 61 | |
| 62 | * Allocating and freeing a pmd is trivial: the 1-entry pmd is
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| 63 | * inside the pgd, so has no extra memory associated with it.
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| 64 |
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| 65 |
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| 66 | #define pgd_free(pgd) free_page((unsigned long)(pgd))
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| 67 |
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| 68 | #if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK
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| 69 |
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| 70 | static inline void
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| 71 | pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmdp, pte_t *pte)
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| 72 | {
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| 73 | pmd_val(*(pmdp)) = (unsigned long)(pte);
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| 74 | __asm__ __volatile__ ("memw; dhwb %0, 0; dsync" :: "a" (pmdp));
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| 75 | }
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| 76 |
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| 77 | static inline void
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| 78 | pmd_populate(struct mm_struct *mm, pmd_t *pmdp, struct page *page)
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| 79 | {
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| 80 | pmd_val(*(pmdp)) = (unsigned long)page_to_virt(page);
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| 81 | __asm__ __volatile__ ("memw; dhwb %0, 0; dsync" :: "a" (pmdp));
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| 82 | }
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| 83 |
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| 84 |
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| 85 |
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| 86 | #else
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| 87 |
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| 88 | # define pmd_populate_kernel(mm, pmdp, pte) \
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| 89 | (pmd_val(*(pmdp)) = (unsigned long)(pte))
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| 90 | # define pmd_populate(mm, pmdp, page) \
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| 91 | (pmd_val(*(pmdp)) = (unsigned long)page_to_virt(page))
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| 92 |
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| 93 | #endif
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| 94 |
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| 95 | static inline pgd_t*
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| 96 | pgd_alloc(struct mm_struct *mm)
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| 97 | {
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| 98 | pgd_t *pgd;
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| 99 |
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| 100 | pgd = (pgd_t *)__get_free_pages(GFP_KERNEL|__GFP_ZERO, PGD_ORDER);
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| 101 |
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| 102 | if (likely(pgd != NULL))
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| 103 | __flush_dcache_page((unsigned long)pgd);
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| 104 |
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| 105 | return pgd;
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| 106 | }
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| 107 |
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| 108 | extern pte_t* pte_alloc_one_kernel(struct mm_struct* mm, unsigned long addr);
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| 109 | extern struct page* pte_alloc_one(struct mm_struct* mm, unsigned long addr);
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| 110 |
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| 111 | #define pte_free_kernel(pte) free_page((unsigned long)pte)
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| 112 | #define pte_free(pte) __free_page(pte)
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| 113 |
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| 114 | #endif
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| 115 | #endif
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