| 1 | |
| 2 | *
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| 3 | * It should be possible to use these on really simple architectures,
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| 4 | * but it serves more as a starting point for new ports.
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| 5 | *
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| 6 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
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| 7 | * Written by David Howells ([email protected])
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| 8 | *
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| 9 | * This program is free software; you can redistribute it and/or
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| 10 | * modify it under the terms of the GNU General Public Licence
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| 11 | * as published by the Free Software Foundation; either version
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| 12 | * 2 of the Licence, or (at your option) any later version.
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| 13 |
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| 14 | #ifndef __ASM_GENERIC_SYSTEM_H
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| 15 | #define __ASM_GENERIC_SYSTEM_H
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| 16 |
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| 17 | #ifdef __KERNEL__
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| 18 | #ifndef __ASSEMBLY__
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| 19 |
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| 20 | #include <linux/types.h>
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| 21 | #include <linux/irqflags.h>
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| 22 |
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| 23 | #include <asm/cmpxchg-local.h>
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| 24 | #include <asm/cmpxchg.h>
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| 25 |
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| 26 | struct task_struct;
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| 27 |
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| 28 |
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| 29 | extern struct task_struct *__switch_to(struct task_struct *,
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| 30 | struct task_struct *);
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| 31 | #define switch_to(prev, next, last) \
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| 32 | do { \
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| 33 | ((last) = __switch_to((prev), (next))); \
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| 34 | } while (0)
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| 35 |
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| 36 | #define arch_align_stack(x) (x)
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| 37 |
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| 38 | #define nop() asm volatile ("nop")
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| 39 |
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| 40 | #endif
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| 41 |
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| 42 | |
| 43 | * Force strict CPU ordering.
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| 44 | * And yes, this is required on UP too when we're talking
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| 45 | * to devices.
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| 46 | *
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| 47 | * This implementation only contains a compiler barrier.
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| 48 |
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| 49 |
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| 50 | #define mb() asm volatile ("": : :"memory")
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| 51 | #define rmb() mb()
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| 52 | #define wmb() asm volatile ("": : :"memory")
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| 53 |
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| 54 | #ifdef CONFIG_SMP
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| 55 | #define smp_mb() mb()
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| 56 | #define smp_rmb() rmb()
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| 57 | #define smp_wmb() wmb()
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| 58 | #else
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| 59 | #define smp_mb() barrier()
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| 60 | #define smp_rmb() barrier()
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| 61 | #define smp_wmb() barrier()
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| 62 | #endif
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| 63 |
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| 64 | #define set_mb(var, value) do { var = value; mb(); } while (0)
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| 65 | #define set_wmb(var, value) do { var = value; wmb(); } while (0)
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| 66 |
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| 67 | #define read_barrier_depends() do {} while (0)
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| 68 | #define smp_read_barrier_depends() do {} while (0)
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| 69 |
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| 70 | |
| 71 | * we make sure local_irq_enable() doesn't cause priority inversion
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| 72 |
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| 73 | #ifndef __ASSEMBLY__
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| 74 |
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| 75 | |
| 76 | * if something tries to do an invalid xchg().
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| 77 | extern void __xchg_called_with_bad_pointer(void);
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| 78 |
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| 79 | static inline
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| 80 | unsigned long __xchg(unsigned long x, volatile void *ptr, int size)
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| 81 | {
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| 82 | unsigned long ret, flags;
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| 83 |
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| 84 | switch (size) {
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| 85 | case 1:
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| 86 | #ifdef __xchg_u8
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| 87 | return __xchg_u8(x, ptr);
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| 88 | #else
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| 89 | local_irq_save(flags);
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| 90 | ret = *(volatile u8 *)ptr;
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| 91 | *(volatile u8 *)ptr = x;
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| 92 | local_irq_restore(flags);
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| 93 | return ret;
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| 94 | #endif
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| 95 |
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| 96 | case 2:
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| 97 | #ifdef __xchg_u16
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| 98 | return __xchg_u16(x, ptr);
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| 99 | #else
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| 100 | local_irq_save(flags);
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| 101 | ret = *(volatile u16 *)ptr;
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| 102 | *(volatile u16 *)ptr = x;
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| 103 | local_irq_restore(flags);
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| 104 | return ret;
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| 105 | #endif
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| 106 |
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| 107 | case 4:
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| 108 | #ifdef __xchg_u32
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| 109 | return __xchg_u32(x, ptr);
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| 110 | #else
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| 111 | local_irq_save(flags);
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| 112 | ret = *(volatile u32 *)ptr;
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| 113 | *(volatile u32 *)ptr = x;
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| 114 | local_irq_restore(flags);
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| 115 | return ret;
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| 116 | #endif
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| 117 |
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| 118 | #ifdef CONFIG_64BIT
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| 119 | case 8:
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| 120 | #ifdef __xchg_u64
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| 121 | return __xchg_u64(x, ptr);
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| 122 | #else
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| 123 | local_irq_save(flags);
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| 124 | ret = *(volatile u64 *)ptr;
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| 125 | *(volatile u64 *)ptr = x;
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| 126 | local_irq_restore(flags);
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| 127 | return ret;
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| 128 | #endif
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| 129 | #endif
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| 130 |
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| 131 | default:
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| 132 | __xchg_called_with_bad_pointer();
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| 133 | return x;
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| 134 | }
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| 135 | }
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| 136 |
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| 137 | #define xchg(ptr, x) \
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| 138 | ((__typeof__(*(ptr))) __xchg((unsigned long)(x), (ptr), sizeof(*(ptr))))
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| 139 |
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| 140 | #endif
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| 141 |
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| 142 | #endif
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| 143 | #endif
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