| 1 | |
| 2 | * Generic implementation of 64-bit atomics using spinlocks,
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| 3 | * useful on processors that don't have 64-bit atomic instructions.
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| 4 | *
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| 5 | * Copyright © 2009 Paul Mackerras, IBM Corp. <[email protected]>
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| 6 | *
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| 7 | * This program is free software; you can redistribute it and/or
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| 8 | * modify it under the terms of the GNU General Public License
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| 9 | * as published by the Free Software Foundation; either version
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| 10 | * 2 of the License, or (at your option) any later version.
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| 11 |
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| 12 | #include <linux/types.h>
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| 13 | #include <linux/cache.h>
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| 14 | #include <linux/spinlock.h>
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| 15 | #include <linux/init.h>
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| 16 | #include <linux/export.h>
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| 17 | #include <linux/atomic.h>
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| 18 |
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| 19 | |
| 20 | * We use a hashed array of spinlocks to provide exclusive access
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| 21 | * to each atomic64_t variable. Since this is expected to used on
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| 22 | * systems with small numbers of CPUs (<= 4 or so), we use a
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| 23 | * relatively small array of 16 spinlocks to avoid wasting too much
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| 24 | * memory on the spinlock array.
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| 25 |
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| 26 | #define NR_LOCKS 16
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| 27 |
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| 28 | |
| 29 | * Ensure each lock is in a separate cacheline.
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| 30 |
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| 31 | static union {
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| 32 | raw_spinlock_t lock;
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| 33 | char pad[L1_CACHE_BYTES];
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| 34 | } atomic64_lock[NR_LOCKS] __cacheline_aligned_in_smp = {
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| 35 | [0 ... (NR_LOCKS - 1)] = {
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| 36 | .lock = __RAW_SPIN_LOCK_UNLOCKED(atomic64_lock.lock),
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| 37 | },
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| 38 | };
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| 39 |
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| 40 | static inline raw_spinlock_t *lock_addr(const atomic64_t *v)
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| 41 | {
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| 42 | unsigned long addr = (unsigned long) v;
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| 43 |
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| 44 | addr >>= L1_CACHE_SHIFT;
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| 45 | addr ^= (addr >> 8) ^ (addr >> 16);
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| 46 | return &atomic64_lock[addr & (NR_LOCKS - 1)].lock;
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| 47 | }
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| 48 |
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| 49 | long long atomic64_read(const atomic64_t *v)
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| 50 | {
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| 51 | unsigned long flags;
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| 52 | raw_spinlock_t *lock = lock_addr(v);
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| 53 | long long val;
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| 54 |
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| 55 | raw_spin_lock_irqsave(lock, flags);
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| 56 | val = v->counter;
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| 57 | raw_spin_unlock_irqrestore(lock, flags);
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| 58 | return val;
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| 59 | }
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| 60 | EXPORT_SYMBOL(atomic64_read);
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| 61 |
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| 62 | void atomic64_set(atomic64_t *v, long long i)
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| 63 | {
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| 64 | unsigned long flags;
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| 65 | raw_spinlock_t *lock = lock_addr(v);
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| 66 |
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| 67 | raw_spin_lock_irqsave(lock, flags);
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| 68 | v->counter = i;
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| 69 | raw_spin_unlock_irqrestore(lock, flags);
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| 70 | }
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| 71 | EXPORT_SYMBOL(atomic64_set);
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| 72 |
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| 73 | void atomic64_add(long long a, atomic64_t *v)
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| 74 | {
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| 75 | unsigned long flags;
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| 76 | raw_spinlock_t *lock = lock_addr(v);
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| 77 |
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| 78 | raw_spin_lock_irqsave(lock, flags);
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| 79 | v->counter += a;
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| 80 | raw_spin_unlock_irqrestore(lock, flags);
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| 81 | }
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| 82 | EXPORT_SYMBOL(atomic64_add);
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| 83 |
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| 84 | long long atomic64_add_return(long long a, atomic64_t *v)
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| 85 | {
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| 86 | unsigned long flags;
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| 87 | raw_spinlock_t *lock = lock_addr(v);
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| 88 | long long val;
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| 89 |
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| 90 | raw_spin_lock_irqsave(lock, flags);
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| 91 | val = v->counter += a;
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| 92 | raw_spin_unlock_irqrestore(lock, flags);
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| 93 | return val;
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| 94 | }
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| 95 | EXPORT_SYMBOL(atomic64_add_return);
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| 96 |
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| 97 | void atomic64_sub(long long a, atomic64_t *v)
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| 98 | {
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| 99 | unsigned long flags;
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| 100 | raw_spinlock_t *lock = lock_addr(v);
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| 101 |
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| 102 | raw_spin_lock_irqsave(lock, flags);
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| 103 | v->counter -= a;
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| 104 | raw_spin_unlock_irqrestore(lock, flags);
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| 105 | }
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| 106 | EXPORT_SYMBOL(atomic64_sub);
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| 107 |
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| 108 | long long atomic64_sub_return(long long a, atomic64_t *v)
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| 109 | {
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| 110 | unsigned long flags;
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| 111 | raw_spinlock_t *lock = lock_addr(v);
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| 112 | long long val;
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| 113 |
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| 114 | raw_spin_lock_irqsave(lock, flags);
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| 115 | val = v->counter -= a;
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| 116 | raw_spin_unlock_irqrestore(lock, flags);
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| 117 | return val;
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| 118 | }
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| 119 | EXPORT_SYMBOL(atomic64_sub_return);
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| 120 |
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| 121 | long long atomic64_dec_if_positive(atomic64_t *v)
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| 122 | {
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| 123 | unsigned long flags;
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| 124 | raw_spinlock_t *lock = lock_addr(v);
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| 125 | long long val;
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| 126 |
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| 127 | raw_spin_lock_irqsave(lock, flags);
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| 128 | val = v->counter - 1;
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| 129 | if (val >= 0)
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| 130 | v->counter = val;
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| 131 | raw_spin_unlock_irqrestore(lock, flags);
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| 132 | return val;
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| 133 | }
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| 134 | EXPORT_SYMBOL(atomic64_dec_if_positive);
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| 135 |
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| 136 | long long atomic64_cmpxchg(atomic64_t *v, long long o, long long n)
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| 137 | {
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| 138 | unsigned long flags;
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| 139 | raw_spinlock_t *lock = lock_addr(v);
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| 140 | long long val;
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| 141 |
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| 142 | raw_spin_lock_irqsave(lock, flags);
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| 143 | val = v->counter;
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| 144 | if (val == o)
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| 145 | v->counter = n;
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| 146 | raw_spin_unlock_irqrestore(lock, flags);
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| 147 | return val;
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| 148 | }
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| 149 | EXPORT_SYMBOL(atomic64_cmpxchg);
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| 150 |
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| 151 | long long atomic64_xchg(atomic64_t *v, long long new)
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| 152 | {
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| 153 | unsigned long flags;
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| 154 | raw_spinlock_t *lock = lock_addr(v);
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| 155 | long long val;
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| 156 |
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| 157 | raw_spin_lock_irqsave(lock, flags);
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| 158 | val = v->counter;
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| 159 | v->counter = new;
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| 160 | raw_spin_unlock_irqrestore(lock, flags);
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| 161 | return val;
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| 162 | }
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| 163 | EXPORT_SYMBOL(atomic64_xchg);
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| 164 |
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| 165 | int atomic64_add_unless(atomic64_t *v, long long a, long long u)
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| 166 | {
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| 167 | unsigned long flags;
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| 168 | raw_spinlock_t *lock = lock_addr(v);
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| 169 | int ret = 0;
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| 170 |
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| 171 | raw_spin_lock_irqsave(lock, flags);
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| 172 | if (v->counter != u) {
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| 173 | v->counter += a;
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| 174 | ret = 1;
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| 175 | }
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| 176 | raw_spin_unlock_irqrestore(lock, flags);
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| 177 | return ret;
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| 178 | }
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| 179 | EXPORT_SYMBOL(atomic64_add_unless);
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