| 1 | |
| 2 | * Generic EDAC defs
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| 3 | *
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| 4 | * Author: Dave Jiang <[email protected]>
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| 5 | *
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| 6 | * 2006-2008 (c) MontaVista Software, Inc. This file is licensed under
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| 7 | * the terms of the GNU General Public License version 2. This program
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| 8 | * is licensed "as is" without any warranty of any kind, whether express
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| 9 | * or implied.
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| 10 | *
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| 11 |
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| 12 | #ifndef _LINUX_EDAC_H_
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| 13 | #define _LINUX_EDAC_H_
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| 14 |
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| 15 | #include <linux/atomic.h>
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| 16 | #include <linux/device.h>
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| 17 | #include <linux/completion.h>
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| 18 | #include <linux/workqueue.h>
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| 19 | #include <linux/debugfs.h>
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| 20 |
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| 21 | struct device;
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| 22 |
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| 23 | #define EDAC_OPSTATE_INVAL -1
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| 24 | #define EDAC_OPSTATE_POLL 0
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| 25 | #define EDAC_OPSTATE_NMI 1
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| 26 | #define EDAC_OPSTATE_INT 2
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| 27 |
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| 28 | extern int edac_op_state;
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| 29 | extern int edac_err_assert;
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| 30 | extern atomic_t edac_handlers;
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| 31 | extern struct bus_type edac_subsys;
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| 32 |
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| 33 | extern int edac_handler_set(void);
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| 34 | extern void edac_atomic_assert_error(void);
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| 35 | extern struct bus_type *edac_get_sysfs_subsys(void);
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| 36 | extern void edac_put_sysfs_subsys(void);
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| 37 |
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| 38 | enum {
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| 39 | EDAC_REPORTING_ENABLED,
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| 40 | EDAC_REPORTING_DISABLED,
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| 41 | EDAC_REPORTING_FORCE
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| 42 | };
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| 43 |
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| 44 | extern int edac_report_status;
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| 45 | #ifdef CONFIG_EDAC
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| 46 | static inline int get_edac_report_status(void)
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| 47 | {
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| 48 | return edac_report_status;
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| 49 | }
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| 50 |
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| 51 | static inline void set_edac_report_status(int new)
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| 52 | {
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| 53 | edac_report_status = new;
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| 54 | }
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| 55 | #else
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| 56 | static inline int get_edac_report_status(void)
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| 57 | {
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| 58 | return EDAC_REPORTING_DISABLED;
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| 59 | }
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| 60 |
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| 61 | static inline void set_edac_report_status(int new)
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| 62 | {
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| 63 | }
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| 64 | #endif
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| 65 |
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| 66 | static inline void opstate_init(void)
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| 67 | {
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| 68 | switch (edac_op_state) {
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| 69 | case EDAC_OPSTATE_POLL:
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| 70 | case EDAC_OPSTATE_NMI:
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| 71 | break;
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| 72 | default:
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| 73 | edac_op_state = EDAC_OPSTATE_POLL;
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| 74 | }
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| 75 | return;
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| 76 | }
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| 77 |
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| 78 |
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| 79 | #define EDAC_MC_LABEL_LEN 31
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| 80 |
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| 81 |
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| 82 | #define LOCATION_SIZE 256
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| 83 |
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| 84 |
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| 85 | #define EDAC_MAX_LABELS 8
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| 86 |
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| 87 |
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| 88 | #define OTHER_LABEL " or "
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| 89 |
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| 90 | |
| 91 | * enum dev_type - describe the type of memory DRAM chips used at the stick
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| 92 | * @DEV_UNKNOWN: Can't be determined, or MC doesn't support detect it
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| 93 | * @DEV_X1: 1 bit for data
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| 94 | * @DEV_X2: 2 bits for data
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| 95 | * @DEV_X4: 4 bits for data
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| 96 | * @DEV_X8: 8 bits for data
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| 97 | * @DEV_X16: 16 bits for data
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| 98 | * @DEV_X32: 32 bits for data
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| 99 | * @DEV_X64: 64 bits for data
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| 100 | *
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| 101 | * Typical values are x4 and x8.
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| 102 |
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| 103 | enum dev_type {
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| 104 | DEV_UNKNOWN = 0,
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| 105 | DEV_X1,
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| 106 | DEV_X2,
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| 107 | DEV_X4,
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| 108 | DEV_X8,
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| 109 | DEV_X16,
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| 110 | DEV_X32,
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| 111 | DEV_X64
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| 112 | };
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| 113 |
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| 114 | #define DEV_FLAG_UNKNOWN BIT(DEV_UNKNOWN)
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| 115 | #define DEV_FLAG_X1 BIT(DEV_X1)
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| 116 | #define DEV_FLAG_X2 BIT(DEV_X2)
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| 117 | #define DEV_FLAG_X4 BIT(DEV_X4)
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| 118 | #define DEV_FLAG_X8 BIT(DEV_X8)
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| 119 | #define DEV_FLAG_X16 BIT(DEV_X16)
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| 120 | #define DEV_FLAG_X32 BIT(DEV_X32)
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| 121 | #define DEV_FLAG_X64 BIT(DEV_X64)
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| 122 |
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| 123 | |
| 124 | * enum hw_event_mc_err_type - type of the detected error
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| 125 | *
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| 126 | * @HW_EVENT_ERR_CORRECTED: Corrected Error - Indicates that an ECC
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| 127 | * corrected error was detected
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| 128 | * @HW_EVENT_ERR_UNCORRECTED: Uncorrected Error - Indicates an error that
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| 129 | * can't be corrected by ECC, but it is not
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| 130 | * fatal (maybe it is on an unused memory area,
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| 131 | * or the memory controller could recover from
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| 132 | * it for example, by re-trying the operation).
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| 133 | * @HW_EVENT_ERR_FATAL: Fatal Error - Uncorrected error that could not
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| 134 | * be recovered.
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| 135 |
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| 136 | enum hw_event_mc_err_type {
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| 137 | HW_EVENT_ERR_CORRECTED,
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| 138 | HW_EVENT_ERR_UNCORRECTED,
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| 139 | HW_EVENT_ERR_FATAL,
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| 140 | HW_EVENT_ERR_INFO,
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| 141 | };
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| 142 |
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| 143 | static inline char *mc_event_error_type(const unsigned int err_type)
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| 144 | {
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| 145 | switch (err_type) {
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| 146 | case HW_EVENT_ERR_CORRECTED:
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| 147 | return "Corrected";
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| 148 | case HW_EVENT_ERR_UNCORRECTED:
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| 149 | return "Uncorrected";
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| 150 | case HW_EVENT_ERR_FATAL:
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| 151 | return "Fatal";
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| 152 | default:
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| 153 | case HW_EVENT_ERR_INFO:
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| 154 | return "Info";
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| 155 | }
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| 156 | }
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| 157 |
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| 158 | |
| 159 | * enum mem_type - memory types. For a more detailed reference, please see
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| 160 | * http://en.wikipedia.org/wiki/DRAM
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| 161 | *
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| 162 | * @MEM_EMPTY Empty csrow
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| 163 | * @MEM_RESERVED: Reserved csrow type
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| 164 | * @MEM_UNKNOWN: Unknown csrow type
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| 165 | * @MEM_FPM: FPM - Fast Page Mode, used on systems up to 1995.
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| 166 | * @MEM_EDO: EDO - Extended data out, used on systems up to 1998.
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| 167 | * @MEM_BEDO: BEDO - Burst Extended data out, an EDO variant.
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| 168 | * @MEM_SDR: SDR - Single data rate SDRAM
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| 169 | * http://en.wikipedia.org/wiki/Synchronous_dynamic_random-access_memory
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| 170 | * They use 3 pins for chip select: Pins 0 and 2 are
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| 171 | * for rank 0; pins 1 and 3 are for rank 1, if the memory
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| 172 | * is dual-rank.
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| 173 | * @MEM_RDR: Registered SDR SDRAM
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| 174 | * @MEM_DDR: Double data rate SDRAM
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| 175 | * http://en.wikipedia.org/wiki/DDR_SDRAM
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| 176 | * @MEM_RDDR: Registered Double data rate SDRAM
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| 177 | * This is a variant of the DDR memories.
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| 178 | * A registered memory has a buffer inside it, hiding
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| 179 | * part of the memory details to the memory controller.
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| 180 | * @MEM_RMBS: Rambus DRAM, used on a few Pentium III/IV controllers.
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| 181 | * @MEM_DDR2: DDR2 RAM, as described at JEDEC JESD79-2F.
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| 182 | * Those memories are labed as "PC2-" instead of "PC" to
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| 183 | * differenciate from DDR.
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| 184 | * @MEM_FB_DDR2: Fully-Buffered DDR2, as described at JEDEC Std No. 205
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| 185 | * and JESD206.
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| 186 | * Those memories are accessed per DIMM slot, and not by
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| 187 | * a chip select signal.
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| 188 | * @MEM_RDDR2: Registered DDR2 RAM
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| 189 | * This is a variant of the DDR2 memories.
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| 190 | * @MEM_XDR: Rambus XDR
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| 191 | * It is an evolution of the original RAMBUS memories,
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| 192 | * created to compete with DDR2. Weren't used on any
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| 193 | * x86 arch, but cell_edac PPC memory controller uses it.
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| 194 | * @MEM_DDR3: DDR3 RAM
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| 195 | * @MEM_RDDR3: Registered DDR3 RAM
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| 196 | * This is a variant of the DDR3 memories.
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| 197 |
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| 198 | enum mem_type {
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| 199 | MEM_EMPTY = 0,
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| 200 | MEM_RESERVED,
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| 201 | MEM_UNKNOWN,
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| 202 | MEM_FPM,
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| 203 | MEM_EDO,
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| 204 | MEM_BEDO,
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| 205 | MEM_SDR,
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| 206 | MEM_RDR,
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| 207 | MEM_DDR,
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| 208 | MEM_RDDR,
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| 209 | MEM_RMBS,
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| 210 | MEM_DDR2,
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| 211 | MEM_FB_DDR2,
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| 212 | MEM_RDDR2,
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| 213 | MEM_XDR,
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| 214 | MEM_DDR3,
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| 215 | MEM_RDDR3,
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| 216 | };
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| 217 |
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| 218 | #define MEM_FLAG_EMPTY BIT(MEM_EMPTY)
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| 219 | #define MEM_FLAG_RESERVED BIT(MEM_RESERVED)
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| 220 | #define MEM_FLAG_UNKNOWN BIT(MEM_UNKNOWN)
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| 221 | #define MEM_FLAG_FPM BIT(MEM_FPM)
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| 222 | #define MEM_FLAG_EDO BIT(MEM_EDO)
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| 223 | #define MEM_FLAG_BEDO BIT(MEM_BEDO)
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| 224 | #define MEM_FLAG_SDR BIT(MEM_SDR)
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| 225 | #define MEM_FLAG_RDR BIT(MEM_RDR)
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| 226 | #define MEM_FLAG_DDR BIT(MEM_DDR)
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| 227 | #define MEM_FLAG_RDDR BIT(MEM_RDDR)
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| 228 | #define MEM_FLAG_RMBS BIT(MEM_RMBS)
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| 229 | #define MEM_FLAG_DDR2 BIT(MEM_DDR2)
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| 230 | #define MEM_FLAG_FB_DDR2 BIT(MEM_FB_DDR2)
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| 231 | #define MEM_FLAG_RDDR2 BIT(MEM_RDDR2)
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| 232 | #define MEM_FLAG_XDR BIT(MEM_XDR)
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| 233 | #define MEM_FLAG_DDR3 BIT(MEM_DDR3)
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| 234 | #define MEM_FLAG_RDDR3 BIT(MEM_RDDR3)
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| 235 |
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| 236 | |
| 237 | * enum edac-type - Error Detection and Correction capabilities and mode
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| 238 | * @EDAC_UNKNOWN: Unknown if ECC is available
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| 239 | * @EDAC_NONE: Doesn't support ECC
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| 240 | * @EDAC_RESERVED: Reserved ECC type
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| 241 | * @EDAC_PARITY: Detects parity errors
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| 242 | * @EDAC_EC: Error Checking - no correction
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| 243 | * @EDAC_SECDED: Single bit error correction, Double detection
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| 244 | * @EDAC_S2ECD2ED: Chipkill x2 devices - do these exist?
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| 245 | * @EDAC_S4ECD4ED: Chipkill x4 devices
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| 246 | * @EDAC_S8ECD8ED: Chipkill x8 devices
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| 247 | * @EDAC_S16ECD16ED: Chipkill x16 devices
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| 248 |
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| 249 | enum edac_type {
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| 250 | EDAC_UNKNOWN = 0,
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| 251 | EDAC_NONE,
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| 252 | EDAC_RESERVED,
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| 253 | EDAC_PARITY,
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| 254 | EDAC_EC,
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| 255 | EDAC_SECDED,
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| 256 | EDAC_S2ECD2ED,
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| 257 | EDAC_S4ECD4ED,
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| 258 | EDAC_S8ECD8ED,
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| 259 | EDAC_S16ECD16ED,
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| 260 | };
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| 261 |
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| 262 | #define EDAC_FLAG_UNKNOWN BIT(EDAC_UNKNOWN)
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| 263 | #define EDAC_FLAG_NONE BIT(EDAC_NONE)
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| 264 | #define EDAC_FLAG_PARITY BIT(EDAC_PARITY)
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| 265 | #define EDAC_FLAG_EC BIT(EDAC_EC)
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| 266 | #define EDAC_FLAG_SECDED BIT(EDAC_SECDED)
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| 267 | #define EDAC_FLAG_S2ECD2ED BIT(EDAC_S2ECD2ED)
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| 268 | #define EDAC_FLAG_S4ECD4ED BIT(EDAC_S4ECD4ED)
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| 269 | #define EDAC_FLAG_S8ECD8ED BIT(EDAC_S8ECD8ED)
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| 270 | #define EDAC_FLAG_S16ECD16ED BIT(EDAC_S16ECD16ED)
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| 271 |
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| 272 | |
| 273 | * enum scrub_type - scrubbing capabilities
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| 274 | * @SCRUB_UNKNOWN Unknown if scrubber is available
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| 275 | * @SCRUB_NONE: No scrubber
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| 276 | * @SCRUB_SW_PROG: SW progressive (sequential) scrubbing
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| 277 | * @SCRUB_SW_SRC: Software scrub only errors
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| 278 | * @SCRUB_SW_PROG_SRC: Progressive software scrub from an error
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| 279 | * @SCRUB_SW_TUNABLE: Software scrub frequency is tunable
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| 280 | * @SCRUB_HW_PROG: HW progressive (sequential) scrubbing
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| 281 | * @SCRUB_HW_SRC: Hardware scrub only errors
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| 282 | * @SCRUB_HW_PROG_SRC: Progressive hardware scrub from an error
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| 283 | * SCRUB_HW_TUNABLE: Hardware scrub frequency is tunable
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| 284 |
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| 285 | enum scrub_type {
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| 286 | SCRUB_UNKNOWN = 0,
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| 287 | SCRUB_NONE,
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| 288 | SCRUB_SW_PROG,
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| 289 | SCRUB_SW_SRC,
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| 290 | SCRUB_SW_PROG_SRC,
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| 291 | SCRUB_SW_TUNABLE,
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| 292 | SCRUB_HW_PROG,
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| 293 | SCRUB_HW_SRC,
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| 294 | SCRUB_HW_PROG_SRC,
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| 295 | SCRUB_HW_TUNABLE
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| 296 | };
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| 297 |
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| 298 | #define SCRUB_FLAG_SW_PROG BIT(SCRUB_SW_PROG)
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| 299 | #define SCRUB_FLAG_SW_SRC BIT(SCRUB_SW_SRC)
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| 300 | #define SCRUB_FLAG_SW_PROG_SRC BIT(SCRUB_SW_PROG_SRC)
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| 301 | #define SCRUB_FLAG_SW_TUN BIT(SCRUB_SW_SCRUB_TUNABLE)
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| 302 | #define SCRUB_FLAG_HW_PROG BIT(SCRUB_HW_PROG)
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| 303 | #define SCRUB_FLAG_HW_SRC BIT(SCRUB_HW_SRC)
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| 304 | #define SCRUB_FLAG_HW_PROG_SRC BIT(SCRUB_HW_PROG_SRC)
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| 305 | #define SCRUB_FLAG_HW_TUN BIT(SCRUB_HW_TUNABLE)
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| 306 |
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| 307 |
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| 308 |
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| 309 |
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| 310 | #define OP_ALLOC 0x100
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| 311 | #define OP_RUNNING_POLL 0x201
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| 312 | #define OP_RUNNING_INTERRUPT 0x202
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| 313 | #define OP_RUNNING_POLL_INTR 0x203
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| 314 | #define OP_OFFLINE 0x300
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| 315 |
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| 316 | |
| 317 | * Concepts used at the EDAC subsystem
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| 318 | *
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| 319 | * There are several things to be aware of that aren't at all obvious:
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| 320 | *
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| 321 | * SOCKETS, SOCKET SETS, BANKS, ROWS, CHIP-SELECT ROWS, CHANNELS, etc..
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| 322 | *
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| 323 | * These are some of the many terms that are thrown about that don't always
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| 324 | * mean what people think they mean (Inconceivable!). In the interest of
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| 325 | * creating a common ground for discussion, terms and their definitions
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| 326 | * will be established.
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| 327 | *
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| 328 | * Memory devices: The individual DRAM chips on a memory stick. These
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| 329 | * devices commonly output 4 and 8 bits each (x4, x8).
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| 330 | * Grouping several of these in parallel provides the
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| 331 | * number of bits that the memory controller expects:
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| 332 | * typically 72 bits, in order to provide 64 bits +
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| 333 | * 8 bits of ECC data.
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| 334 | *
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| 335 | * Memory Stick: A printed circuit board that aggregates multiple
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| 336 | * memory devices in parallel. In general, this is the
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| 337 | * Field Replaceable Unit (FRU) which gets replaced, in
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| 338 | * the case of excessive errors. Most often it is also
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| 339 | * called DIMM (Dual Inline Memory Module).
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| 340 | *
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| 341 | * Memory Socket: A physical connector on the motherboard that accepts
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| 342 | * a single memory stick. Also called as "slot" on several
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| 343 | * datasheets.
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| 344 | *
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| 345 | * Channel: A memory controller channel, responsible to communicate
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| 346 | * with a group of DIMMs. Each channel has its own
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| 347 | * independent control (command) and data bus, and can
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| 348 | * be used independently or grouped with other channels.
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| 349 | *
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| 350 | * Branch: It is typically the highest hierarchy on a
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| 351 | * Fully-Buffered DIMM memory controller.
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| 352 | * Typically, it contains two channels.
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| 353 | * Two channels at the same branch can be used in single
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| 354 | * mode or in lockstep mode.
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| 355 | * When lockstep is enabled, the cacheline is doubled,
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| 356 | * but it generally brings some performance penalty.
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| 357 | * Also, it is generally not possible to point to just one
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| 358 | * memory stick when an error occurs, as the error
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| 359 | * correction code is calculated using two DIMMs instead
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| 360 | * of one. Due to that, it is capable of correcting more
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| 361 | * errors than on single mode.
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| 362 | *
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| 363 | * Single-channel: The data accessed by the memory controller is contained
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| 364 | * into one dimm only. E. g. if the data is 64 bits-wide,
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| 365 | * the data flows to the CPU using one 64 bits parallel
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| 366 | * access.
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| 367 | * Typically used with SDR, DDR, DDR2 and DDR3 memories.
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| 368 | * FB-DIMM and RAMBUS use a different concept for channel,
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| 369 | * so this concept doesn't apply there.
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| 370 | *
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| 371 | * Double-channel: The data size accessed by the memory controller is
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| 372 | * interlaced into two dimms, accessed at the same time.
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| 373 | * E. g. if the DIMM is 64 bits-wide (72 bits with ECC),
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| 374 | * the data flows to the CPU using a 128 bits parallel
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| 375 | * access.
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| 376 | *
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| 377 | * Chip-select row: This is the name of the DRAM signal used to select the
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| 378 | * DRAM ranks to be accessed. Common chip-select rows for
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| 379 | * single channel are 64 bits, for dual channel 128 bits.
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| 380 | * It may not be visible by the memory controller, as some
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| 381 | * DIMM types have a memory buffer that can hide direct
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| 382 | * access to it from the Memory Controller.
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| 383 | *
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| 384 | * Single-Ranked stick: A Single-ranked stick has 1 chip-select row of memory.
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| 385 | * Motherboards commonly drive two chip-select pins to
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| 386 | * a memory stick. A single-ranked stick, will occupy
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| 387 | * only one of those rows. The other will be unused.
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| 388 | *
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| 389 | * Double-Ranked stick: A double-ranked stick has two chip-select rows which
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| 390 | * access different sets of memory devices. The two
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| 391 | * rows cannot be accessed concurrently.
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| 392 | *
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| 393 | * Double-sided stick: DEPRECATED TERM, see Double-Ranked stick.
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| 394 | * A double-sided stick has two chip-select rows which
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| 395 | * access different sets of memory devices. The two
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| 396 | * rows cannot be accessed concurrently. "Double-sided"
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| 397 | * is irrespective of the memory devices being mounted
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| 398 | * on both sides of the memory stick.
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| 399 | *
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| 400 | * Socket set: All of the memory sticks that are required for
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| 401 | * a single memory access or all of the memory sticks
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| 402 | * spanned by a chip-select row. A single socket set
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| 403 | * has two chip-select rows and if double-sided sticks
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| 404 | * are used these will occupy those chip-select rows.
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| 405 | *
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| 406 | * Bank: This term is avoided because it is unclear when
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| 407 | * needing to distinguish between chip-select rows and
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| 408 | * socket sets.
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| 409 | *
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| 410 | * Controller pages:
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| 411 | *
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| 412 | * Physical pages:
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| 413 | *
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| 414 | * Virtual pages:
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| 415 | *
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| 416 | *
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| 417 | * STRUCTURE ORGANIZATION AND CHOICES
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| 418 | *
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| 419 | *
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| 420 | *
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| 421 | * PS - I enjoyed writing all that about as much as you enjoyed reading it.
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| 422 |
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| 423 |
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| 424 | |
| 425 | * enum edac_mc_layer - memory controller hierarchy layer
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| 426 | *
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| 427 | * @EDAC_MC_LAYER_BRANCH: memory layer is named "branch"
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| 428 | * @EDAC_MC_LAYER_CHANNEL: memory layer is named "channel"
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| 429 | * @EDAC_MC_LAYER_SLOT: memory layer is named "slot"
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| 430 | * @EDAC_MC_LAYER_CHIP_SELECT: memory layer is named "chip select"
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| 431 | * @EDAC_MC_LAYER_ALL_MEM: memory layout is unknown. All memory is mapped
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| 432 | * as a single memory area. This is used when
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| 433 | * retrieving errors from a firmware driven driver.
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| 434 | *
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| 435 | * This enum is used by the drivers to tell edac_mc_sysfs what name should
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| 436 | * be used when describing a memory stick location.
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| 437 |
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| 438 | enum edac_mc_layer_type {
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| 439 | EDAC_MC_LAYER_BRANCH,
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| 440 | EDAC_MC_LAYER_CHANNEL,
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| 441 | EDAC_MC_LAYER_SLOT,
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| 442 | EDAC_MC_LAYER_CHIP_SELECT,
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| 443 | EDAC_MC_LAYER_ALL_MEM,
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| 444 | };
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| 445 |
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| 446 | |
| 447 | * struct edac_mc_layer - describes the memory controller hierarchy
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| 448 | * @layer: layer type
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| 449 | * @size: number of components per layer. For example,
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| 450 | * if the channel layer has two channels, size = 2
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| 451 | * @is_virt_csrow: This layer is part of the "csrow" when old API
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| 452 | * compatibility mode is enabled. Otherwise, it is
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| 453 | * a channel
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| 454 |
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| 455 | struct edac_mc_layer {
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| 456 | enum edac_mc_layer_type type;
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| 457 | unsigned size;
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| 458 | bool is_virt_csrow;
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| 459 | };
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| 460 |
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| 461 | |
| 462 | * Maximum number of layers used by the memory controller to uniquely
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| 463 | * identify a single memory stick.
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| 464 | * NOTE: Changing this constant requires not only to change the constant
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| 465 | * below, but also to change the existing code at the core, as there are
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| 466 | * some code there that are optimized for 3 layers.
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| 467 |
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| 468 | #define EDAC_MAX_LAYERS 3
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| 469 |
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| 470 | |
| 471 | * EDAC_DIMM_OFF - Macro responsible to get a pointer offset inside a pointer array
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| 472 | * for the element given by [layer0,layer1,layer2] position
|
| 473 | *
|
| 474 | * @layers: a struct edac_mc_layer array, describing how many elements
|
| 475 | * were allocated for each layer
|
| 476 | * @n_layers: Number of layers at the @layers array
|
| 477 | * @layer0: layer0 position
|
| 478 | * @layer1: layer1 position. Unused if n_layers < 2
|
| 479 | * @layer2: layer2 position. Unused if n_layers < 3
|
| 480 | *
|
| 481 | * For 1 layer, this macro returns &var[layer0] - &var
|
| 482 | * For 2 layers, this macro is similar to allocate a bi-dimensional array
|
| 483 | * and to return "&var[layer0][layer1] - &var"
|
| 484 | * For 3 layers, this macro is similar to allocate a tri-dimensional array
|
| 485 | * and to return "&var[layer0][layer1][layer2] - &var"
|
| 486 | *
|
| 487 | * A loop could be used here to make it more generic, but, as we only have
|
| 488 | * 3 layers, this is a little faster.
|
| 489 | * By design, layers can never be 0 or more than 3. If that ever happens,
|
| 490 | * a NULL is returned, causing an OOPS during the memory allocation routine,
|
| 491 | * with would point to the developer that he's doing something wrong.
|
| 492 |
|
| 493 | #define EDAC_DIMM_OFF(layers, nlayers, layer0, layer1, layer2) ({ \
|
| 494 | int __i; \
|
| 495 | if ((nlayers) == 1) \
|
| 496 | __i = layer0; \
|
| 497 | else if ((nlayers) == 2) \
|
| 498 | __i = (layer1) + ((layers[1]).size * (layer0)); \
|
| 499 | else if ((nlayers) == 3) \
|
| 500 | __i = (layer2) + ((layers[2]).size * ((layer1) + \
|
| 501 | ((layers[1]).size * (layer0)))); \
|
| 502 | else \
|
| 503 | __i = -EINVAL; \
|
| 504 | __i; \
|
| 505 | })
|
| 506 |
|
| 507 | |
| 508 | * EDAC_DIMM_PTR - Macro responsible to get a pointer inside a pointer array
|
| 509 | * for the element given by [layer0,layer1,layer2] position
|
| 510 | *
|
| 511 | * @layers: a struct edac_mc_layer array, describing how many elements
|
| 512 | * were allocated for each layer
|
| 513 | * @var: name of the var where we want to get the pointer
|
| 514 | * (like mci->dimms)
|
| 515 | * @n_layers: Number of layers at the @layers array
|
| 516 | * @layer0: layer0 position
|
| 517 | * @layer1: layer1 position. Unused if n_layers < 2
|
| 518 | * @layer2: layer2 position. Unused if n_layers < 3
|
| 519 | *
|
| 520 | * For 1 layer, this macro returns &var[layer0]
|
| 521 | * For 2 layers, this macro is similar to allocate a bi-dimensional array
|
| 522 | * and to return "&var[layer0][layer1]"
|
| 523 | * For 3 layers, this macro is similar to allocate a tri-dimensional array
|
| 524 | * and to return "&var[layer0][layer1][layer2]"
|
| 525 |
|
| 526 | #define EDAC_DIMM_PTR(layers, var, nlayers, layer0, layer1, layer2) ({ \
|
| 527 | typeof(*var) __p; \
|
| 528 | int ___i = EDAC_DIMM_OFF(layers, nlayers, layer0, layer1, layer2); \
|
| 529 | if (___i < 0) \
|
| 530 | __p = NULL; \
|
| 531 | else \
|
| 532 | __p = (var)[___i]; \
|
| 533 | __p; \
|
| 534 | })
|
| 535 |
|
| 536 | struct dimm_info {
|
| 537 | struct device dev;
|
| 538 |
|
| 539 | char label[EDAC_MC_LABEL_LEN + 1];
|
| 540 |
|
| 541 |
|
| 542 | unsigned location[EDAC_MAX_LAYERS];
|
| 543 |
|
| 544 | struct mem_ctl_info *mci;
|
| 545 |
|
| 546 | u32 grain;
|
| 547 | enum dev_type dtype;
|
| 548 | enum mem_type mtype;
|
| 549 | enum edac_type edac_mode;
|
| 550 |
|
| 551 | u32 nr_pages;
|
| 552 |
|
| 553 | unsigned csrow, cschannel;
|
| 554 | };
|
| 555 |
|
| 556 | |
| 557 | * struct rank_info - contains the information for one DIMM rank
|
| 558 | *
|
| 559 | * @chan_idx: channel number where the rank is (typically, 0 or 1)
|
| 560 | * @ce_count: number of correctable errors for this rank
|
| 561 | * @csrow: A pointer to the chip select row structure (the parent
|
| 562 | * structure). The location of the rank is given by
|
| 563 | * the (csrow->csrow_idx, chan_idx) vector.
|
| 564 | * @dimm: A pointer to the DIMM structure, where the DIMM label
|
| 565 | * information is stored.
|
| 566 | *
|
| 567 | * FIXME: Currently, the EDAC core model will assume one DIMM per rank.
|
| 568 | * This is a bad assumption, but it makes this patch easier. Later
|
| 569 | * patches in this series will fix this issue.
|
| 570 |
|
| 571 | struct rank_info {
|
| 572 | int chan_idx;
|
| 573 | struct csrow_info *csrow;
|
| 574 | struct dimm_info *dimm;
|
| 575 |
|
| 576 | u32 ce_count;
|
| 577 | };
|
| 578 |
|
| 579 | struct csrow_info {
|
| 580 | struct device dev;
|
| 581 |
|
| 582 |
|
| 583 | unsigned long first_page;
|
| 584 | unsigned long last_page;
|
| 585 | unsigned long page_mask; |
| 586 | * 0UL for non intlv
|
| 587 |
|
| 588 | int csrow_idx;
|
| 589 |
|
| 590 | u32 ue_count;
|
| 591 | u32 ce_count;
|
| 592 |
|
| 593 | struct mem_ctl_info *mci;
|
| 594 |
|
| 595 |
|
| 596 | u32 nr_channels;
|
| 597 | struct rank_info **channels;
|
| 598 | };
|
| 599 |
|
| 600 | |
| 601 | * struct errcount_attribute - used to store the several error counts
|
| 602 |
|
| 603 | struct errcount_attribute_data {
|
| 604 | int n_layers;
|
| 605 | int pos[EDAC_MAX_LAYERS];
|
| 606 | int layer0, layer1, layer2;
|
| 607 | };
|
| 608 |
|
| 609 | |
| 610 | * edac_raw_error_desc - Raw error report structure
|
| 611 | * @grain: minimum granularity for an error report, in bytes
|
| 612 | * @error_count: number of errors of the same type
|
| 613 | * @top_layer: top layer of the error (layer[0])
|
| 614 | * @mid_layer: middle layer of the error (layer[1])
|
| 615 | * @low_layer: low layer of the error (layer[2])
|
| 616 | * @page_frame_number: page where the error happened
|
| 617 | * @offset_in_page: page offset
|
| 618 | * @syndrome: syndrome of the error (or 0 if unknown or if
|
| 619 | * the syndrome is not applicable)
|
| 620 | * @msg: error message
|
| 621 | * @location: location of the error
|
| 622 | * @label: label of the affected DIMM(s)
|
| 623 | * @other_detail: other driver-specific detail about the error
|
| 624 | * @enable_per_layer_report: if false, the error affects all layers
|
| 625 | * (typically, a memory controller error)
|
| 626 |
|
| 627 | struct edac_raw_error_desc {
|
| 628 | |
| 629 | * NOTE: everything before grain won't be cleaned by
|
| 630 | * edac_raw_error_desc_clean()
|
| 631 |
|
| 632 | char location[LOCATION_SIZE];
|
| 633 | char label[(EDAC_MC_LABEL_LEN + 1 + sizeof(OTHER_LABEL)) * EDAC_MAX_LABELS];
|
| 634 | long grain;
|
| 635 |
|
| 636 |
|
| 637 | u16 error_count;
|
| 638 | int top_layer;
|
| 639 | int mid_layer;
|
| 640 | int low_layer;
|
| 641 | unsigned long page_frame_number;
|
| 642 | unsigned long offset_in_page;
|
| 643 | unsigned long syndrome;
|
| 644 | const char *msg;
|
| 645 | const char *other_detail;
|
| 646 | bool enable_per_layer_report;
|
| 647 | };
|
| 648 |
|
| 649 | |
| 650 |
|
| 651 | struct mem_ctl_info {
|
| 652 | struct device dev;
|
| 653 | struct bus_type *bus;
|
| 654 |
|
| 655 | struct list_head link;
|
| 656 |
|
| 657 | struct module *owner;
|
| 658 |
|
| 659 | unsigned long mtype_cap;
|
| 660 | unsigned long edac_ctl_cap;
|
| 661 | unsigned long edac_cap; |
| 662 | * closely related to edac_ctl_cap. The
|
| 663 | * difference is that the controller may be
|
| 664 | * capable of s4ecd4ed which would be listed
|
| 665 | * in edac_ctl_cap, but if channels aren't
|
| 666 | * capable of s4ecd4ed then the edac_cap would
|
| 667 | * not have that capability.
|
| 668 |
|
| 669 | unsigned long scrub_cap;
|
| 670 | enum scrub_type scrub_mode;
|
| 671 |
|
| 672 | |
| 673 | internal representation and configures whatever else needs
|
| 674 | to be configured.
|
| 675 |
|
| 676 | int (*set_sdram_scrub_rate) (struct mem_ctl_info * mci, u32 bw);
|
| 677 |
|
| 678 | |
| 679 | representation and converts it to the closest matching
|
| 680 | bandwidth in bytes/sec.
|
| 681 |
|
| 682 | int (*get_sdram_scrub_rate) (struct mem_ctl_info * mci);
|
| 683 |
|
| 684 |
|
| 685 |
|
| 686 | void (*edac_check) (struct mem_ctl_info * mci);
|
| 687 |
|
| 688 | |
| 689 | * Remaps memory pages: controller pages to physical pages.
|
| 690 | * For most MC's, this will be NULL.
|
| 691 |
|
| 692 |
|
| 693 | unsigned long (*ctl_page_to_phys) (struct mem_ctl_info * mci,
|
| 694 | unsigned long page);
|
| 695 | int mc_idx;
|
| 696 | struct csrow_info **csrows;
|
| 697 | unsigned nr_csrows, num_cschannel;
|
| 698 |
|
| 699 | |
| 700 | * Memory Controller hierarchy
|
| 701 | *
|
| 702 | * There are basically two types of memory controller: the ones that
|
| 703 | * sees memory sticks ("dimms"), and the ones that sees memory ranks.
|
| 704 | * All old memory controllers enumerate memories per rank, but most
|
| 705 | * of the recent drivers enumerate memories per DIMM, instead.
|
| 706 | * When the memory controller is per rank, csbased is true.
|
| 707 |
|
| 708 | unsigned n_layers;
|
| 709 | struct edac_mc_layer *layers;
|
| 710 | bool csbased;
|
| 711 |
|
| 712 | |
| 713 | * DIMM info. Will eventually remove the entire csrows_info some day
|
| 714 |
|
| 715 | unsigned tot_dimms;
|
| 716 | struct dimm_info **dimms;
|
| 717 |
|
| 718 | |
| 719 | * FIXME - what about controllers on other busses? - IDs must be
|
| 720 | * unique. dev pointer should be sufficiently unique, but
|
| 721 | * BUS:SLOT.FUNC numbers may not be unique.
|
| 722 |
|
| 723 | struct device *pdev;
|
| 724 | const char *mod_name;
|
| 725 | const char *mod_ver;
|
| 726 | const char *ctl_name;
|
| 727 | const char *dev_name;
|
| 728 | void *pvt_info;
|
| 729 | unsigned long start_time;
|
| 730 |
|
| 731 | |
| 732 | * drivers shouldn't access those fields directly, as the core
|
| 733 | * already handles that.
|
| 734 |
|
| 735 | u32 ce_noinfo_count, ue_noinfo_count;
|
| 736 | u32 ue_mc, ce_mc;
|
| 737 | u32 *ce_per_layer[EDAC_MAX_LAYERS], *ue_per_layer[EDAC_MAX_LAYERS];
|
| 738 |
|
| 739 | struct completion complete;
|
| 740 |
|
| 741 | |
| 742 | * by the low level driver.
|
| 743 | *
|
| 744 | * Set by the low level driver to provide attributes at the
|
| 745 | * controller level.
|
| 746 | * An array of structures, NULL terminated
|
| 747 | *
|
| 748 | * If attributes are desired, then set to array of attributes
|
| 749 | * If no attributes are desired, leave NULL
|
| 750 |
|
| 751 | const struct mcidev_sysfs_attribute *mc_driver_sysfs_attributes;
|
| 752 |
|
| 753 |
|
| 754 | struct delayed_work work;
|
| 755 |
|
| 756 | |
| 757 | * Used to report an error - by being at the global struct
|
| 758 | * makes the memory allocated by the EDAC core
|
| 759 |
|
| 760 | struct edac_raw_error_desc error_desc;
|
| 761 |
|
| 762 |
|
| 763 | int op_state;
|
| 764 |
|
| 765 | #ifdef CONFIG_EDAC_DEBUG
|
| 766 | struct dentry *debugfs;
|
| 767 | u8 fake_inject_layer[EDAC_MAX_LAYERS];
|
| 768 | u32 fake_inject_ue;
|
| 769 | u16 fake_inject_count;
|
| 770 | #endif
|
| 771 | };
|
| 772 |
|
| 773 | |
| 774 | * Maximum number of memory controllers in the coherent fabric.
|
| 775 |
|
| 776 | #define EDAC_MAX_MCS 16
|
| 777 |
|
| 778 | #endif
|