| 1 | |
| 2 | * Marvell MBUS common definitions.
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| 3 | *
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| 4 | * Copyright (C) 2008 Marvell Semiconductor
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| 5 | *
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| 6 | * This file is licensed under the terms of the GNU General Public
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| 7 | * License version 2. This program is licensed "as is" without any
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| 8 | * warranty of any kind, whether express or implied.
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| 9 |
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| 10 |
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| 11 | #ifndef __LINUX_MBUS_H
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| 12 | #define __LINUX_MBUS_H
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| 13 |
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| 14 | #include <linux/errno.h>
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| 15 |
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| 16 | struct resource;
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| 17 |
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| 18 | struct mbus_dram_target_info
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| 19 | {
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| 20 | |
| 21 | * The 4-bit MBUS target ID of the DRAM controller.
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| 22 |
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| 23 | u8 mbus_dram_target_id;
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| 24 |
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| 25 | |
| 26 | * The base address, size, and MBUS attribute ID for each
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| 27 | * of the possible DRAM chip selects. Peripherals are
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| 28 | * required to support at least 4 decode windows.
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| 29 |
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| 30 | int num_cs;
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| 31 | struct mbus_dram_window {
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| 32 | u8 cs_index;
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| 33 | u8 mbus_attr;
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| 34 | u32 base;
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| 35 | u32 size;
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| 36 | } cs[4];
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| 37 | };
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| 38 |
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| 39 |
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| 40 | #define MVEBU_MBUS_PCI_IO 0x1
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| 41 | #define MVEBU_MBUS_PCI_MEM 0x2
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| 42 | #define MVEBU_MBUS_PCI_WA 0x3
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| 43 |
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| 44 | |
| 45 | * Magic value that explicits that we don't need a remapping-capable
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| 46 | * address decoding window.
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| 47 |
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| 48 | #define MVEBU_MBUS_NO_REMAP (0xffffffff)
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| 49 |
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| 50 |
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| 51 | #define MVEBU_MBUS_MAX_WINNAME_SZ 32
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| 52 |
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| 53 | |
| 54 | * The Marvell mbus is to be found only on SOCs from the Orion family
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| 55 | * at the moment. Provide a dummy stub for other architectures.
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| 56 |
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| 57 | #ifdef CONFIG_PLAT_ORION
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| 58 | extern const struct mbus_dram_target_info *mv_mbus_dram_info(void);
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| 59 | extern const struct mbus_dram_target_info *mv_mbus_dram_info_nooverlap(void);
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| 60 | int mvebu_mbus_get_io_win_info(phys_addr_t phyaddr, u32 *size, u8 *target,
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| 61 | u8 *attr);
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| 62 | #else
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| 63 | static inline const struct mbus_dram_target_info *mv_mbus_dram_info(void)
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| 64 | {
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| 65 | return NULL;
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| 66 | }
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| 67 | static inline const struct mbus_dram_target_info *mv_mbus_dram_info_nooverlap(void)
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| 68 | {
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| 69 | return NULL;
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| 70 | }
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| 71 | static inline int mvebu_mbus_get_io_win_info(phys_addr_t phyaddr, u32 *size,
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| 72 | u8 *target, u8 *attr)
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| 73 | {
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| 74 | |
| 75 | * On all ARM32 MVEBU platforms with MBus support, this stub
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| 76 | * function will not get called. The real function from the
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| 77 | * MBus driver is called instead. ARM64 MVEBU platforms like
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| 78 | * the Armada 3700 could use the mv_xor device driver which calls
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| 79 | * into this function
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| 80 |
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| 81 | return -EINVAL;
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| 82 | }
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| 83 | #endif
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| 84 |
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| 85 | #ifdef CONFIG_MVEBU_MBUS
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| 86 | int mvebu_mbus_save_cpu_target(u32 __iomem *store_addr);
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| 87 | void mvebu_mbus_get_pcie_mem_aperture(struct resource *res);
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| 88 | void mvebu_mbus_get_pcie_io_aperture(struct resource *res);
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| 89 | int mvebu_mbus_get_dram_win_info(phys_addr_t phyaddr, u8 *target, u8 *attr);
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| 90 | int mvebu_mbus_add_window_remap_by_id(unsigned int target,
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| 91 | unsigned int attribute,
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| 92 | phys_addr_t base, size_t size,
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| 93 | phys_addr_t remap);
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| 94 | int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute,
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| 95 | phys_addr_t base, size_t size);
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| 96 | int mvebu_mbus_del_window(phys_addr_t base, size_t size);
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| 97 | int mvebu_mbus_init(const char *soc, phys_addr_t mbus_phys_base,
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| 98 | size_t mbus_size, phys_addr_t sdram_phys_base,
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| 99 | size_t sdram_size);
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| 100 | int mvebu_mbus_dt_init(bool is_coherent);
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| 101 | #else
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| 102 | static inline int mvebu_mbus_get_dram_win_info(phys_addr_t phyaddr, u8 *target,
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| 103 | u8 *attr)
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| 104 | {
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| 105 | return -EINVAL;
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| 106 | }
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| 107 | #endif
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| 108 |
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| 109 | #endif
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