| 1 | |
| 2 | |
| 3 | * Generic implementation of 64-bit atomics using spinlocks,
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| 4 | * useful on processors that don't have 64-bit atomic instructions.
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| 5 | *
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| 6 | * Copyright © 2009 Paul Mackerras, IBM Corp. <[email protected]>
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| 7 |
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| 8 | #include <linux/types.h>
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| 9 | #include <linux/cache.h>
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| 10 | #include <linux/spinlock.h>
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| 11 | #include <linux/init.h>
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| 12 | #include <linux/export.h>
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| 13 | #include <linux/atomic.h>
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| 14 |
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| 15 | |
| 16 | * We use a hashed array of spinlocks to provide exclusive access
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| 17 | * to each atomic64_t variable. Since this is expected to used on
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| 18 | * systems with small numbers of CPUs (<= 4 or so), we use a
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| 19 | * relatively small array of 16 spinlocks to avoid wasting too much
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| 20 | * memory on the spinlock array.
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| 21 |
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| 22 | #define NR_LOCKS 16
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| 23 |
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| 24 | |
| 25 | * Ensure each lock is in a separate cacheline.
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| 26 |
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| 27 | static union {
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| 28 | raw_spinlock_t lock;
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| 29 | char pad[L1_CACHE_BYTES];
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| 30 | } atomic64_lock[NR_LOCKS] __cacheline_aligned_in_smp = {
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| 31 | [0 ... (NR_LOCKS - 1)] = {
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| 32 | .lock = __RAW_SPIN_LOCK_UNLOCKED(atomic64_lock.lock),
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| 33 | },
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| 34 | };
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| 35 |
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| 36 | static inline raw_spinlock_t *lock_addr(const atomic64_t *v)
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| 37 | {
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| 38 | unsigned long addr = (unsigned long) v;
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| 39 |
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| 40 | addr >>= L1_CACHE_SHIFT;
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| 41 | addr ^= (addr >> 8) ^ (addr >> 16);
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| 42 | return &atomic64_lock[addr & (NR_LOCKS - 1)].lock;
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| 43 | }
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| 44 |
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| 45 | long long atomic64_read(const atomic64_t *v)
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| 46 | {
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| 47 | unsigned long flags;
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| 48 | raw_spinlock_t *lock = lock_addr(v);
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| 49 | long long val;
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| 50 |
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| 51 | raw_spin_lock_irqsave(lock, flags);
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| 52 | val = v->counter;
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| 53 | raw_spin_unlock_irqrestore(lock, flags);
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| 54 | return val;
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| 55 | }
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| 56 | EXPORT_SYMBOL(atomic64_read);
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| 57 |
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| 58 | void atomic64_set(atomic64_t *v, long long i)
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| 59 | {
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| 60 | unsigned long flags;
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| 61 | raw_spinlock_t *lock = lock_addr(v);
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| 62 |
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| 63 | raw_spin_lock_irqsave(lock, flags);
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| 64 | v->counter = i;
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| 65 | raw_spin_unlock_irqrestore(lock, flags);
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| 66 | }
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| 67 | EXPORT_SYMBOL(atomic64_set);
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| 68 |
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| 69 | #define ATOMIC64_OP(op, c_op) \
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| 70 | void atomic64_##op(long long a, atomic64_t *v) \
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| 71 | { \
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| 72 | unsigned long flags; \
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| 73 | raw_spinlock_t *lock = lock_addr(v); \
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| 74 | \
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| 75 | raw_spin_lock_irqsave(lock, flags); \
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| 76 | v->counter c_op a; \
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| 77 | raw_spin_unlock_irqrestore(lock, flags); \
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| 78 | } \
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| 79 | EXPORT_SYMBOL(atomic64_##op);
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| 80 |
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| 81 | #define ATOMIC64_OP_RETURN(op, c_op) \
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| 82 | long long atomic64_##op##_return(long long a, atomic64_t *v) \
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| 83 | { \
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| 84 | unsigned long flags; \
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| 85 | raw_spinlock_t *lock = lock_addr(v); \
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| 86 | long long val; \
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| 87 | \
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| 88 | raw_spin_lock_irqsave(lock, flags); \
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| 89 | val = (v->counter c_op a); \
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| 90 | raw_spin_unlock_irqrestore(lock, flags); \
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| 91 | return val; \
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| 92 | } \
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| 93 | EXPORT_SYMBOL(atomic64_##op##_return);
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| 94 |
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| 95 | #define ATOMIC64_FETCH_OP(op, c_op) \
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| 96 | long long atomic64_fetch_##op(long long a, atomic64_t *v) \
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| 97 | { \
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| 98 | unsigned long flags; \
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| 99 | raw_spinlock_t *lock = lock_addr(v); \
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| 100 | long long val; \
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| 101 | \
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| 102 | raw_spin_lock_irqsave(lock, flags); \
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| 103 | val = v->counter; \
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| 104 | v->counter c_op a; \
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| 105 | raw_spin_unlock_irqrestore(lock, flags); \
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| 106 | return val; \
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| 107 | } \
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| 108 | EXPORT_SYMBOL(atomic64_fetch_##op);
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| 109 |
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| 110 | #define ATOMIC64_OPS(op, c_op) \
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| 111 | ATOMIC64_OP(op, c_op) \
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| 112 | ATOMIC64_OP_RETURN(op, c_op) \
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| 113 | ATOMIC64_FETCH_OP(op, c_op)
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| 114 |
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| 115 | ATOMIC64_OPS(add, +=)
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| 116 | ATOMIC64_OPS(sub, -=)
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| 117 |
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| 118 | #undef ATOMIC64_OPS
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| 119 | #define ATOMIC64_OPS(op, c_op) \
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| 120 | ATOMIC64_OP(op, c_op) \
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| 121 | ATOMIC64_OP_RETURN(op, c_op) \
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| 122 | ATOMIC64_FETCH_OP(op, c_op)
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| 123 |
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| 124 | ATOMIC64_OPS(and, &=)
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| 125 | ATOMIC64_OPS(or, |=)
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| 126 | ATOMIC64_OPS(xor, ^=)
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| 127 |
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| 128 | #undef ATOMIC64_OPS
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| 129 | #undef ATOMIC64_FETCH_OP
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| 130 | #undef ATOMIC64_OP_RETURN
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| 131 | #undef ATOMIC64_OP
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| 132 |
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| 133 | long long atomic64_dec_if_positive(atomic64_t *v)
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| 134 | {
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| 135 | unsigned long flags;
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| 136 | raw_spinlock_t *lock = lock_addr(v);
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| 137 | long long val;
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| 138 |
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| 139 | raw_spin_lock_irqsave(lock, flags);
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| 140 | val = v->counter - 1;
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| 141 | if (val >= 0)
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| 142 | v->counter = val;
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| 143 | raw_spin_unlock_irqrestore(lock, flags);
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| 144 | return val;
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| 145 | }
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| 146 | EXPORT_SYMBOL(atomic64_dec_if_positive);
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| 147 |
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| 148 | long long atomic64_cmpxchg(atomic64_t *v, long long o, long long n)
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| 149 | {
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| 150 | unsigned long flags;
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| 151 | raw_spinlock_t *lock = lock_addr(v);
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| 152 | long long val;
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| 153 |
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| 154 | raw_spin_lock_irqsave(lock, flags);
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| 155 | val = v->counter;
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| 156 | if (val == o)
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| 157 | v->counter = n;
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| 158 | raw_spin_unlock_irqrestore(lock, flags);
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| 159 | return val;
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| 160 | }
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| 161 | EXPORT_SYMBOL(atomic64_cmpxchg);
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| 162 |
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| 163 | long long atomic64_xchg(atomic64_t *v, long long new)
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| 164 | {
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| 165 | unsigned long flags;
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| 166 | raw_spinlock_t *lock = lock_addr(v);
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| 167 | long long val;
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| 168 |
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| 169 | raw_spin_lock_irqsave(lock, flags);
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| 170 | val = v->counter;
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| 171 | v->counter = new;
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| 172 | raw_spin_unlock_irqrestore(lock, flags);
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| 173 | return val;
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| 174 | }
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| 175 | EXPORT_SYMBOL(atomic64_xchg);
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| 176 |
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| 177 | long long atomic64_fetch_add_unless(atomic64_t *v, long long a, long long u)
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| 178 | {
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| 179 | unsigned long flags;
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| 180 | raw_spinlock_t *lock = lock_addr(v);
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| 181 | long long val;
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| 182 |
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| 183 | raw_spin_lock_irqsave(lock, flags);
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| 184 | val = v->counter;
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| 185 | if (val != u)
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| 186 | v->counter += a;
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| 187 | raw_spin_unlock_irqrestore(lock, flags);
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| 188 |
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| 189 | return val;
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| 190 | }
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| 191 | EXPORT_SYMBOL(atomic64_fetch_add_unless);
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