| 1 |
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| 2 | #ifndef _RESCTRL_H
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| 3 | #define _RESCTRL_H
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| 4 |
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| 5 | #include <linux/cacheinfo.h>
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| 6 | #include <linux/kernel.h>
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| 7 | #include <linux/list.h>
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| 8 | #include <linux/pid.h>
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| 9 |
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| 10 |
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| 11 | #define RESCTRL_RESERVED_CLOSID 0
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| 12 | #define RESCTRL_RESERVED_RMID 0
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| 13 |
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| 14 | #define RESCTRL_PICK_ANY_CPU -1
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| 15 |
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| 16 | #ifdef CONFIG_PROC_CPU_RESCTRL
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| 17 |
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| 18 | int proc_resctrl_show(struct seq_file *m,
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| 19 | struct pid_namespace *ns,
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| 20 | struct pid *pid,
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| 21 | struct task_struct *tsk);
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| 22 |
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| 23 | #endif
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| 24 |
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| 25 |
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| 26 | #define MBA_MAX_MBPS U32_MAX
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| 27 |
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| 28 | |
| 29 | * enum resctrl_conf_type - The type of configuration.
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| 30 | * @CDP_NONE: No prioritisation, both code and data are controlled or monitored.
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| 31 | * @CDP_CODE: Configuration applies to instruction fetches.
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| 32 | * @CDP_DATA: Configuration applies to reads and writes.
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| 33 |
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| 34 | enum resctrl_conf_type {
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| 35 | CDP_NONE,
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| 36 | CDP_CODE,
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| 37 | CDP_DATA,
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| 38 | };
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| 39 |
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| 40 | #define CDP_NUM_TYPES (CDP_DATA + 1)
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| 41 |
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| 42 | |
| 43 | * Event IDs, the values match those used to program IA32_QM_EVTSEL before
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| 44 | * reading IA32_QM_CTR on RDT systems.
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| 45 |
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| 46 | enum resctrl_event_id {
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| 47 | QOS_L3_OCCUP_EVENT_ID = 0x01,
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| 48 | QOS_L3_MBM_TOTAL_EVENT_ID = 0x02,
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| 49 | QOS_L3_MBM_LOCAL_EVENT_ID = 0x03,
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| 50 | };
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| 51 |
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| 52 | |
| 53 | * struct resctrl_staged_config - parsed configuration to be applied
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| 54 | * @new_ctrl: new ctrl value to be loaded
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| 55 | * @have_new_ctrl: whether the user provided new_ctrl is valid
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| 56 |
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| 57 | struct resctrl_staged_config {
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| 58 | u32 new_ctrl;
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| 59 | bool have_new_ctrl;
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| 60 | };
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| 61 |
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| 62 | enum resctrl_domain_type {
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| 63 | RESCTRL_CTRL_DOMAIN,
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| 64 | RESCTRL_MON_DOMAIN,
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| 65 | };
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| 66 |
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| 67 | |
| 68 | * struct rdt_domain_hdr - common header for different domain types
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| 69 | * @list: all instances of this resource
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| 70 | * @id: unique id for this instance
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| 71 | * @type: type of this instance
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| 72 | * @cpu_mask: which CPUs share this resource
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| 73 |
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| 74 | struct rdt_domain_hdr {
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| 75 | struct list_head list;
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| 76 | int id;
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| 77 | enum resctrl_domain_type type;
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| 78 | struct cpumask cpu_mask;
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| 79 | };
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| 80 |
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| 81 | |
| 82 | * struct rdt_ctrl_domain - group of CPUs sharing a resctrl control resource
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| 83 | * @hdr: common header for different domain types
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| 84 | * @plr: pseudo-locked region (if any) associated with domain
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| 85 | * @staged_config: parsed configuration to be applied
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| 86 | * @mbps_val: When mba_sc is enabled, this holds the array of user
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| 87 | * specified control values for mba_sc in MBps, indexed
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| 88 | * by closid
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| 89 |
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| 90 | struct rdt_ctrl_domain {
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| 91 | struct rdt_domain_hdr hdr;
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| 92 | struct pseudo_lock_region *plr;
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| 93 | struct resctrl_staged_config staged_config[CDP_NUM_TYPES];
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| 94 | u32 *mbps_val;
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| 95 | };
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| 96 |
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| 97 | |
| 98 | * struct rdt_mon_domain - group of CPUs sharing a resctrl monitor resource
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| 99 | * @hdr: common header for different domain types
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| 100 | * @ci: cache info for this domain
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| 101 | * @rmid_busy_llc: bitmap of which limbo RMIDs are above threshold
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| 102 | * @mbm_total: saved state for MBM total bandwidth
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| 103 | * @mbm_local: saved state for MBM local bandwidth
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| 104 | * @mbm_over: worker to periodically read MBM h/w counters
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| 105 | * @cqm_limbo: worker to periodically read CQM h/w counters
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| 106 | * @mbm_work_cpu: worker CPU for MBM h/w counters
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| 107 | * @cqm_work_cpu: worker CPU for CQM h/w counters
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| 108 |
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| 109 | struct rdt_mon_domain {
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| 110 | struct rdt_domain_hdr hdr;
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| 111 | struct cacheinfo *ci;
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| 112 | unsigned long *rmid_busy_llc;
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| 113 | struct mbm_state *mbm_total;
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| 114 | struct mbm_state *mbm_local;
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| 115 | struct delayed_work mbm_over;
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| 116 | struct delayed_work cqm_limbo;
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| 117 | int mbm_work_cpu;
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| 118 | int cqm_work_cpu;
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| 119 | };
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| 120 |
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| 121 | |
| 122 | * struct resctrl_cache - Cache allocation related data
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| 123 | * @cbm_len: Length of the cache bit mask
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| 124 | * @min_cbm_bits: Minimum number of consecutive bits to be set.
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| 125 | * The value 0 means the architecture can support
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| 126 | * zero CBM.
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| 127 | * @shareable_bits: Bitmask of shareable resource with other
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| 128 | * executing entities
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| 129 | * @arch_has_sparse_bitmasks: True if a bitmask like f00f is valid.
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| 130 | * @arch_has_per_cpu_cfg: True if QOS_CFG register for this cache
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| 131 | * level has CPU scope.
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| 132 |
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| 133 | struct resctrl_cache {
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| 134 | unsigned int cbm_len;
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| 135 | unsigned int min_cbm_bits;
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| 136 | unsigned int shareable_bits;
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| 137 | bool arch_has_sparse_bitmasks;
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| 138 | bool arch_has_per_cpu_cfg;
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| 139 | };
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| 140 |
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| 141 | |
| 142 | * enum membw_throttle_mode - System's memory bandwidth throttling mode
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| 143 | * @THREAD_THROTTLE_UNDEFINED: Not relevant to the system
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| 144 | * @THREAD_THROTTLE_MAX: Memory bandwidth is throttled at the core
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| 145 | * always using smallest bandwidth percentage
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| 146 | * assigned to threads, aka "max throttling"
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| 147 | * @THREAD_THROTTLE_PER_THREAD: Memory bandwidth is throttled at the thread
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| 148 |
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| 149 | enum membw_throttle_mode {
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| 150 | THREAD_THROTTLE_UNDEFINED = 0,
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| 151 | THREAD_THROTTLE_MAX,
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| 152 | THREAD_THROTTLE_PER_THREAD,
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| 153 | };
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| 154 |
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| 155 | |
| 156 | * struct resctrl_membw - Memory bandwidth allocation related data
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| 157 | * @min_bw: Minimum memory bandwidth percentage user can request
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| 158 | * @bw_gran: Granularity at which the memory bandwidth is allocated
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| 159 | * @delay_linear: True if memory B/W delay is in linear scale
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| 160 | * @arch_needs_linear: True if we can't configure non-linear resources
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| 161 | * @throttle_mode: Bandwidth throttling mode when threads request
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| 162 | * different memory bandwidths
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| 163 | * @mba_sc: True if MBA software controller(mba_sc) is enabled
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| 164 | * @mb_map: Mapping of memory B/W percentage to memory B/W delay
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| 165 |
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| 166 | struct resctrl_membw {
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| 167 | u32 min_bw;
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| 168 | u32 bw_gran;
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| 169 | u32 delay_linear;
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| 170 | bool arch_needs_linear;
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| 171 | enum membw_throttle_mode throttle_mode;
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| 172 | bool mba_sc;
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| 173 | u32 *mb_map;
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| 174 | };
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| 175 |
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| 176 | struct rdt_parse_data;
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| 177 | struct resctrl_schema;
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| 178 |
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| 179 | enum resctrl_scope {
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| 180 | RESCTRL_L2_CACHE = 2,
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| 181 | RESCTRL_L3_CACHE = 3,
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| 182 | RESCTRL_L3_NODE,
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| 183 | };
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| 184 |
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| 185 | |
| 186 | * struct rdt_resource - attributes of a resctrl resource
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| 187 | * @rid: The index of the resource
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| 188 | * @alloc_capable: Is allocation available on this machine
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| 189 | * @mon_capable: Is monitor feature available on this machine
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| 190 | * @num_rmid: Number of RMIDs available
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| 191 | * @ctrl_scope: Scope of this resource for control functions
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| 192 | * @mon_scope: Scope of this resource for monitor functions
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| 193 | * @cache: Cache allocation related data
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| 194 | * @membw: If the component has bandwidth controls, their properties.
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| 195 | * @ctrl_domains: RCU list of all control domains for this resource
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| 196 | * @mon_domains: RCU list of all monitor domains for this resource
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| 197 | * @name: Name to use in "schemata" file.
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| 198 | * @data_width: Character width of data when displaying
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| 199 | * @default_ctrl: Specifies default cache cbm or memory B/W percent.
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| 200 | * @format_str: Per resource format string to show domain value
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| 201 | * @parse_ctrlval: Per resource function pointer to parse control values
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| 202 | * @evt_list: List of monitoring events
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| 203 | * @fflags: flags to choose base and info files
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| 204 | * @cdp_capable: Is the CDP feature available on this resource
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| 205 |
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| 206 | struct rdt_resource {
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| 207 | int rid;
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| 208 | bool alloc_capable;
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| 209 | bool mon_capable;
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| 210 | int num_rmid;
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| 211 | enum resctrl_scope ctrl_scope;
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| 212 | enum resctrl_scope mon_scope;
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| 213 | struct resctrl_cache cache;
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| 214 | struct resctrl_membw membw;
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| 215 | struct list_head ctrl_domains;
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| 216 | struct list_head mon_domains;
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| 217 | char *name;
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| 218 | int data_width;
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| 219 | u32 default_ctrl;
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| 220 | const char *format_str;
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| 221 | int (*parse_ctrlval)(struct rdt_parse_data *data,
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| 222 | struct resctrl_schema *s,
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| 223 | struct rdt_ctrl_domain *d);
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| 224 | struct list_head evt_list;
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| 225 | unsigned long fflags;
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| 226 | bool cdp_capable;
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| 227 | };
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| 228 |
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| 229 | |
| 230 | * struct resctrl_schema - configuration abilities of a resource presented to
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| 231 | * user-space
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| 232 | * @list: Member of resctrl_schema_all.
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| 233 | * @name: The name to use in the "schemata" file.
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| 234 | * @conf_type: Whether this schema is specific to code/data.
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| 235 | * @res: The resource structure exported by the architecture to describe
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| 236 | * the hardware that is configured by this schema.
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| 237 | * @num_closid: The number of closid that can be used with this schema. When
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| 238 | * features like CDP are enabled, this will be lower than the
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| 239 | * hardware supports for the resource.
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| 240 |
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| 241 | struct resctrl_schema {
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| 242 | struct list_head list;
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| 243 | char name[8];
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| 244 | enum resctrl_conf_type conf_type;
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| 245 | struct rdt_resource *res;
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| 246 | u32 num_closid;
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| 247 | };
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| 248 |
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| 249 |
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| 250 | u32 resctrl_arch_get_num_closid(struct rdt_resource *r);
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| 251 | u32 resctrl_arch_system_num_rmid_idx(void);
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| 252 | int resctrl_arch_update_domains(struct rdt_resource *r, u32 closid);
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| 253 |
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| 254 | |
| 255 | * Update the ctrl_val and apply this config right now.
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| 256 | * Must be called on one of the domain's CPUs.
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| 257 |
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| 258 | int resctrl_arch_update_one(struct rdt_resource *r, struct rdt_ctrl_domain *d,
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| 259 | u32 closid, enum resctrl_conf_type t, u32 cfg_val);
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| 260 |
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| 261 | u32 resctrl_arch_get_config(struct rdt_resource *r, struct rdt_ctrl_domain *d,
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| 262 | u32 closid, enum resctrl_conf_type type);
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| 263 | int resctrl_online_ctrl_domain(struct rdt_resource *r, struct rdt_ctrl_domain *d);
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| 264 | int resctrl_online_mon_domain(struct rdt_resource *r, struct rdt_mon_domain *d);
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| 265 | void resctrl_offline_ctrl_domain(struct rdt_resource *r, struct rdt_ctrl_domain *d);
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| 266 | void resctrl_offline_mon_domain(struct rdt_resource *r, struct rdt_mon_domain *d);
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| 267 | void resctrl_online_cpu(unsigned int cpu);
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| 268 | void resctrl_offline_cpu(unsigned int cpu);
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| 269 |
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| 270 | |
| 271 | * resctrl_arch_rmid_read() - Read the eventid counter corresponding to rmid
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| 272 | * for this resource and domain.
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| 273 | * @r: resource that the counter should be read from.
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| 274 | * @d: domain that the counter should be read from.
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| 275 | * @closid: closid that matches the rmid. Depending on the architecture, the
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| 276 | * counter may match traffic of both @closid and @rmid, or @rmid
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| 277 | * only.
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| 278 | * @rmid: rmid of the counter to read.
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| 279 | * @eventid: eventid to read, e.g. L3 occupancy.
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| 280 | * @val: result of the counter read in bytes.
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| 281 | * @arch_mon_ctx: An architecture specific value from
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| 282 | * resctrl_arch_mon_ctx_alloc(), for MPAM this identifies
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| 283 | * the hardware monitor allocated for this read request.
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| 284 | *
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| 285 | * Some architectures need to sleep when first programming some of the counters.
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| 286 | * (specifically: arm64's MPAM cache occupancy counters can return 'not ready'
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| 287 | * for a short period of time). Call from a non-migrateable process context on
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| 288 | * a CPU that belongs to domain @d. e.g. use smp_call_on_cpu() or
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| 289 | * schedule_work_on(). This function can be called with interrupts masked,
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| 290 | * e.g. using smp_call_function_any(), but may consistently return an error.
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| 291 | *
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| 292 | * Return:
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| 293 | * 0 on success, or -EIO, -EINVAL etc on error.
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| 294 |
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| 295 | int resctrl_arch_rmid_read(struct rdt_resource *r, struct rdt_mon_domain *d,
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| 296 | u32 closid, u32 rmid, enum resctrl_event_id eventid,
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| 297 | u64 *val, void *arch_mon_ctx);
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| 298 |
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| 299 | |
| 300 | * resctrl_arch_rmid_read_context_check() - warn about invalid contexts
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| 301 | *
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| 302 | * When built with CONFIG_DEBUG_ATOMIC_SLEEP generate a warning when
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| 303 | * resctrl_arch_rmid_read() is called with preemption disabled.
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| 304 | *
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| 305 | * The contract with resctrl_arch_rmid_read() is that if interrupts
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| 306 | * are unmasked, it can sleep. This allows NOHZ_FULL systems to use an
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| 307 | * IPI, (and fail if the call needed to sleep), while most of the time
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| 308 | * the work is scheduled, allowing the call to sleep.
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| 309 |
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| 310 | static inline void resctrl_arch_rmid_read_context_check(void)
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| 311 | {
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| 312 | if (!irqs_disabled())
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| 313 | might_sleep();
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| 314 | }
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| 315 |
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| 316 | |
| 317 | * resctrl_arch_reset_rmid() - Reset any private state associated with rmid
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| 318 | * and eventid.
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| 319 | * @r: The domain's resource.
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| 320 | * @d: The rmid's domain.
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| 321 | * @closid: closid that matches the rmid. Depending on the architecture, the
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| 322 | * counter may match traffic of both @closid and @rmid, or @rmid only.
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| 323 | * @rmid: The rmid whose counter values should be reset.
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| 324 | * @eventid: The eventid whose counter values should be reset.
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| 325 | *
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| 326 | * This can be called from any CPU.
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| 327 |
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| 328 | void resctrl_arch_reset_rmid(struct rdt_resource *r, struct rdt_mon_domain *d,
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| 329 | u32 closid, u32 rmid,
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| 330 | enum resctrl_event_id eventid);
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| 331 |
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| 332 | |
| 333 | * resctrl_arch_reset_rmid_all() - Reset all private state associated with
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| 334 | * all rmids and eventids.
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| 335 | * @r: The resctrl resource.
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| 336 | * @d: The domain for which all architectural counter state will
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| 337 | * be cleared.
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| 338 | *
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| 339 | * This can be called from any CPU.
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| 340 |
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| 341 | void resctrl_arch_reset_rmid_all(struct rdt_resource *r, struct rdt_mon_domain *d);
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| 342 |
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| 343 | extern unsigned int resctrl_rmid_realloc_threshold;
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| 344 | extern unsigned int resctrl_rmid_realloc_limit;
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| 345 |
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| 346 | #endif
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