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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * arch-independent dma-mapping routines
4 *
5 * Copyright (c) 2006 SUSE Linux Products GmbH
6 * Copyright (c) 2006 Tejun Heo <[email protected]>
7 */
8#include <linux/memblock.h> /* for max_pfn */
9#include <linux/acpi.h>
10#include <linux/dma-map-ops.h>
11#include <linux/export.h>
12#include <linux/gfp.h>
13#include <linux/iommu-dma.h>
14#include <linux/kmsan.h>
15#include <linux/of_device.h>
16#include <linux/slab.h>
17#include <linux/vmalloc.h>
18#include "debug.h"
19#include "direct.h"
20
21#define CREATE_TRACE_POINTS
22#include <trace/events/dma.h>
23
24#if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \
25 defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \
26 defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL)
27bool dma_default_coherent = IS_ENABLED(CONFIG_ARCH_DMA_DEFAULT_COHERENT);
28#endif
29
30/*
31 * Managed DMA API
32 */
33struct dma_devres {
34 size_t size;
35 void *vaddr;
36 dma_addr_t dma_handle;
37 unsigned long attrs;
38};
39
40static void dmam_release(struct device *dev, void *res)
41{
42 struct dma_devres *this = res;
43
44 dma_free_attrs(dev, this->size, this->vaddr, this->dma_handle,
45 this->attrs);
46}
47
48static int dmam_match(struct device *dev, void *res, void *match_data)
49{
50 struct dma_devres *this = res, *match = match_data;
51
52 if (this->vaddr == match->vaddr) {
53 WARN_ON(this->size != match->size ||
54 this->dma_handle != match->dma_handle);
55 return 1;
56 }
57 return 0;
58}
59
60/**
61 * dmam_free_coherent - Managed dma_free_coherent()
62 * @dev: Device to free coherent memory for
63 * @size: Size of allocation
64 * @vaddr: Virtual address of the memory to free
65 * @dma_handle: DMA handle of the memory to free
66 *
67 * Managed dma_free_coherent().
68 */
69void dmam_free_coherent(struct device *dev, size_t size, void *vaddr,
70 dma_addr_t dma_handle)
71{
72 struct dma_devres match_data = { size, vaddr, dma_handle };
73
74 WARN_ON(devres_destroy(dev, dmam_release, dmam_match, &match_data));
75 dma_free_coherent(dev, size, vaddr, dma_handle);
76}
77EXPORT_SYMBOL(dmam_free_coherent);
78
79/**
80 * dmam_alloc_attrs - Managed dma_alloc_attrs()
81 * @dev: Device to allocate non_coherent memory for
82 * @size: Size of allocation
83 * @dma_handle: Out argument for allocated DMA handle
84 * @gfp: Allocation flags
85 * @attrs: Flags in the DMA_ATTR_* namespace.
86 *
87 * Managed dma_alloc_attrs(). Memory allocated using this function will be
88 * automatically released on driver detach.
89 *
90 * RETURNS:
91 * Pointer to allocated memory on success, NULL on failure.
92 */
93void *dmam_alloc_attrs(struct device *dev, size_t size, dma_addr_t *dma_handle,
94 gfp_t gfp, unsigned long attrs)
95{
96 struct dma_devres *dr;
97 void *vaddr;
98
99 dr = devres_alloc(dmam_release, sizeof(*dr), gfp);
100 if (!dr)
101 return NULL;
102
103 vaddr = dma_alloc_attrs(dev, size, dma_handle, gfp, attrs);
104 if (!vaddr) {
105 devres_free(dr);
106 return NULL;
107 }
108
109 dr->vaddr = vaddr;
110 dr->dma_handle = *dma_handle;
111 dr->size = size;
112 dr->attrs = attrs;
113
114 devres_add(dev, dr);
115
116 return vaddr;
117}
118EXPORT_SYMBOL(dmam_alloc_attrs);
119
120static bool dma_go_direct(struct device *dev, dma_addr_t mask,
121 const struct dma_map_ops *ops)
122{
123 if (use_dma_iommu(dev))
124 return false;
125
126 if (likely(!ops))
127 return true;
128
129#ifdef CONFIG_DMA_OPS_BYPASS
130 if (dev->dma_ops_bypass)
131 return min_not_zero(mask, dev->bus_dma_limit) >=
132 dma_direct_get_required_mask(dev);
133#endif
134 return false;
135}
136
137
138/*
139 * Check if the devices uses a direct mapping for streaming DMA operations.
140 * This allows IOMMU drivers to set a bypass mode if the DMA mask is large
141 * enough.
142 */
143static inline bool dma_alloc_direct(struct device *dev,
144 const struct dma_map_ops *ops)
145{
146 return dma_go_direct(dev, dev->coherent_dma_mask, ops);
147}
148
149static inline bool dma_map_direct(struct device *dev,
150 const struct dma_map_ops *ops)
151{
152 return dma_go_direct(dev, *dev->dma_mask, ops);
153}
154
155dma_addr_t dma_map_phys(struct device *dev, phys_addr_t phys, size_t size,
156 enum dma_data_direction dir, unsigned long attrs)
157{
158 const struct dma_map_ops *ops = get_dma_ops(dev);
159 bool is_mmio = attrs & DMA_ATTR_MMIO;
160 bool is_cc_shared = attrs & DMA_ATTR_CC_SHARED;
161 dma_addr_t addr = DMA_MAPPING_ERROR;
162
163 BUG_ON(!valid_dma_direction(dir));
164
165 if (WARN_ON_ONCE(!dev->dma_mask))
166 return DMA_MAPPING_ERROR;
167
168 if (!dev_is_dma_coherent(dev) && (attrs & DMA_ATTR_REQUIRE_COHERENT))
169 return DMA_MAPPING_ERROR;
170
171 if (dma_map_direct(dev, ops) ||
172 (!is_mmio && !is_cc_shared &&
173 arch_dma_map_phys_direct(dev, phys + size)))
174 addr = dma_direct_map_phys(dev, phys, size, dir, attrs, true);
175 else if (is_cc_shared)
176 return DMA_MAPPING_ERROR;
177 else if (use_dma_iommu(dev))
178 addr = iommu_dma_map_phys(dev, phys, size, dir, attrs);
179 else if (ops->map_phys)
180 addr = ops->map_phys(dev, phys, size, dir, attrs);
181
182 if (!is_mmio)
183 kmsan_handle_dma(phys, size, dir);
184 trace_dma_map_phys(dev, phys, addr, size, dir, attrs);
185 debug_dma_map_phys(dev, phys, size, dir, addr, attrs);
186
187 return addr;
188}
189EXPORT_SYMBOL_GPL(dma_map_phys);
190
191dma_addr_t dma_map_page_attrs(struct device *dev, struct page *page,
192 size_t offset, size_t size, enum dma_data_direction dir,
193 unsigned long attrs)
194{
195 phys_addr_t phys = page_to_phys(page) + offset;
196
197 if (unlikely(attrs & DMA_ATTR_MMIO))
198 return DMA_MAPPING_ERROR;
199
200 if (IS_ENABLED(CONFIG_DMA_API_DEBUG) &&
201 WARN_ON_ONCE(is_zone_device_page(page)))
202 return DMA_MAPPING_ERROR;
203
204 return dma_map_phys(dev, phys, size, dir, attrs);
205}
206EXPORT_SYMBOL(dma_map_page_attrs);
207
208void dma_unmap_phys(struct device *dev, dma_addr_t addr, size_t size,
209 enum dma_data_direction dir, unsigned long attrs)
210{
211 const struct dma_map_ops *ops = get_dma_ops(dev);
212 bool is_mmio = attrs & DMA_ATTR_MMIO;
213 bool is_cc_shared = attrs & DMA_ATTR_CC_SHARED;
214
215 BUG_ON(!valid_dma_direction(dir));
216
217 if (dma_map_direct(dev, ops) ||
218 (!is_mmio && !is_cc_shared &&
219 arch_dma_unmap_phys_direct(dev, addr + size)))
220 dma_direct_unmap_phys(dev, addr, size, dir, attrs, true);
221 else if (is_cc_shared)
222 return;
223 else if (use_dma_iommu(dev))
224 iommu_dma_unmap_phys(dev, addr, size, dir, attrs);
225 else if (ops->unmap_phys)
226 ops->unmap_phys(dev, addr, size, dir, attrs);
227 trace_dma_unmap_phys(dev, addr, size, dir, attrs);
228 debug_dma_unmap_phys(dev, addr, size, dir);
229}
230EXPORT_SYMBOL_GPL(dma_unmap_phys);
231
232void dma_unmap_page_attrs(struct device *dev, dma_addr_t addr, size_t size,
233 enum dma_data_direction dir, unsigned long attrs)
234{
235 if (unlikely(attrs & DMA_ATTR_MMIO))
236 return;
237
238 dma_unmap_phys(dev, addr, size, dir, attrs);
239}
240EXPORT_SYMBOL(dma_unmap_page_attrs);
241
242static int __dma_map_sg_attrs(struct device *dev, struct scatterlist *sg,
243 int nents, enum dma_data_direction dir, unsigned long attrs)
244{
245 const struct dma_map_ops *ops = get_dma_ops(dev);
246 int ents;
247
248 BUG_ON(!valid_dma_direction(dir));
249
250 if (!dev_is_dma_coherent(dev) && (attrs & DMA_ATTR_REQUIRE_COHERENT))
251 return -EOPNOTSUPP;
252
253 if (WARN_ON_ONCE(!dev->dma_mask))
254 return 0;
255
256 if (dma_map_direct(dev, ops) ||
257 arch_dma_map_sg_direct(dev, sg, nents))
258 ents = dma_direct_map_sg(dev, sg, nents, dir, attrs);
259 else if (use_dma_iommu(dev))
260 ents = iommu_dma_map_sg(dev, sg, nents, dir, attrs);
261 else
262 ents = ops->map_sg(dev, sg, nents, dir, attrs);
263
264 if (ents > 0) {
265 kmsan_handle_dma_sg(sg, nents, dir);
266 trace_dma_map_sg(dev, sg, nents, ents, dir, attrs);
267 debug_dma_map_sg(dev, sg, nents, ents, dir, attrs);
268 } else if (WARN_ON_ONCE(ents != -EINVAL && ents != -ENOMEM &&
269 ents != -EIO && ents != -EREMOTEIO)) {
270 trace_dma_map_sg_err(dev, sg, nents, ents, dir, attrs);
271 return -EIO;
272 }
273
274 return ents;
275}
276
277/**
278 * dma_map_sg_attrs - Map the given buffer for DMA
279 * @dev: The device for which to perform the DMA operation
280 * @sg: The sg_table object describing the buffer
281 * @nents: Number of entries to map
282 * @dir: DMA direction
283 * @attrs: Optional DMA attributes for the map operation
284 *
285 * Maps a buffer described by a scatterlist passed in the sg argument with
286 * nents segments for the @dir DMA operation by the @dev device.
287 *
288 * Returns the number of mapped entries (which can be less than nents)
289 * on success. Zero is returned for any error.
290 *
291 * dma_unmap_sg_attrs() should be used to unmap the buffer with the
292 * original sg and original nents (not the value returned by this funciton).
293 */
294unsigned int dma_map_sg_attrs(struct device *dev, struct scatterlist *sg,
295 int nents, enum dma_data_direction dir, unsigned long attrs)
296{
297 int ret;
298
299 ret = __dma_map_sg_attrs(dev, sg, nents, dir, attrs);
300 if (ret < 0)
301 return 0;
302 return ret;
303}
304EXPORT_SYMBOL(dma_map_sg_attrs);
305
306/**
307 * dma_map_sgtable - Map the given buffer for DMA
308 * @dev: The device for which to perform the DMA operation
309 * @sgt: The sg_table object describing the buffer
310 * @dir: DMA direction
311 * @attrs: Optional DMA attributes for the map operation
312 *
313 * Maps a buffer described by a scatterlist stored in the given sg_table
314 * object for the @dir DMA operation by the @dev device. After success, the
315 * ownership for the buffer is transferred to the DMA domain. One has to
316 * call dma_sync_sgtable_for_cpu() or dma_unmap_sgtable() to move the
317 * ownership of the buffer back to the CPU domain before touching the
318 * buffer by the CPU.
319 *
320 * Returns 0 on success or a negative error code on error. The following
321 * error codes are supported with the given meaning:
322 *
323 * -EINVAL An invalid argument, unaligned access or other error
324 * in usage. Will not succeed if retried.
325 * -ENOMEM Insufficient resources (like memory or IOVA space) to
326 * complete the mapping. Should succeed if retried later.
327 * -EIO Legacy error code with an unknown meaning. eg. this is
328 * returned if a lower level call returned
329 * DMA_MAPPING_ERROR.
330 * -EREMOTEIO The DMA device cannot access P2PDMA memory specified
331 * in the sg_table. This will not succeed if retried.
332 */
333int dma_map_sgtable(struct device *dev, struct sg_table *sgt,
334 enum dma_data_direction dir, unsigned long attrs)
335{
336 int nents;
337
338 nents = __dma_map_sg_attrs(dev, sgt->sgl, sgt->orig_nents, dir, attrs);
339 if (nents < 0)
340 return nents;
341 sgt->nents = nents;
342 return 0;
343}
344EXPORT_SYMBOL_GPL(dma_map_sgtable);
345
346void dma_unmap_sg_attrs(struct device *dev, struct scatterlist *sg,
347 int nents, enum dma_data_direction dir,
348 unsigned long attrs)
349{
350 const struct dma_map_ops *ops = get_dma_ops(dev);
351
352 BUG_ON(!valid_dma_direction(dir));
353 trace_dma_unmap_sg(dev, sg, nents, dir, attrs);
354 debug_dma_unmap_sg(dev, sg, nents, dir);
355 if (dma_map_direct(dev, ops) ||
356 arch_dma_unmap_sg_direct(dev, sg, nents))
357 dma_direct_unmap_sg(dev, sg, nents, dir, attrs);
358 else if (use_dma_iommu(dev))
359 iommu_dma_unmap_sg(dev, sg, nents, dir, attrs);
360 else if (ops->unmap_sg)
361 ops->unmap_sg(dev, sg, nents, dir, attrs);
362}
363EXPORT_SYMBOL(dma_unmap_sg_attrs);
364
365dma_addr_t dma_map_resource(struct device *dev, phys_addr_t phys_addr,
366 size_t size, enum dma_data_direction dir, unsigned long attrs)
367{
368 return dma_map_phys(dev, phys_addr, size, dir, attrs | DMA_ATTR_MMIO);
369}
370EXPORT_SYMBOL(dma_map_resource);
371
372void dma_unmap_resource(struct device *dev, dma_addr_t addr, size_t size,
373 enum dma_data_direction dir, unsigned long attrs)
374{
375 dma_unmap_phys(dev, addr, size, dir, attrs | DMA_ATTR_MMIO);
376}
377EXPORT_SYMBOL(dma_unmap_resource);
378
379#ifdef CONFIG_DMA_NEED_SYNC
380void __dma_sync_single_for_cpu(struct device *dev, dma_addr_t addr, size_t size,
381 enum dma_data_direction dir)
382{
383 const struct dma_map_ops *ops = get_dma_ops(dev);
384
385 BUG_ON(!valid_dma_direction(dir));
386 if (dma_map_direct(dev, ops))
387 dma_direct_sync_single_for_cpu(dev, addr, size, dir, true);
388 else if (use_dma_iommu(dev))
389 iommu_dma_sync_single_for_cpu(dev, addr, size, dir);
390 else if (ops->sync_single_for_cpu)
391 ops->sync_single_for_cpu(dev, addr, size, dir);
392 trace_dma_sync_single_for_cpu(dev, addr, size, dir);
393 debug_dma_sync_single_for_cpu(dev, addr, size, dir);
394}
395EXPORT_SYMBOL(__dma_sync_single_for_cpu);
396
397void __dma_sync_single_for_device(struct device *dev, dma_addr_t addr,
398 size_t size, enum dma_data_direction dir)
399{
400 const struct dma_map_ops *ops = get_dma_ops(dev);
401
402 BUG_ON(!valid_dma_direction(dir));
403 if (dma_map_direct(dev, ops))
404 dma_direct_sync_single_for_device(dev, addr, size, dir);
405 else if (use_dma_iommu(dev))
406 iommu_dma_sync_single_for_device(dev, addr, size, dir);
407 else if (ops->sync_single_for_device)
408 ops->sync_single_for_device(dev, addr, size, dir);
409 trace_dma_sync_single_for_device(dev, addr, size, dir);
410 debug_dma_sync_single_for_device(dev, addr, size, dir);
411}
412EXPORT_SYMBOL(__dma_sync_single_for_device);
413
414void __dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
415 int nelems, enum dma_data_direction dir)
416{
417 const struct dma_map_ops *ops = get_dma_ops(dev);
418
419 BUG_ON(!valid_dma_direction(dir));
420 if (dma_map_direct(dev, ops))
421 dma_direct_sync_sg_for_cpu(dev, sg, nelems, dir);
422 else if (use_dma_iommu(dev))
423 iommu_dma_sync_sg_for_cpu(dev, sg, nelems, dir);
424 else if (ops->sync_sg_for_cpu)
425 ops->sync_sg_for_cpu(dev, sg, nelems, dir);
426 trace_dma_sync_sg_for_cpu(dev, sg, nelems, dir);
427 debug_dma_sync_sg_for_cpu(dev, sg, nelems, dir);
428}
429EXPORT_SYMBOL(__dma_sync_sg_for_cpu);
430
431void __dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
432 int nelems, enum dma_data_direction dir)
433{
434 const struct dma_map_ops *ops = get_dma_ops(dev);
435
436 BUG_ON(!valid_dma_direction(dir));
437 if (dma_map_direct(dev, ops))
438 dma_direct_sync_sg_for_device(dev, sg, nelems, dir);
439 else if (use_dma_iommu(dev))
440 iommu_dma_sync_sg_for_device(dev, sg, nelems, dir);
441 else if (ops->sync_sg_for_device)
442 ops->sync_sg_for_device(dev, sg, nelems, dir);
443 trace_dma_sync_sg_for_device(dev, sg, nelems, dir);
444 debug_dma_sync_sg_for_device(dev, sg, nelems, dir);
445}
446EXPORT_SYMBOL(__dma_sync_sg_for_device);
447
448bool __dma_need_sync(struct device *dev, dma_addr_t dma_addr)
449{
450 const struct dma_map_ops *ops = get_dma_ops(dev);
451
452 if (dma_map_direct(dev, ops))
453 /*
454 * dma_skip_sync could've been reset on first SWIOTLB buffer
455 * mapping, but @dma_addr is not necessary an SWIOTLB buffer.
456 * In this case, fall back to more granular check.
457 */
458 return dma_direct_need_sync(dev, dma_addr);
459 return true;
460}
461EXPORT_SYMBOL_GPL(__dma_need_sync);
462
463/**
464 * dma_need_unmap - does this device need dma_unmap_* operations
465 * @dev: device to check
466 *
467 * If this function returns %false, drivers can skip calling dma_unmap_* after
468 * finishing an I/O. This function must be called after all mappings that might
469 * need to be unmapped have been performed.
470 */
471bool dma_need_unmap(struct device *dev)
472{
473 if (!dma_map_direct(dev, get_dma_ops(dev)))
474 return true;
475 if (!dev->dma_skip_sync)
476 return true;
477 return IS_ENABLED(CONFIG_DMA_API_DEBUG);
478}
479EXPORT_SYMBOL_GPL(dma_need_unmap);
480
481static void dma_setup_need_sync(struct device *dev)
482{
483 const struct dma_map_ops *ops = get_dma_ops(dev);
484
485 if (dma_map_direct(dev, ops) || use_dma_iommu(dev))
486 /*
487 * dma_skip_sync will be reset to %false on first SWIOTLB buffer
488 * mapping, if any. During the device initialization, it's
489 * enough to check only for the DMA coherence.
490 */
491 dev->dma_skip_sync = dev_is_dma_coherent(dev);
492 else if (!ops->sync_single_for_device && !ops->sync_single_for_cpu &&
493 !ops->sync_sg_for_device && !ops->sync_sg_for_cpu)
494 /*
495 * Synchronization is not possible when none of DMA sync ops
496 * is set.
497 */
498 dev->dma_skip_sync = true;
499 else
500 dev->dma_skip_sync = false;
501}
502#else /* !CONFIG_DMA_NEED_SYNC */
503static inline void dma_setup_need_sync(struct device *dev) { }
504#endif /* !CONFIG_DMA_NEED_SYNC */
505
506/*
507 * The whole dma_get_sgtable() idea is fundamentally unsafe - it seems
508 * that the intention is to allow exporting memory allocated via the
509 * coherent DMA APIs through the dma_buf API, which only accepts a
510 * scattertable. This presents a couple of problems:
511 * 1. Not all memory allocated via the coherent DMA APIs is backed by
512 * a struct page
513 * 2. Passing coherent DMA memory into the streaming APIs is not allowed
514 * as we will try to flush the memory through a different alias to that
515 * actually being used (and the flushes are redundant.)
516 */
517int dma_get_sgtable_attrs(struct device *dev, struct sg_table *sgt,
518 void *cpu_addr, dma_addr_t dma_addr, size_t size,
519 unsigned long attrs)
520{
521 const struct dma_map_ops *ops = get_dma_ops(dev);
522
523 if (dma_alloc_direct(dev, ops))
524 return dma_direct_get_sgtable(dev, sgt, cpu_addr, dma_addr,
525 size, attrs);
526 if (use_dma_iommu(dev))
527 return iommu_dma_get_sgtable(dev, sgt, cpu_addr, dma_addr,
528 size, attrs);
529 if (!ops->get_sgtable)
530 return -ENXIO;
531 return ops->get_sgtable(dev, sgt, cpu_addr, dma_addr, size, attrs);
532}
533EXPORT_SYMBOL(dma_get_sgtable_attrs);
534
535#ifdef CONFIG_MMU
536/*
537 * Return the page attributes used for mapping dma_alloc_* memory, either in
538 * kernel space if remapping is needed, or to userspace through dma_mmap_*.
539 */
540pgprot_t dma_pgprot(struct device *dev, pgprot_t prot, unsigned long attrs)
541{
542 if (dev_is_dma_coherent(dev))
543 return prot;
544#ifdef CONFIG_ARCH_HAS_DMA_WRITE_COMBINE
545 if (attrs & DMA_ATTR_WRITE_COMBINE)
546 return pgprot_writecombine(prot);
547#endif
548 return pgprot_dmacoherent(prot);
549}
550#endif /* CONFIG_MMU */
551
552/**
553 * dma_can_mmap - check if a given device supports dma_mmap_*
554 * @dev: device to check
555 *
556 * Returns %true if @dev supports dma_mmap_coherent() and dma_mmap_attrs() to
557 * map DMA allocations to userspace.
558 */
559bool dma_can_mmap(struct device *dev)
560{
561 const struct dma_map_ops *ops = get_dma_ops(dev);
562
563 if (dma_alloc_direct(dev, ops))
564 return dma_direct_can_mmap(dev);
565 if (use_dma_iommu(dev))
566 return true;
567 return ops->mmap != NULL;
568}
569EXPORT_SYMBOL_GPL(dma_can_mmap);
570
571/**
572 * dma_mmap_attrs - map a coherent DMA allocation into user space
573 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
574 * @vma: vm_area_struct describing requested user mapping
575 * @cpu_addr: kernel CPU-view address returned from dma_alloc_attrs
576 * @dma_addr: device-view address returned from dma_alloc_attrs
577 * @size: size of memory originally requested in dma_alloc_attrs
578 * @attrs: attributes of mapping properties requested in dma_alloc_attrs
579 *
580 * Map a coherent DMA buffer previously allocated by dma_alloc_attrs into user
581 * space. The coherent DMA buffer must not be freed by the driver until the
582 * user space mapping has been released.
583 */
584int dma_mmap_attrs(struct device *dev, struct vm_area_struct *vma,
585 void *cpu_addr, dma_addr_t dma_addr, size_t size,
586 unsigned long attrs)
587{
588 const struct dma_map_ops *ops = get_dma_ops(dev);
589
590 if (dma_alloc_direct(dev, ops))
591 return dma_direct_mmap(dev, vma, cpu_addr, dma_addr, size,
592 attrs);
593 if (use_dma_iommu(dev))
594 return iommu_dma_mmap(dev, vma, cpu_addr, dma_addr, size,
595 attrs);
596 if (!ops->mmap)
597 return -ENXIO;
598 return ops->mmap(dev, vma, cpu_addr, dma_addr, size, attrs);
599}
600EXPORT_SYMBOL(dma_mmap_attrs);
601
602u64 dma_get_required_mask(struct device *dev)
603{
604 const struct dma_map_ops *ops = get_dma_ops(dev);
605
606 if (dma_alloc_direct(dev, ops))
607 return dma_direct_get_required_mask(dev);
608
609 if (use_dma_iommu(dev))
610 return DMA_BIT_MASK(32);
611
612 if (ops->get_required_mask)
613 return ops->get_required_mask(dev);
614
615 /*
616 * We require every DMA ops implementation to at least support a 32-bit
617 * DMA mask (and use bounce buffering if that isn't supported in
618 * hardware). As the direct mapping code has its own routine to
619 * actually report an optimal mask we default to 32-bit here as that
620 * is the right thing for most IOMMUs, and at least not actively
621 * harmful in general.
622 */
623 return DMA_BIT_MASK(32);
624}
625EXPORT_SYMBOL_GPL(dma_get_required_mask);
626
627void *dma_alloc_attrs(struct device *dev, size_t size, dma_addr_t *dma_handle,
628 gfp_t flag, unsigned long attrs)
629{
630 const struct dma_map_ops *ops = get_dma_ops(dev);
631 void *cpu_addr;
632
633 WARN_ON_ONCE(!dev->coherent_dma_mask);
634
635 /*
636 * DMA allocations can never be turned back into a page pointer, so
637 * requesting compound pages doesn't make sense (and can't even be
638 * supported at all by various backends).
639 */
640 if (WARN_ON_ONCE(flag & __GFP_COMP))
641 return NULL;
642
643 if (dma_alloc_from_dev_coherent(dev, size, dma_handle, &cpu_addr)) {
644 trace_dma_alloc(dev, cpu_addr, *dma_handle, size,
645 DMA_BIDIRECTIONAL, flag, attrs);
646 return cpu_addr;
647 }
648
649 /* let the implementation decide on the zone to allocate from: */
650 flag &= ~(__GFP_DMA | __GFP_DMA32 | __GFP_HIGHMEM);
651
652 if (dma_alloc_direct(dev, ops) || arch_dma_alloc_direct(dev)) {
653 cpu_addr = dma_direct_alloc(dev, size, dma_handle, flag, attrs);
654 } else if (use_dma_iommu(dev)) {
655 cpu_addr = iommu_dma_alloc(dev, size, dma_handle, flag, attrs);
656 } else if (ops->alloc) {
657 cpu_addr = ops->alloc(dev, size, dma_handle, flag, attrs);
658 } else {
659 trace_dma_alloc(dev, NULL, 0, size, DMA_BIDIRECTIONAL, flag,
660 attrs);
661 return NULL;
662 }
663
664 trace_dma_alloc(dev, cpu_addr, *dma_handle, size, DMA_BIDIRECTIONAL,
665 flag, attrs);
666 debug_dma_alloc_coherent(dev, size, *dma_handle, cpu_addr, attrs);
667 return cpu_addr;
668}
669EXPORT_SYMBOL(dma_alloc_attrs);
670
671void dma_free_attrs(struct device *dev, size_t size, void *cpu_addr,
672 dma_addr_t dma_handle, unsigned long attrs)
673{
674 const struct dma_map_ops *ops = get_dma_ops(dev);
675
676 if (dma_release_from_dev_coherent(dev, get_order(size), cpu_addr))
677 return;
678 /*
679 * On non-coherent platforms which implement DMA-coherent buffers via
680 * non-cacheable remaps, ops->free() may call vunmap(). Thus getting
681 * this far in IRQ context is a) at risk of a BUG_ON() or trying to
682 * sleep on some machines, and b) an indication that the driver is
683 * probably misusing the coherent API anyway.
684 */
685 WARN_ON(irqs_disabled());
686
687 trace_dma_free(dev, cpu_addr, dma_handle, size, DMA_BIDIRECTIONAL,
688 attrs);
689 if (!cpu_addr)
690 return;
691
692 debug_dma_free_coherent(dev, size, cpu_addr, dma_handle);
693 if (dma_alloc_direct(dev, ops) || arch_dma_free_direct(dev, dma_handle))
694 dma_direct_free(dev, size, cpu_addr, dma_handle, attrs);
695 else if (use_dma_iommu(dev))
696 iommu_dma_free(dev, size, cpu_addr, dma_handle, attrs);
697 else if (ops->free)
698 ops->free(dev, size, cpu_addr, dma_handle, attrs);
699}
700EXPORT_SYMBOL(dma_free_attrs);
701
702static struct page *__dma_alloc_pages(struct device *dev, size_t size,
703 dma_addr_t *dma_handle, enum dma_data_direction dir, gfp_t gfp)
704{
705 const struct dma_map_ops *ops = get_dma_ops(dev);
706
707 if (WARN_ON_ONCE(!dev->coherent_dma_mask))
708 return NULL;
709 if (WARN_ON_ONCE(gfp & (__GFP_DMA | __GFP_DMA32 | __GFP_HIGHMEM)))
710 return NULL;
711 if (WARN_ON_ONCE(gfp & __GFP_COMP))
712 return NULL;
713
714 size = PAGE_ALIGN(size);
715 if (dma_alloc_direct(dev, ops))
716 return dma_direct_alloc_pages(dev, size, dma_handle, dir, gfp);
717 if (use_dma_iommu(dev))
718 return dma_common_alloc_pages(dev, size, dma_handle, dir, gfp);
719 if (!ops->alloc_pages_op)
720 return NULL;
721 return ops->alloc_pages_op(dev, size, dma_handle, dir, gfp);
722}
723
724struct page *dma_alloc_pages(struct device *dev, size_t size,
725 dma_addr_t *dma_handle, enum dma_data_direction dir, gfp_t gfp)
726{
727 struct page *page = __dma_alloc_pages(dev, size, dma_handle, dir, gfp);
728
729 if (page) {
730 trace_dma_alloc_pages(dev, page_to_virt(page), *dma_handle,
731 size, dir, gfp, 0);
732 debug_dma_alloc_pages(dev, page, size, dir, *dma_handle, 0);
733 } else {
734 trace_dma_alloc_pages(dev, NULL, 0, size, dir, gfp, 0);
735 }
736 return page;
737}
738EXPORT_SYMBOL_GPL(dma_alloc_pages);
739
740static void __dma_free_pages(struct device *dev, size_t size, struct page *page,
741 dma_addr_t dma_handle, enum dma_data_direction dir)
742{
743 const struct dma_map_ops *ops = get_dma_ops(dev);
744
745 size = PAGE_ALIGN(size);
746 if (dma_alloc_direct(dev, ops))
747 dma_direct_free_pages(dev, size, page, dma_handle, dir);
748 else if (use_dma_iommu(dev))
749 dma_common_free_pages(dev, size, page, dma_handle, dir);
750 else if (ops->free_pages)
751 ops->free_pages(dev, size, page, dma_handle, dir);
752}
753
754void dma_free_pages(struct device *dev, size_t size, struct page *page,
755 dma_addr_t dma_handle, enum dma_data_direction dir)
756{
757 trace_dma_free_pages(dev, page_to_virt(page), dma_handle, size, dir, 0);
758 debug_dma_free_pages(dev, page, size, dir, dma_handle);
759 __dma_free_pages(dev, size, page, dma_handle, dir);
760}
761EXPORT_SYMBOL_GPL(dma_free_pages);
762
763int dma_mmap_pages(struct device *dev, struct vm_area_struct *vma,
764 size_t size, struct page *page)
765{
766 unsigned long count = PAGE_ALIGN(size) >> PAGE_SHIFT;
767
768 if (vma->vm_pgoff >= count || vma_pages(vma) > count - vma->vm_pgoff)
769 return -ENXIO;
770 return remap_pfn_range(vma, vma->vm_start,
771 page_to_pfn(page) + vma->vm_pgoff,
772 vma_pages(vma) << PAGE_SHIFT, vma->vm_page_prot);
773}
774EXPORT_SYMBOL_GPL(dma_mmap_pages);
775
776static struct sg_table *alloc_single_sgt(struct device *dev, size_t size,
777 enum dma_data_direction dir, gfp_t gfp)
778{
779 struct sg_table *sgt;
780 struct page *page;
781
782 sgt = kmalloc_obj(*sgt, gfp);
783 if (!sgt)
784 return NULL;
785 if (sg_alloc_table(sgt, 1, gfp))
786 goto out_free_sgt;
787 page = __dma_alloc_pages(dev, size, &sgt->sgl->dma_address, dir, gfp);
788 if (!page)
789 goto out_free_table;
790 sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0);
791 sg_dma_len(sgt->sgl) = sgt->sgl->length;
792 return sgt;
793out_free_table:
794 sg_free_table(sgt);
795out_free_sgt:
796 kfree(sgt);
797 return NULL;
798}
799
800struct sg_table *dma_alloc_noncontiguous(struct device *dev, size_t size,
801 enum dma_data_direction dir, gfp_t gfp, unsigned long attrs)
802{
803 struct sg_table *sgt;
804
805 if (WARN_ON_ONCE(attrs & ~DMA_ATTR_ALLOC_SINGLE_PAGES))
806 return NULL;
807 if (WARN_ON_ONCE(gfp & __GFP_COMP))
808 return NULL;
809
810 if (use_dma_iommu(dev))
811 sgt = iommu_dma_alloc_noncontiguous(dev, size, dir, gfp, attrs);
812 else
813 sgt = alloc_single_sgt(dev, size, dir, gfp);
814
815 if (sgt) {
816 sgt->nents = 1;
817 trace_dma_alloc_sgt(dev, sgt, size, dir, gfp, attrs);
818 debug_dma_map_sg(dev, sgt->sgl, sgt->orig_nents, 1, dir, attrs);
819 } else {
820 trace_dma_alloc_sgt_err(dev, NULL, 0, size, dir, gfp, attrs);
821 }
822 return sgt;
823}
824EXPORT_SYMBOL_GPL(dma_alloc_noncontiguous);
825
826static void free_single_sgt(struct device *dev, size_t size,
827 struct sg_table *sgt, enum dma_data_direction dir)
828{
829 __dma_free_pages(dev, size, sg_page(sgt->sgl), sgt->sgl->dma_address,
830 dir);
831 sg_free_table(sgt);
832 kfree(sgt);
833}
834
835void dma_free_noncontiguous(struct device *dev, size_t size,
836 struct sg_table *sgt, enum dma_data_direction dir)
837{
838 trace_dma_free_sgt(dev, sgt, size, dir);
839 debug_dma_unmap_sg(dev, sgt->sgl, sgt->orig_nents, dir);
840
841 if (use_dma_iommu(dev))
842 iommu_dma_free_noncontiguous(dev, size, sgt, dir);
843 else
844 free_single_sgt(dev, size, sgt, dir);
845}
846EXPORT_SYMBOL_GPL(dma_free_noncontiguous);
847
848void *dma_vmap_noncontiguous(struct device *dev, size_t size,
849 struct sg_table *sgt)
850{
851
852 if (use_dma_iommu(dev))
853 return iommu_dma_vmap_noncontiguous(dev, size, sgt);
854
855 return page_address(sg_page(sgt->sgl));
856}
857EXPORT_SYMBOL_GPL(dma_vmap_noncontiguous);
858
859void dma_vunmap_noncontiguous(struct device *dev, void *vaddr)
860{
861 if (use_dma_iommu(dev))
862 iommu_dma_vunmap_noncontiguous(dev, vaddr);
863}
864EXPORT_SYMBOL_GPL(dma_vunmap_noncontiguous);
865
866int dma_mmap_noncontiguous(struct device *dev, struct vm_area_struct *vma,
867 size_t size, struct sg_table *sgt)
868{
869 if (use_dma_iommu(dev))
870 return iommu_dma_mmap_noncontiguous(dev, vma, size, sgt);
871 return dma_mmap_pages(dev, vma, size, sg_page(sgt->sgl));
872}
873EXPORT_SYMBOL_GPL(dma_mmap_noncontiguous);
874
875static int dma_supported(struct device *dev, u64 mask)
876{
877 const struct dma_map_ops *ops = get_dma_ops(dev);
878
879 if (use_dma_iommu(dev)) {
880 if (WARN_ON(ops))
881 return false;
882 return true;
883 }
884
885 /*
886 * ->dma_supported sets and clears the bypass flag, so ignore it here
887 * and always call into the method if there is one.
888 */
889 if (ops) {
890 if (!ops->dma_supported)
891 return true;
892 return ops->dma_supported(dev, mask);
893 }
894
895 return dma_direct_supported(dev, mask);
896}
897
898bool dma_pci_p2pdma_supported(struct device *dev)
899{
900 const struct dma_map_ops *ops = get_dma_ops(dev);
901
902 /*
903 * Note: dma_ops_bypass is not checked here because P2PDMA should
904 * not be used with dma mapping ops that do not have support even
905 * if the specific device is bypassing them.
906 */
907
908 /* if ops is not set, dma direct and default IOMMU support P2PDMA */
909 return !ops;
910}
911EXPORT_SYMBOL_GPL(dma_pci_p2pdma_supported);
912
913int dma_set_mask(struct device *dev, u64 mask)
914{
915 /*
916 * Truncate the mask to the actually supported dma_addr_t width to
917 * avoid generating unsupportable addresses.
918 */
919 mask = (dma_addr_t)mask;
920
921 if (!dev->dma_mask || !dma_supported(dev, mask))
922 return -EIO;
923
924 arch_dma_set_mask(dev, mask);
925 *dev->dma_mask = mask;
926 dma_setup_need_sync(dev);
927
928 return 0;
929}
930EXPORT_SYMBOL(dma_set_mask);
931
932int dma_set_coherent_mask(struct device *dev, u64 mask)
933{
934 /*
935 * Truncate the mask to the actually supported dma_addr_t width to
936 * avoid generating unsupportable addresses.
937 */
938 mask = (dma_addr_t)mask;
939
940 if (!dma_supported(dev, mask))
941 return -EIO;
942
943 dev->coherent_dma_mask = mask;
944 return 0;
945}
946EXPORT_SYMBOL(dma_set_coherent_mask);
947
948static bool __dma_addressing_limited(struct device *dev)
949{
950 const struct dma_map_ops *ops = get_dma_ops(dev);
951
952 if (min_not_zero(dma_get_mask(dev), dev->bus_dma_limit) <
953 dma_get_required_mask(dev))
954 return true;
955
956 if (unlikely(ops) || use_dma_iommu(dev))
957 return false;
958 return !dma_direct_all_ram_mapped(dev);
959}
960
961/**
962 * dma_addressing_limited - return if the device is addressing limited
963 * @dev: device to check
964 *
965 * Return %true if the devices DMA mask is too small to address all memory in
966 * the system, else %false. Lack of addressing bits is the prime reason for
967 * bounce buffering, but might not be the only one.
968 */
969bool dma_addressing_limited(struct device *dev)
970{
971 if (!__dma_addressing_limited(dev))
972 return false;
973
974 dev_dbg(dev, "device is DMA addressing limited\n");
975 return true;
976}
977EXPORT_SYMBOL_GPL(dma_addressing_limited);
978
979size_t dma_max_mapping_size(struct device *dev)
980{
981 const struct dma_map_ops *ops = get_dma_ops(dev);
982 size_t size = SIZE_MAX;
983
984 if (dma_map_direct(dev, ops))
985 size = dma_direct_max_mapping_size(dev);
986 else if (use_dma_iommu(dev))
987 size = iommu_dma_max_mapping_size(dev);
988 else if (ops && ops->max_mapping_size)
989 size = ops->max_mapping_size(dev);
990
991 return size;
992}
993EXPORT_SYMBOL_GPL(dma_max_mapping_size);
994
995size_t dma_opt_mapping_size(struct device *dev)
996{
997 const struct dma_map_ops *ops = get_dma_ops(dev);
998 size_t size = SIZE_MAX;
999
1000 if (use_dma_iommu(dev))
1001 size = iommu_dma_opt_mapping_size();
1002 else if (ops && ops->opt_mapping_size)
1003 size = ops->opt_mapping_size();
1004
1005 return min(dma_max_mapping_size(dev), size);
1006}
1007EXPORT_SYMBOL_GPL(dma_opt_mapping_size);
1008
1009unsigned long dma_get_merge_boundary(struct device *dev)
1010{
1011 const struct dma_map_ops *ops = get_dma_ops(dev);
1012
1013 if (use_dma_iommu(dev))
1014 return iommu_dma_get_merge_boundary(dev);
1015
1016 if (!ops || !ops->get_merge_boundary)
1017 return 0; /* can't merge */
1018
1019 return ops->get_merge_boundary(dev);
1020}
1021EXPORT_SYMBOL_GPL(dma_get_merge_boundary);