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1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
4 */
5#ifndef LINUX_DMAENGINE_H
6#define LINUX_DMAENGINE_H
7
8#include <linux/device.h>
9#include <linux/err.h>
10#include <linux/uio.h>
11#include <linux/bug.h>
12#include <linux/scatterlist.h>
13#include <linux/bitmap.h>
14#include <linux/types.h>
15#include <asm/page.h>
16
17/**
18 * typedef dma_cookie_t - an opaque DMA cookie
19 *
20 * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code
21 */
22typedef s32 dma_cookie_t;
23#define DMA_MIN_COOKIE 1
24
25static inline int dma_submit_error(dma_cookie_t cookie)
26{
27 return cookie < 0 ? cookie : 0;
28}
29
30/**
31 * enum dma_status - DMA transaction status
32 * @DMA_COMPLETE: transaction completed
33 * @DMA_IN_PROGRESS: transaction not yet processed
34 * @DMA_PAUSED: transaction is paused
35 * @DMA_ERROR: transaction failed
36 */
37enum dma_status {
38 DMA_COMPLETE,
39 DMA_IN_PROGRESS,
40 DMA_PAUSED,
41 DMA_ERROR,
42 DMA_OUT_OF_ORDER,
43};
44
45/**
46 * enum dma_transaction_type - DMA transaction types/indexes
47 *
48 * Note: The DMA_ASYNC_TX capability is not to be set by drivers. It is
49 * automatically set as dma devices are registered.
50 */
51enum dma_transaction_type {
52 DMA_MEMCPY,
53 DMA_XOR,
54 DMA_PQ,
55 DMA_XOR_VAL,
56 DMA_PQ_VAL,
57 DMA_MEMSET,
58 DMA_MEMSET_SG,
59 DMA_INTERRUPT,
60 DMA_PRIVATE,
61 DMA_ASYNC_TX,
62 DMA_SLAVE,
63 DMA_CYCLIC,
64 DMA_INTERLEAVE,
65 DMA_COMPLETION_NO_ORDER,
66 DMA_REPEAT,
67 DMA_LOAD_EOT,
68/* last transaction type for creation of the capabilities mask */
69 DMA_TX_TYPE_END,
70};
71
72/**
73 * enum dma_transfer_direction - dma transfer mode and direction indicator
74 * @DMA_MEM_TO_MEM: Async/Memcpy mode
75 * @DMA_MEM_TO_DEV: Slave mode & From Memory to Device
76 * @DMA_DEV_TO_MEM: Slave mode & From Device to Memory
77 * @DMA_DEV_TO_DEV: Slave mode & From Device to Device
78 */
79enum dma_transfer_direction {
80 DMA_MEM_TO_MEM,
81 DMA_MEM_TO_DEV,
82 DMA_DEV_TO_MEM,
83 DMA_DEV_TO_DEV,
84 DMA_TRANS_NONE,
85};
86
87/*
88 * Interleaved Transfer Request
89 * ----------------------------
90 * A chunk is collection of contiguous bytes to be transferred.
91 * The gap(in bytes) between two chunks is called inter-chunk-gap(ICG).
92 * ICGs may or may not change between chunks.
93 * A FRAME is the smallest series of contiguous {chunk,icg} pairs,
94 * that when repeated an integral number of times, specifies the transfer.
95 * A transfer template is specification of a Frame, the number of times
96 * it is to be repeated and other per-transfer attributes.
97 *
98 * Practically, a client driver would have ready a template for each
99 * type of transfer it is going to need during its lifetime and
100 * set only 'src_start' and 'dst_start' before submitting the requests.
101 *
102 *
103 * | Frame-1 | Frame-2 | ~ | Frame-'numf' |
104 * |====....==.===...=...|====....==.===...=...| ~ |====....==.===...=...|
105 *
106 * == Chunk size
107 * ... ICG
108 */
109
110/**
111 * struct data_chunk - Element of scatter-gather list that makes a frame.
112 * @size: Number of bytes to read from source.
113 * size_dst := fn(op, size_src), so doesn't mean much for destination.
114 * @icg: Number of bytes to jump after last src/dst address of this
115 * chunk and before first src/dst address for next chunk.
116 * Ignored for dst(assumed 0), if dst_inc is true and dst_sgl is false.
117 * Ignored for src(assumed 0), if src_inc is true and src_sgl is false.
118 * @dst_icg: Number of bytes to jump after last dst address of this
119 * chunk and before the first dst address for next chunk.
120 * Ignored if dst_inc is true and dst_sgl is false.
121 * @src_icg: Number of bytes to jump after last src address of this
122 * chunk and before the first src address for next chunk.
123 * Ignored if src_inc is true and src_sgl is false.
124 */
125struct data_chunk {
126 size_t size;
127 size_t icg;
128 size_t dst_icg;
129 size_t src_icg;
130};
131
132/**
133 * struct dma_interleaved_template - Template to convey DMAC the transfer pattern
134 * and attributes.
135 * @src_start: Bus address of source for the first chunk.
136 * @dst_start: Bus address of destination for the first chunk.
137 * @dir: Specifies the type of Source and Destination.
138 * @src_inc: If the source address increments after reading from it.
139 * @dst_inc: If the destination address increments after writing to it.
140 * @src_sgl: If the 'icg' of sgl[] applies to Source (scattered read).
141 * Otherwise, source is read contiguously (icg ignored).
142 * Ignored if src_inc is false.
143 * @dst_sgl: If the 'icg' of sgl[] applies to Destination (scattered write).
144 * Otherwise, destination is filled contiguously (icg ignored).
145 * Ignored if dst_inc is false.
146 * @numf: Number of frames in this template.
147 * @frame_size: Number of chunks in a frame i.e, size of sgl[].
148 * @sgl: Array of {chunk,icg} pairs that make up a frame.
149 */
150struct dma_interleaved_template {
151 dma_addr_t src_start;
152 dma_addr_t dst_start;
153 enum dma_transfer_direction dir;
154 bool src_inc;
155 bool dst_inc;
156 bool src_sgl;
157 bool dst_sgl;
158 size_t numf;
159 size_t frame_size;
160 struct data_chunk sgl[];
161};
162
163/**
164 * struct dma_vec - DMA vector
165 * @addr: Bus address of the start of the vector
166 * @len: Length in bytes of the DMA vector
167 */
168struct dma_vec {
169 dma_addr_t addr;
170 size_t len;
171};
172
173/**
174 * enum dma_ctrl_flags - DMA flags to augment operation preparation,
175 * control completion, and communicate status.
176 * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of
177 * this transaction
178 * @DMA_CTRL_ACK - if clear, the descriptor cannot be reused until the client
179 * acknowledges receipt, i.e. has a chance to establish any dependency
180 * chains
181 * @DMA_PREP_PQ_DISABLE_P - prevent generation of P while generating Q
182 * @DMA_PREP_PQ_DISABLE_Q - prevent generation of Q while generating P
183 * @DMA_PREP_CONTINUE - indicate to a driver that it is reusing buffers as
184 * sources that were the result of a previous operation, in the case of a PQ
185 * operation it continues the calculation with new sources
186 * @DMA_PREP_FENCE - tell the driver that subsequent operations depend
187 * on the result of this operation
188 * @DMA_CTRL_REUSE: client can reuse the descriptor and submit again till
189 * cleared or freed
190 * @DMA_PREP_CMD: tell the driver that the data passed to DMA API is command
191 * data and the descriptor should be in different format from normal
192 * data descriptors.
193 * @DMA_PREP_REPEAT: tell the driver that the transaction shall be automatically
194 * repeated when it ends until a transaction is issued on the same channel
195 * with the DMA_PREP_LOAD_EOT flag set. This flag is only applicable to
196 * interleaved transactions and is ignored for all other transaction types.
197 * @DMA_PREP_LOAD_EOT: tell the driver that the transaction shall replace any
198 * active repeated (as indicated by DMA_PREP_REPEAT) transaction when the
199 * repeated transaction ends. Not setting this flag when the previously queued
200 * transaction is marked with DMA_PREP_REPEAT will cause the new transaction
201 * to never be processed and stay in the issued queue forever. The flag is
202 * ignored if the previous transaction is not a repeated transaction.
203 */
204enum dma_ctrl_flags {
205 DMA_PREP_INTERRUPT = (1 << 0),
206 DMA_CTRL_ACK = (1 << 1),
207 DMA_PREP_PQ_DISABLE_P = (1 << 2),
208 DMA_PREP_PQ_DISABLE_Q = (1 << 3),
209 DMA_PREP_CONTINUE = (1 << 4),
210 DMA_PREP_FENCE = (1 << 5),
211 DMA_CTRL_REUSE = (1 << 6),
212 DMA_PREP_CMD = (1 << 7),
213 DMA_PREP_REPEAT = (1 << 8),
214 DMA_PREP_LOAD_EOT = (1 << 9),
215};
216
217/**
218 * enum sum_check_bits - bit position of pq_check_flags
219 */
220enum sum_check_bits {
221 SUM_CHECK_P = 0,
222 SUM_CHECK_Q = 1,
223};
224
225/**
226 * enum sum_check_flags - result of async_{xor,pq}_zero_sum operations
227 * @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise
228 * @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise
229 */
230enum sum_check_flags {
231 SUM_CHECK_P_RESULT = (1 << SUM_CHECK_P),
232 SUM_CHECK_Q_RESULT = (1 << SUM_CHECK_Q),
233};
234
235
236/**
237 * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t.
238 * See linux/cpumask.h
239 */
240typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t;
241
242/**
243 * enum dma_desc_metadata_mode - per descriptor metadata mode types supported
244 * @DESC_METADATA_CLIENT - the metadata buffer is allocated/provided by the
245 * client driver and it is attached (via the dmaengine_desc_attach_metadata()
246 * helper) to the descriptor.
247 *
248 * Client drivers interested to use this mode can follow:
249 * - DMA_MEM_TO_DEV / DEV_MEM_TO_MEM:
250 * 1. prepare the descriptor (dmaengine_prep_*)
251 * construct the metadata in the client's buffer
252 * 2. use dmaengine_desc_attach_metadata() to attach the buffer to the
253 * descriptor
254 * 3. submit the transfer
255 * - DMA_DEV_TO_MEM:
256 * 1. prepare the descriptor (dmaengine_prep_*)
257 * 2. use dmaengine_desc_attach_metadata() to attach the buffer to the
258 * descriptor
259 * 3. submit the transfer
260 * 4. when the transfer is completed, the metadata should be available in the
261 * attached buffer
262 *
263 * @DESC_METADATA_ENGINE - the metadata buffer is allocated/managed by the DMA
264 * driver. The client driver can ask for the pointer, maximum size and the
265 * currently used size of the metadata and can directly update or read it.
266 * dmaengine_desc_get_metadata_ptr() and dmaengine_desc_set_metadata_len() is
267 * provided as helper functions.
268 *
269 * Note: the metadata area for the descriptor is no longer valid after the
270 * transfer has been completed (valid up to the point when the completion
271 * callback returns if used).
272 *
273 * Client drivers interested to use this mode can follow:
274 * - DMA_MEM_TO_DEV / DEV_MEM_TO_MEM:
275 * 1. prepare the descriptor (dmaengine_prep_*)
276 * 2. use dmaengine_desc_get_metadata_ptr() to get the pointer to the engine's
277 * metadata area
278 * 3. update the metadata at the pointer
279 * 4. use dmaengine_desc_set_metadata_len() to tell the DMA engine the amount
280 * of data the client has placed into the metadata buffer
281 * 5. submit the transfer
282 * - DMA_DEV_TO_MEM:
283 * 1. prepare the descriptor (dmaengine_prep_*)
284 * 2. submit the transfer
285 * 3. on transfer completion, use dmaengine_desc_get_metadata_ptr() to get the
286 * pointer to the engine's metadata area
287 * 4. Read out the metadata from the pointer
288 *
289 * Warning: the two modes are not compatible and clients must use one mode for a
290 * descriptor.
291 */
292enum dma_desc_metadata_mode {
293 DESC_METADATA_NONE = 0,
294 DESC_METADATA_CLIENT = BIT(0),
295 DESC_METADATA_ENGINE = BIT(1),
296};
297
298/**
299 * struct dma_chan_percpu - the per-CPU part of struct dma_chan
300 * @memcpy_count: transaction counter
301 * @bytes_transferred: byte counter
302 */
303struct dma_chan_percpu {
304 /* stats */
305 unsigned long memcpy_count;
306 unsigned long bytes_transferred;
307};
308
309/**
310 * struct dma_router - DMA router structure
311 * @dev: pointer to the DMA router device
312 * @route_free: function to be called when the route can be disconnected
313 */
314struct dma_router {
315 struct device *dev;
316 void (*route_free)(struct device *dev, void *route_data);
317};
318
319/**
320 * struct dma_chan - devices supply DMA channels, clients use them
321 * @device: ptr to the dma device who supplies this channel, always !%NULL
322 * @slave: ptr to the device using this channel
323 * @cookie: last cookie value returned to client
324 * @completed_cookie: last completed cookie for this channel
325 * @chan_id: channel ID for sysfs
326 * @dev: class device for sysfs
327 * @name: backlink name for sysfs
328 * @dbg_client_name: slave name for debugfs in format:
329 * dev_name(requester's dev):channel name, for example: "2b00000.mcasp:tx"
330 * @device_node: used to add this to the device chan list
331 * @local: per-cpu pointer to a struct dma_chan_percpu
332 * @client_count: how many clients are using this channel
333 * @table_count: number of appearances in the mem-to-mem allocation table
334 * @router: pointer to the DMA router structure
335 * @route_data: channel specific data for the router
336 * @private: private data for certain client-channel associations
337 */
338struct dma_chan {
339 struct dma_device *device;
340 struct device *slave;
341 dma_cookie_t cookie;
342 dma_cookie_t completed_cookie;
343
344 /* sysfs */
345 int chan_id;
346 struct dma_chan_dev *dev;
347 const char *name;
348#ifdef CONFIG_DEBUG_FS
349 char *dbg_client_name;
350#endif
351
352 struct list_head device_node;
353 struct dma_chan_percpu __percpu *local;
354 int client_count;
355 int table_count;
356
357 /* DMA router */
358 struct dma_router *router;
359 void *route_data;
360
361 void *private;
362};
363
364/**
365 * struct dma_chan_dev - relate sysfs device node to backing channel device
366 * @chan: driver channel device
367 * @device: sysfs device
368 * @dev_id: parent dma_device dev_id
369 * @chan_dma_dev: The channel is using custom/different dma-mapping
370 * compared to the parent dma_device
371 */
372struct dma_chan_dev {
373 struct dma_chan *chan;
374 struct device device;
375 int dev_id;
376 bool chan_dma_dev;
377};
378
379/**
380 * enum dma_slave_buswidth - defines bus width of the DMA slave
381 * device, source or target buses
382 */
383enum dma_slave_buswidth {
384 DMA_SLAVE_BUSWIDTH_UNDEFINED = 0,
385 DMA_SLAVE_BUSWIDTH_1_BYTE = 1,
386 DMA_SLAVE_BUSWIDTH_2_BYTES = 2,
387 DMA_SLAVE_BUSWIDTH_3_BYTES = 3,
388 DMA_SLAVE_BUSWIDTH_4_BYTES = 4,
389 DMA_SLAVE_BUSWIDTH_8_BYTES = 8,
390 DMA_SLAVE_BUSWIDTH_16_BYTES = 16,
391 DMA_SLAVE_BUSWIDTH_32_BYTES = 32,
392 DMA_SLAVE_BUSWIDTH_64_BYTES = 64,
393 DMA_SLAVE_BUSWIDTH_128_BYTES = 128,
394};
395
396/**
397 * struct dma_slave_config - dma slave channel runtime config
398 * @direction: whether the data shall go in or out on this slave
399 * channel, right now. DMA_MEM_TO_DEV and DMA_DEV_TO_MEM are
400 * legal values. DEPRECATED, drivers should use the direction argument
401 * to the device_prep_slave_sg and device_prep_dma_cyclic functions or
402 * the dir field in the dma_interleaved_template structure.
403 * @src_addr: this is the physical address where DMA slave data
404 * should be read (RX), if the source is memory this argument is
405 * ignored.
406 * @dst_addr: this is the physical address where DMA slave data
407 * should be written (TX), if the destination is memory this argument
408 * is ignored.
409 * @src_addr_width: this is the width in bytes of the source (RX)
410 * register where DMA data shall be read. If the source
411 * is memory this may be ignored depending on architecture.
412 * Legal values: 1, 2, 3, 4, 8, 16, 32, 64, 128.
413 * @dst_addr_width: same as src_addr_width but for destination
414 * target (TX) mutatis mutandis.
415 * @src_maxburst: the maximum number of words (note: words, as in
416 * units of the src_addr_width member, not bytes) that can be sent
417 * in one burst to the device. Typically something like half the
418 * FIFO depth on I/O peripherals so you don't overflow it. This
419 * may or may not be applicable on memory sources.
420 * @dst_maxburst: same as src_maxburst but for destination target
421 * mutatis mutandis.
422 * @src_port_window_size: The length of the register area in words the data need
423 * to be accessed on the device side. It is only used for devices which is using
424 * an area instead of a single register to receive the data. Typically the DMA
425 * loops in this area in order to transfer the data.
426 * @dst_port_window_size: same as src_port_window_size but for the destination
427 * port.
428 * @device_fc: Flow Controller Settings. Only valid for slave channels. Fill
429 * with 'true' if peripheral should be flow controller. Direction will be
430 * selected at Runtime.
431 * @peripheral_config: peripheral configuration for programming peripheral
432 * for dmaengine transfer
433 * @peripheral_size: peripheral configuration buffer size
434 *
435 * This struct is passed in as configuration data to a DMA engine
436 * in order to set up a certain channel for DMA transport at runtime.
437 * The DMA device/engine has to provide support for an additional
438 * callback in the dma_device structure, device_config and this struct
439 * will then be passed in as an argument to the function.
440 *
441 * The rationale for adding configuration information to this struct is as
442 * follows: if it is likely that more than one DMA slave controllers in
443 * the world will support the configuration option, then make it generic.
444 * If not: if it is fixed so that it be sent in static from the platform
445 * data, then prefer to do that.
446 */
447struct dma_slave_config {
448 enum dma_transfer_direction direction;
449 phys_addr_t src_addr;
450 phys_addr_t dst_addr;
451 enum dma_slave_buswidth src_addr_width;
452 enum dma_slave_buswidth dst_addr_width;
453 u32 src_maxburst;
454 u32 dst_maxburst;
455 u32 src_port_window_size;
456 u32 dst_port_window_size;
457 bool device_fc;
458 void *peripheral_config;
459 size_t peripheral_size;
460};
461
462/**
463 * enum dma_residue_granularity - Granularity of the reported transfer residue
464 * @DMA_RESIDUE_GRANULARITY_DESCRIPTOR: Residue reporting is not support. The
465 * DMA channel is only able to tell whether a descriptor has been completed or
466 * not, which means residue reporting is not supported by this channel. The
467 * residue field of the dma_tx_state field will always be 0.
468 * @DMA_RESIDUE_GRANULARITY_SEGMENT: Residue is updated after each successfully
469 * completed segment of the transfer (For cyclic transfers this is after each
470 * period). This is typically implemented by having the hardware generate an
471 * interrupt after each transferred segment and then the drivers updates the
472 * outstanding residue by the size of the segment. Another possibility is if
473 * the hardware supports scatter-gather and the segment descriptor has a field
474 * which gets set after the segment has been completed. The driver then counts
475 * the number of segments without the flag set to compute the residue.
476 * @DMA_RESIDUE_GRANULARITY_BURST: Residue is updated after each transferred
477 * burst. This is typically only supported if the hardware has a progress
478 * register of some sort (E.g. a register with the current read/write address
479 * or a register with the amount of bursts/beats/bytes that have been
480 * transferred or still need to be transferred).
481 */
482enum dma_residue_granularity {
483 DMA_RESIDUE_GRANULARITY_DESCRIPTOR = 0,
484 DMA_RESIDUE_GRANULARITY_SEGMENT = 1,
485 DMA_RESIDUE_GRANULARITY_BURST = 2,
486};
487
488/**
489 * struct dma_slave_caps - expose capabilities of a slave channel only
490 * @src_addr_widths: bit mask of src addr widths the channel supports.
491 * Width is specified in bytes, e.g. for a channel supporting
492 * a width of 4 the mask should have BIT(4) set.
493 * @dst_addr_widths: bit mask of dst addr widths the channel supports
494 * @directions: bit mask of slave directions the channel supports.
495 * Since the enum dma_transfer_direction is not defined as bit flag for
496 * each type, the dma controller should set BIT(<TYPE>) and same
497 * should be checked by controller as well
498 * @min_burst: min burst capability per-transfer
499 * @max_burst: max burst capability per-transfer
500 * @max_sg_burst: max number of SG list entries executed in a single burst
501 * DMA tansaction with no software intervention for reinitialization.
502 * Zero value means unlimited number of entries.
503 * @cmd_pause: true, if pause is supported (i.e. for reading residue or
504 * for resume later)
505 * @cmd_resume: true, if resume is supported
506 * @cmd_terminate: true, if terminate cmd is supported
507 * @residue_granularity: granularity of the reported transfer residue
508 * @descriptor_reuse: if a descriptor can be reused by client and
509 * resubmitted multiple times
510 */
511struct dma_slave_caps {
512 u32 src_addr_widths;
513 u32 dst_addr_widths;
514 u32 directions;
515 u32 min_burst;
516 u32 max_burst;
517 u32 max_sg_burst;
518 bool cmd_pause;
519 bool cmd_resume;
520 bool cmd_terminate;
521 enum dma_residue_granularity residue_granularity;
522 bool descriptor_reuse;
523};
524
525static inline const char *dma_chan_name(struct dma_chan *chan)
526{
527 return dev_name(&chan->dev->device);
528}
529
530/**
531 * typedef dma_filter_fn - callback filter for dma_request_channel
532 * @chan: channel to be reviewed
533 * @filter_param: opaque parameter passed through dma_request_channel
534 *
535 * When this optional parameter is specified in a call to dma_request_channel a
536 * suitable channel is passed to this routine for further dispositioning before
537 * being returned. Where 'suitable' indicates a non-busy channel that
538 * satisfies the given capability mask. It returns 'true' to indicate that the
539 * channel is suitable.
540 */
541typedef bool (*dma_filter_fn)(struct dma_chan *chan, void *filter_param);
542
543typedef void (*dma_async_tx_callback)(void *dma_async_param);
544
545enum dmaengine_tx_result {
546 DMA_TRANS_NOERROR = 0, /* SUCCESS */
547 DMA_TRANS_READ_FAILED, /* Source DMA read failed */
548 DMA_TRANS_WRITE_FAILED, /* Destination DMA write failed */
549 DMA_TRANS_ABORTED, /* Op never submitted / aborted */
550};
551
552struct dmaengine_result {
553 enum dmaengine_tx_result result;
554 u32 residue;
555};
556
557typedef void (*dma_async_tx_callback_result)(void *dma_async_param,
558 const struct dmaengine_result *result);
559
560struct dmaengine_unmap_data {
561#if IS_ENABLED(CONFIG_DMA_ENGINE_RAID)
562 u16 map_cnt;
563#else
564 u8 map_cnt;
565#endif
566 u8 to_cnt;
567 u8 from_cnt;
568 u8 bidi_cnt;
569 struct device *dev;
570 struct kref kref;
571 size_t len;
572 dma_addr_t addr[];
573};
574
575struct dma_async_tx_descriptor;
576
577struct dma_descriptor_metadata_ops {
578 int (*attach)(struct dma_async_tx_descriptor *desc, void *data,
579 size_t len);
580
581 void *(*get_ptr)(struct dma_async_tx_descriptor *desc,
582 size_t *payload_len, size_t *max_len);
583 int (*set_len)(struct dma_async_tx_descriptor *desc,
584 size_t payload_len);
585};
586
587/**
588 * struct dma_async_tx_descriptor - async transaction descriptor
589 * ---dma generic offload fields---
590 * @cookie: tracking cookie for this transaction, set to -EBUSY if
591 * this tx is sitting on a dependency list
592 * @flags: flags to augment operation preparation, control completion, and
593 * communicate status
594 * @phys: physical address of the descriptor
595 * @chan: target channel for this operation
596 * @tx_submit: accept the descriptor, assign ordered cookie and mark the
597 * descriptor pending. To be pushed on .issue_pending() call
598 * @desc_free: driver's callback function to free a resusable descriptor
599 * after completion
600 * @callback: routine to call after this operation is complete
601 * @callback_result: error result from a DMA transaction
602 * @callback_param: general parameter to pass to the callback routine
603 * @unmap: hook for generic DMA unmap data
604 * @desc_metadata_mode: core managed metadata mode to protect mixed use of
605 * DESC_METADATA_CLIENT or DESC_METADATA_ENGINE. Otherwise
606 * DESC_METADATA_NONE
607 * @metadata_ops: DMA driver provided metadata mode ops, need to be set by the
608 * DMA driver if metadata mode is supported with the descriptor
609 * ---async_tx api specific fields---
610 * @next: at completion submit this descriptor
611 * @parent: pointer to the next level up in the dependency chain
612 * @lock: protect the parent and next pointers
613 */
614struct dma_async_tx_descriptor {
615 dma_cookie_t cookie;
616 enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */
617 dma_addr_t phys;
618 struct dma_chan *chan;
619 dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx);
620 int (*desc_free)(struct dma_async_tx_descriptor *tx);
621 dma_async_tx_callback callback;
622 dma_async_tx_callback_result callback_result;
623 void *callback_param;
624 struct dmaengine_unmap_data *unmap;
625 enum dma_desc_metadata_mode desc_metadata_mode;
626 struct dma_descriptor_metadata_ops *metadata_ops;
627#ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
628 struct dma_async_tx_descriptor *next;
629 struct dma_async_tx_descriptor *parent;
630 spinlock_t lock;
631#endif
632};
633
634#ifdef CONFIG_DMA_ENGINE
635static inline void dma_set_unmap(struct dma_async_tx_descriptor *tx,
636 struct dmaengine_unmap_data *unmap)
637{
638 kref_get(&unmap->kref);
639 tx->unmap = unmap;
640}
641
642struct dmaengine_unmap_data *
643dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags);
644void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap);
645#else
646static inline void dma_set_unmap(struct dma_async_tx_descriptor *tx,
647 struct dmaengine_unmap_data *unmap)
648{
649}
650static inline struct dmaengine_unmap_data *
651dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags)
652{
653 return NULL;
654}
655static inline void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap)
656{
657}
658#endif
659
660static inline void dma_descriptor_unmap(struct dma_async_tx_descriptor *tx)
661{
662 if (!tx->unmap)
663 return;
664
665 dmaengine_unmap_put(tx->unmap);
666 tx->unmap = NULL;
667}
668
669#ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
670static inline void txd_lock(struct dma_async_tx_descriptor *txd)
671{
672}
673static inline void txd_unlock(struct dma_async_tx_descriptor *txd)
674{
675}
676static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next)
677{
678 BUG();
679}
680static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd)
681{
682}
683static inline void txd_clear_next(struct dma_async_tx_descriptor *txd)
684{
685}
686static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd)
687{
688 return NULL;
689}
690static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd)
691{
692 return NULL;
693}
694
695#else
696static inline void txd_lock(struct dma_async_tx_descriptor *txd)
697{
698 spin_lock_bh(&txd->lock);
699}
700static inline void txd_unlock(struct dma_async_tx_descriptor *txd)
701{
702 spin_unlock_bh(&txd->lock);
703}
704static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next)
705{
706 txd->next = next;
707 next->parent = txd;
708}
709static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd)
710{
711 txd->parent = NULL;
712}
713static inline void txd_clear_next(struct dma_async_tx_descriptor *txd)
714{
715 txd->next = NULL;
716}
717static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd)
718{
719 return txd->parent;
720}
721static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd)
722{
723 return txd->next;
724}
725#endif
726
727/**
728 * struct dma_tx_state - filled in to report the status of
729 * a transfer.
730 * @last: last completed DMA cookie
731 * @used: last issued DMA cookie (i.e. the one in progress)
732 * @residue: the remaining number of bytes left to transmit
733 * on the selected transfer for states DMA_IN_PROGRESS and
734 * DMA_PAUSED if this is implemented in the driver, else 0
735 * @in_flight_bytes: amount of data in bytes cached by the DMA.
736 */
737struct dma_tx_state {
738 dma_cookie_t last;
739 dma_cookie_t used;
740 u32 residue;
741 u32 in_flight_bytes;
742};
743
744/**
745 * enum dmaengine_alignment - defines alignment of the DMA async tx
746 * buffers
747 */
748enum dmaengine_alignment {
749 DMAENGINE_ALIGN_1_BYTE = 0,
750 DMAENGINE_ALIGN_2_BYTES = 1,
751 DMAENGINE_ALIGN_4_BYTES = 2,
752 DMAENGINE_ALIGN_8_BYTES = 3,
753 DMAENGINE_ALIGN_16_BYTES = 4,
754 DMAENGINE_ALIGN_32_BYTES = 5,
755 DMAENGINE_ALIGN_64_BYTES = 6,
756 DMAENGINE_ALIGN_128_BYTES = 7,
757 DMAENGINE_ALIGN_256_BYTES = 8,
758};
759
760/**
761 * struct dma_slave_map - associates slave device and it's slave channel with
762 * parameter to be used by a filter function
763 * @devname: name of the device
764 * @slave: slave channel name
765 * @param: opaque parameter to pass to struct dma_filter.fn
766 */
767struct dma_slave_map {
768 const char *devname;
769 const char *slave;
770 void *param;
771};
772
773/**
774 * struct dma_filter - information for slave device/channel to filter_fn/param
775 * mapping
776 * @fn: filter function callback
777 * @mapcnt: number of slave device/channel in the map
778 * @map: array of channel to filter mapping data
779 */
780struct dma_filter {
781 dma_filter_fn fn;
782 int mapcnt;
783 const struct dma_slave_map *map;
784};
785
786/**
787 * struct dma_device - info on the entity supplying DMA services
788 * @ref: reference is taken and put every time a channel is allocated or freed
789 * @chancnt: how many DMA channels are supported
790 * @privatecnt: how many DMA channels are requested by dma_request_channel
791 * @channels: the list of struct dma_chan
792 * @global_node: list_head for global dma_device_list
793 * @filter: information for device/slave to filter function/param mapping
794 * @cap_mask: one or more dma_capability flags
795 * @desc_metadata_modes: supported metadata modes by the DMA device
796 * @max_xor: maximum number of xor sources, 0 if no capability
797 * @max_pq: maximum number of PQ sources and PQ-continue capability
798 * @copy_align: alignment shift for memcpy operations
799 * @xor_align: alignment shift for xor operations
800 * @pq_align: alignment shift for pq operations
801 * @fill_align: alignment shift for memset operations
802 * @dev_id: unique device ID
803 * @dev: struct device reference for dma mapping api
804 * @owner: owner module (automatically set based on the provided dev)
805 * @chan_ida: unique channel ID
806 * @src_addr_widths: bit mask of src addr widths the device supports
807 * Width is specified in bytes, e.g. for a device supporting
808 * a width of 4 the mask should have BIT(4) set.
809 * @dst_addr_widths: bit mask of dst addr widths the device supports
810 * @directions: bit mask of slave directions the device supports.
811 * Since the enum dma_transfer_direction is not defined as bit flag for
812 * each type, the dma controller should set BIT(<TYPE>) and same
813 * should be checked by controller as well
814 * @min_burst: min burst capability per-transfer
815 * @max_burst: max burst capability per-transfer
816 * @max_sg_burst: max number of SG list entries executed in a single burst
817 * DMA tansaction with no software intervention for reinitialization.
818 * Zero value means unlimited number of entries.
819 * @descriptor_reuse: a submitted transfer can be resubmitted after completion
820 * @residue_granularity: granularity of the transfer residue reported
821 * by tx_status
822 * @device_alloc_chan_resources: allocate resources and return the
823 * number of allocated descriptors
824 * @device_router_config: optional callback for DMA router configuration
825 * @device_free_chan_resources: release DMA channel's resources
826 * @device_prep_dma_memcpy: prepares a memcpy operation
827 * @device_prep_dma_xor: prepares a xor operation
828 * @device_prep_dma_xor_val: prepares a xor validation operation
829 * @device_prep_dma_pq: prepares a pq operation
830 * @device_prep_dma_pq_val: prepares a pqzero_sum operation
831 * @device_prep_dma_memset: prepares a memset operation
832 * @device_prep_dma_memset_sg: prepares a memset operation over a scatter list
833 * @device_prep_dma_interrupt: prepares an end of chain interrupt operation
834 * @device_prep_peripheral_dma_vec: prepares a scatter-gather DMA transfer,
835 * where the address and size of each segment is located in one entry of
836 * the dma_vec array.
837 * @device_prep_slave_sg: prepares a slave dma operation
838 * @device_prep_dma_cyclic: prepare a cyclic dma operation suitable for audio.
839 * The function takes a buffer of size buf_len. The callback function will
840 * be called after period_len bytes have been transferred.
841 * @device_prep_interleaved_dma: Transfer expression in a generic way.
842 * @device_caps: May be used to override the generic DMA slave capabilities
843 * with per-channel specific ones
844 * @device_config: Pushes a new configuration to a channel, return 0 or an error
845 * code
846 * @device_pause: Pauses any transfer happening on a channel. Returns
847 * 0 or an error code
848 * @device_resume: Resumes any transfer on a channel previously
849 * paused. Returns 0 or an error code
850 * @device_terminate_all: Aborts all transfers on a channel. Returns 0
851 * or an error code
852 * @device_synchronize: Synchronizes the termination of a transfers to the
853 * current context.
854 * @device_tx_status: poll for transaction completion, the optional
855 * txstate parameter can be supplied with a pointer to get a
856 * struct with auxiliary transfer status information, otherwise the call
857 * will just return a simple status code
858 * @device_issue_pending: push pending transactions to hardware
859 * @device_release: called sometime atfer dma_async_device_unregister() is
860 * called and there are no further references to this structure. This
861 * must be implemented to free resources however many existing drivers
862 * do not and are therefore not safe to unbind while in use.
863 * @dbg_summary_show: optional routine to show contents in debugfs; default code
864 * will be used when this is omitted, but custom code can show extra,
865 * controller specific information.
866 * @dbg_dev_root: the root folder in debugfs for this device
867 */
868struct dma_device {
869 struct kref ref;
870 unsigned int chancnt;
871 unsigned int privatecnt;
872 struct list_head channels;
873 struct list_head global_node;
874 struct dma_filter filter;
875 dma_cap_mask_t cap_mask;
876 enum dma_desc_metadata_mode desc_metadata_modes;
877 unsigned short max_xor;
878 unsigned short max_pq;
879 enum dmaengine_alignment copy_align;
880 enum dmaengine_alignment xor_align;
881 enum dmaengine_alignment pq_align;
882 enum dmaengine_alignment fill_align;
883 #define DMA_HAS_PQ_CONTINUE (1 << 15)
884
885 int dev_id;
886 struct device *dev;
887 struct module *owner;
888 struct ida chan_ida;
889
890 u32 src_addr_widths;
891 u32 dst_addr_widths;
892 u32 directions;
893 u32 min_burst;
894 u32 max_burst;
895 u32 max_sg_burst;
896 bool descriptor_reuse;
897 enum dma_residue_granularity residue_granularity;
898
899 int (*device_alloc_chan_resources)(struct dma_chan *chan);
900 int (*device_router_config)(struct dma_chan *chan);
901 void (*device_free_chan_resources)(struct dma_chan *chan);
902
903 struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)(
904 struct dma_chan *chan, dma_addr_t dst, dma_addr_t src,
905 size_t len, unsigned long flags);
906 struct dma_async_tx_descriptor *(*device_prep_dma_xor)(
907 struct dma_chan *chan, dma_addr_t dst, dma_addr_t *src,
908 unsigned int src_cnt, size_t len, unsigned long flags);
909 struct dma_async_tx_descriptor *(*device_prep_dma_xor_val)(
910 struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt,
911 size_t len, enum sum_check_flags *result, unsigned long flags);
912 struct dma_async_tx_descriptor *(*device_prep_dma_pq)(
913 struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src,
914 unsigned int src_cnt, const unsigned char *scf,
915 size_t len, unsigned long flags);
916 struct dma_async_tx_descriptor *(*device_prep_dma_pq_val)(
917 struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src,
918 unsigned int src_cnt, const unsigned char *scf, size_t len,
919 enum sum_check_flags *pqres, unsigned long flags);
920 struct dma_async_tx_descriptor *(*device_prep_dma_memset)(
921 struct dma_chan *chan, dma_addr_t dest, int value, size_t len,
922 unsigned long flags);
923 struct dma_async_tx_descriptor *(*device_prep_dma_memset_sg)(
924 struct dma_chan *chan, struct scatterlist *sg,
925 unsigned int nents, int value, unsigned long flags);
926 struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)(
927 struct dma_chan *chan, unsigned long flags);
928
929 struct dma_async_tx_descriptor *(*device_prep_peripheral_dma_vec)(
930 struct dma_chan *chan, const struct dma_vec *vecs,
931 size_t nents, enum dma_transfer_direction direction,
932 unsigned long flags);
933 struct dma_async_tx_descriptor *(*device_prep_slave_sg)(
934 struct dma_chan *chan, struct scatterlist *sgl,
935 unsigned int sg_len, enum dma_transfer_direction direction,
936 unsigned long flags, void *context);
937 struct dma_async_tx_descriptor *(*device_prep_dma_cyclic)(
938 struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
939 size_t period_len, enum dma_transfer_direction direction,
940 unsigned long flags);
941 struct dma_async_tx_descriptor *(*device_prep_interleaved_dma)(
942 struct dma_chan *chan, struct dma_interleaved_template *xt,
943 unsigned long flags);
944
945 void (*device_caps)(struct dma_chan *chan, struct dma_slave_caps *caps);
946 int (*device_config)(struct dma_chan *chan, struct dma_slave_config *config);
947 int (*device_pause)(struct dma_chan *chan);
948 int (*device_resume)(struct dma_chan *chan);
949 int (*device_terminate_all)(struct dma_chan *chan);
950 void (*device_synchronize)(struct dma_chan *chan);
951
952 enum dma_status (*device_tx_status)(struct dma_chan *chan,
953 dma_cookie_t cookie,
954 struct dma_tx_state *txstate);
955 void (*device_issue_pending)(struct dma_chan *chan);
956 void (*device_release)(struct dma_device *dev);
957 /* debugfs support */
958 void (*dbg_summary_show)(struct seq_file *s, struct dma_device *dev);
959 struct dentry *dbg_dev_root;
960};
961
962static inline int dmaengine_slave_config(struct dma_chan *chan,
963 struct dma_slave_config *config)
964{
965 if (chan->device->device_config)
966 return chan->device->device_config(chan, config);
967
968 return -ENOSYS;
969}
970
971static inline bool is_slave_direction(enum dma_transfer_direction direction)
972{
973 return (direction == DMA_MEM_TO_DEV) || (direction == DMA_DEV_TO_MEM) ||
974 (direction == DMA_DEV_TO_DEV);
975}
976
977static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_single(
978 struct dma_chan *chan, dma_addr_t buf, size_t len,
979 enum dma_transfer_direction dir, unsigned long flags)
980{
981 struct scatterlist sg;
982 sg_init_table(&sg, 1);
983 sg_dma_address(&sg) = buf;
984 sg_dma_len(&sg) = len;
985
986 if (!chan || !chan->device || !chan->device->device_prep_slave_sg)
987 return NULL;
988
989 return chan->device->device_prep_slave_sg(chan, &sg, 1,
990 dir, flags, NULL);
991}
992
993/**
994 * dmaengine_prep_peripheral_dma_vec() - Prepare a DMA scatter-gather descriptor
995 * @chan: The channel to be used for this descriptor
996 * @vecs: The array of DMA vectors that should be transferred
997 * @nents: The number of DMA vectors in the array
998 * @dir: Specifies the direction of the data transfer
999 * @flags: DMA engine flags - DMA_PREP_REPEAT can be used to mark a cyclic
1000 * DMA transfer
1001 */
1002static inline struct dma_async_tx_descriptor *dmaengine_prep_peripheral_dma_vec(
1003 struct dma_chan *chan, const struct dma_vec *vecs, size_t nents,
1004 enum dma_transfer_direction dir, unsigned long flags)
1005{
1006 if (!chan || !chan->device || !chan->device->device_prep_peripheral_dma_vec)
1007 return NULL;
1008
1009 return chan->device->device_prep_peripheral_dma_vec(chan, vecs, nents,
1010 dir, flags);
1011}
1012
1013static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_sg(
1014 struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len,
1015 enum dma_transfer_direction dir, unsigned long flags)
1016{
1017 if (!chan || !chan->device || !chan->device->device_prep_slave_sg)
1018 return NULL;
1019
1020 return chan->device->device_prep_slave_sg(chan, sgl, sg_len,
1021 dir, flags, NULL);
1022}
1023
1024#ifdef CONFIG_RAPIDIO_DMA_ENGINE
1025struct rio_dma_ext;
1026static inline struct dma_async_tx_descriptor *dmaengine_prep_rio_sg(
1027 struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len,
1028 enum dma_transfer_direction dir, unsigned long flags,
1029 struct rio_dma_ext *rio_ext)
1030{
1031 if (!chan || !chan->device || !chan->device->device_prep_slave_sg)
1032 return NULL;
1033
1034 return chan->device->device_prep_slave_sg(chan, sgl, sg_len,
1035 dir, flags, rio_ext);
1036}
1037#endif
1038
1039static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_cyclic(
1040 struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
1041 size_t period_len, enum dma_transfer_direction dir,
1042 unsigned long flags)
1043{
1044 if (!chan || !chan->device || !chan->device->device_prep_dma_cyclic)
1045 return NULL;
1046
1047 return chan->device->device_prep_dma_cyclic(chan, buf_addr, buf_len,
1048 period_len, dir, flags);
1049}
1050
1051static inline struct dma_async_tx_descriptor *dmaengine_prep_interleaved_dma(
1052 struct dma_chan *chan, struct dma_interleaved_template *xt,
1053 unsigned long flags)
1054{
1055 if (!chan || !chan->device || !chan->device->device_prep_interleaved_dma)
1056 return NULL;
1057 if (flags & DMA_PREP_REPEAT &&
1058 !test_bit(DMA_REPEAT, chan->device->cap_mask.bits))
1059 return NULL;
1060
1061 return chan->device->device_prep_interleaved_dma(chan, xt, flags);
1062}
1063
1064/**
1065 * dmaengine_prep_dma_memset() - Prepare a DMA memset descriptor.
1066 * @chan: The channel to be used for this descriptor
1067 * @dest: Address of buffer to be set
1068 * @value: Treated as a single byte value that fills the destination buffer
1069 * @len: The total size of dest
1070 * @flags: DMA engine flags
1071 */
1072static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_memset(
1073 struct dma_chan *chan, dma_addr_t dest, int value, size_t len,
1074 unsigned long flags)
1075{
1076 if (!chan || !chan->device || !chan->device->device_prep_dma_memset)
1077 return NULL;
1078
1079 return chan->device->device_prep_dma_memset(chan, dest, value,
1080 len, flags);
1081}
1082
1083static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_memcpy(
1084 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
1085 size_t len, unsigned long flags)
1086{
1087 if (!chan || !chan->device || !chan->device->device_prep_dma_memcpy)
1088 return NULL;
1089
1090 return chan->device->device_prep_dma_memcpy(chan, dest, src,
1091 len, flags);
1092}
1093
1094static inline bool dmaengine_is_metadata_mode_supported(struct dma_chan *chan,
1095 enum dma_desc_metadata_mode mode)
1096{
1097 if (!chan)
1098 return false;
1099
1100 return !!(chan->device->desc_metadata_modes & mode);
1101}
1102
1103#ifdef CONFIG_DMA_ENGINE
1104int dmaengine_desc_attach_metadata(struct dma_async_tx_descriptor *desc,
1105 void *data, size_t len);
1106void *dmaengine_desc_get_metadata_ptr(struct dma_async_tx_descriptor *desc,
1107 size_t *payload_len, size_t *max_len);
1108int dmaengine_desc_set_metadata_len(struct dma_async_tx_descriptor *desc,
1109 size_t payload_len);
1110#else /* CONFIG_DMA_ENGINE */
1111static inline int dmaengine_desc_attach_metadata(
1112 struct dma_async_tx_descriptor *desc, void *data, size_t len)
1113{
1114 return -EINVAL;
1115}
1116static inline void *dmaengine_desc_get_metadata_ptr(
1117 struct dma_async_tx_descriptor *desc, size_t *payload_len,
1118 size_t *max_len)
1119{
1120 return NULL;
1121}
1122static inline int dmaengine_desc_set_metadata_len(
1123 struct dma_async_tx_descriptor *desc, size_t payload_len)
1124{
1125 return -EINVAL;
1126}
1127#endif /* CONFIG_DMA_ENGINE */
1128
1129/**
1130 * dmaengine_terminate_all() - Terminate all active DMA transfers
1131 * @chan: The channel for which to terminate the transfers
1132 *
1133 * This function is DEPRECATED use either dmaengine_terminate_sync() or
1134 * dmaengine_terminate_async() instead.
1135 */
1136static inline int dmaengine_terminate_all(struct dma_chan *chan)
1137{
1138 if (chan->device->device_terminate_all)
1139 return chan->device->device_terminate_all(chan);
1140
1141 return -ENOSYS;
1142}
1143
1144/**
1145 * dmaengine_terminate_async() - Terminate all active DMA transfers
1146 * @chan: The channel for which to terminate the transfers
1147 *
1148 * Calling this function will terminate all active and pending descriptors
1149 * that have previously been submitted to the channel. It is not guaranteed
1150 * though that the transfer for the active descriptor has stopped when the
1151 * function returns. Furthermore it is possible the complete callback of a
1152 * submitted transfer is still running when this function returns.
1153 *
1154 * dmaengine_synchronize() needs to be called before it is safe to free
1155 * any memory that is accessed by previously submitted descriptors or before
1156 * freeing any resources accessed from within the completion callback of any
1157 * previously submitted descriptors.
1158 *
1159 * This function can be called from atomic context as well as from within a
1160 * complete callback of a descriptor submitted on the same channel.
1161 *
1162 * If none of the two conditions above apply consider using
1163 * dmaengine_terminate_sync() instead.
1164 */
1165static inline int dmaengine_terminate_async(struct dma_chan *chan)
1166{
1167 if (chan->device->device_terminate_all)
1168 return chan->device->device_terminate_all(chan);
1169
1170 return -EINVAL;
1171}
1172
1173/**
1174 * dmaengine_synchronize() - Synchronize DMA channel termination
1175 * @chan: The channel to synchronize
1176 *
1177 * Synchronizes to the DMA channel termination to the current context. When this
1178 * function returns it is guaranteed that all transfers for previously issued
1179 * descriptors have stopped and it is safe to free the memory associated
1180 * with them. Furthermore it is guaranteed that all complete callback functions
1181 * for a previously submitted descriptor have finished running and it is safe to
1182 * free resources accessed from within the complete callbacks.
1183 *
1184 * The behavior of this function is undefined if dma_async_issue_pending() has
1185 * been called between dmaengine_terminate_async() and this function.
1186 *
1187 * This function must only be called from non-atomic context and must not be
1188 * called from within a complete callback of a descriptor submitted on the same
1189 * channel.
1190 */
1191static inline void dmaengine_synchronize(struct dma_chan *chan)
1192{
1193 might_sleep();
1194
1195 if (chan->device->device_synchronize)
1196 chan->device->device_synchronize(chan);
1197}
1198
1199/**
1200 * dmaengine_terminate_sync() - Terminate all active DMA transfers
1201 * @chan: The channel for which to terminate the transfers
1202 *
1203 * Calling this function will terminate all active and pending transfers
1204 * that have previously been submitted to the channel. It is similar to
1205 * dmaengine_terminate_async() but guarantees that the DMA transfer has actually
1206 * stopped and that all complete callbacks have finished running when the
1207 * function returns.
1208 *
1209 * This function must only be called from non-atomic context and must not be
1210 * called from within a complete callback of a descriptor submitted on the same
1211 * channel.
1212 */
1213static inline int dmaengine_terminate_sync(struct dma_chan *chan)
1214{
1215 int ret;
1216
1217 ret = dmaengine_terminate_async(chan);
1218 if (ret)
1219 return ret;
1220
1221 dmaengine_synchronize(chan);
1222
1223 return 0;
1224}
1225
1226static inline int dmaengine_pause(struct dma_chan *chan)
1227{
1228 if (chan->device->device_pause)
1229 return chan->device->device_pause(chan);
1230
1231 return -ENOSYS;
1232}
1233
1234static inline int dmaengine_resume(struct dma_chan *chan)
1235{
1236 if (chan->device->device_resume)
1237 return chan->device->device_resume(chan);
1238
1239 return -ENOSYS;
1240}
1241
1242static inline enum dma_status dmaengine_tx_status(struct dma_chan *chan,
1243 dma_cookie_t cookie, struct dma_tx_state *state)
1244{
1245 return chan->device->device_tx_status(chan, cookie, state);
1246}
1247
1248static inline dma_cookie_t dmaengine_submit(struct dma_async_tx_descriptor *desc)
1249{
1250 return desc->tx_submit(desc);
1251}
1252
1253static inline bool dmaengine_check_align(enum dmaengine_alignment align,
1254 size_t off1, size_t off2, size_t len)
1255{
1256 return !(((1 << align) - 1) & (off1 | off2 | len));
1257}
1258
1259static inline bool is_dma_copy_aligned(struct dma_device *dev, size_t off1,
1260 size_t off2, size_t len)
1261{
1262 return dmaengine_check_align(dev->copy_align, off1, off2, len);
1263}
1264
1265static inline bool is_dma_xor_aligned(struct dma_device *dev, size_t off1,
1266 size_t off2, size_t len)
1267{
1268 return dmaengine_check_align(dev->xor_align, off1, off2, len);
1269}
1270
1271static inline bool is_dma_pq_aligned(struct dma_device *dev, size_t off1,
1272 size_t off2, size_t len)
1273{
1274 return dmaengine_check_align(dev->pq_align, off1, off2, len);
1275}
1276
1277static inline bool is_dma_fill_aligned(struct dma_device *dev, size_t off1,
1278 size_t off2, size_t len)
1279{
1280 return dmaengine_check_align(dev->fill_align, off1, off2, len);
1281}
1282
1283static inline void
1284dma_set_maxpq(struct dma_device *dma, int maxpq, int has_pq_continue)
1285{
1286 dma->max_pq = maxpq;
1287 if (has_pq_continue)
1288 dma->max_pq |= DMA_HAS_PQ_CONTINUE;
1289}
1290
1291static inline bool dmaf_continue(enum dma_ctrl_flags flags)
1292{
1293 return (flags & DMA_PREP_CONTINUE) == DMA_PREP_CONTINUE;
1294}
1295
1296static inline bool dmaf_p_disabled_continue(enum dma_ctrl_flags flags)
1297{
1298 enum dma_ctrl_flags mask = DMA_PREP_CONTINUE | DMA_PREP_PQ_DISABLE_P;
1299
1300 return (flags & mask) == mask;
1301}
1302
1303static inline bool dma_dev_has_pq_continue(struct dma_device *dma)
1304{
1305 return (dma->max_pq & DMA_HAS_PQ_CONTINUE) == DMA_HAS_PQ_CONTINUE;
1306}
1307
1308static inline unsigned short dma_dev_to_maxpq(struct dma_device *dma)
1309{
1310 return dma->max_pq & ~DMA_HAS_PQ_CONTINUE;
1311}
1312
1313/* dma_maxpq - reduce maxpq in the face of continued operations
1314 * @dma - dma device with PQ capability
1315 * @flags - to check if DMA_PREP_CONTINUE and DMA_PREP_PQ_DISABLE_P are set
1316 *
1317 * When an engine does not support native continuation we need 3 extra
1318 * source slots to reuse P and Q with the following coefficients:
1319 * 1/ {00} * P : remove P from Q', but use it as a source for P'
1320 * 2/ {01} * Q : use Q to continue Q' calculation
1321 * 3/ {00} * Q : subtract Q from P' to cancel (2)
1322 *
1323 * In the case where P is disabled we only need 1 extra source:
1324 * 1/ {01} * Q : use Q to continue Q' calculation
1325 */
1326static inline int dma_maxpq(struct dma_device *dma, enum dma_ctrl_flags flags)
1327{
1328 if (dma_dev_has_pq_continue(dma) || !dmaf_continue(flags))
1329 return dma_dev_to_maxpq(dma);
1330 if (dmaf_p_disabled_continue(flags))
1331 return dma_dev_to_maxpq(dma) - 1;
1332 if (dmaf_continue(flags))
1333 return dma_dev_to_maxpq(dma) - 3;
1334 BUG();
1335}
1336
1337static inline size_t dmaengine_get_icg(bool inc, bool sgl, size_t icg,
1338 size_t dir_icg)
1339{
1340 if (inc) {
1341 if (dir_icg)
1342 return dir_icg;
1343 if (sgl)
1344 return icg;
1345 }
1346
1347 return 0;
1348}
1349
1350static inline size_t dmaengine_get_dst_icg(struct dma_interleaved_template *xt,
1351 struct data_chunk *chunk)
1352{
1353 return dmaengine_get_icg(xt->dst_inc, xt->dst_sgl,
1354 chunk->icg, chunk->dst_icg);
1355}
1356
1357static inline size_t dmaengine_get_src_icg(struct dma_interleaved_template *xt,
1358 struct data_chunk *chunk)
1359{
1360 return dmaengine_get_icg(xt->src_inc, xt->src_sgl,
1361 chunk->icg, chunk->src_icg);
1362}
1363
1364/* --- public DMA engine API --- */
1365
1366#ifdef CONFIG_DMA_ENGINE
1367void dmaengine_get(void);
1368void dmaengine_put(void);
1369#else
1370static inline void dmaengine_get(void)
1371{
1372}
1373static inline void dmaengine_put(void)
1374{
1375}
1376#endif
1377
1378#ifdef CONFIG_ASYNC_TX_DMA
1379#define async_dmaengine_get() dmaengine_get()
1380#define async_dmaengine_put() dmaengine_put()
1381#ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
1382#define async_dma_find_channel(type) dma_find_channel(DMA_ASYNC_TX)
1383#else
1384#define async_dma_find_channel(type) dma_find_channel(type)
1385#endif /* CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH */
1386#else
1387static inline void async_dmaengine_get(void)
1388{
1389}
1390static inline void async_dmaengine_put(void)
1391{
1392}
1393static inline struct dma_chan *
1394async_dma_find_channel(enum dma_transaction_type type)
1395{
1396 return NULL;
1397}
1398#endif /* CONFIG_ASYNC_TX_DMA */
1399void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
1400 struct dma_chan *chan);
1401
1402static inline void async_tx_ack(struct dma_async_tx_descriptor *tx)
1403{
1404 tx->flags |= DMA_CTRL_ACK;
1405}
1406
1407static inline void async_tx_clear_ack(struct dma_async_tx_descriptor *tx)
1408{
1409 tx->flags &= ~DMA_CTRL_ACK;
1410}
1411
1412static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx)
1413{
1414 return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK;
1415}
1416
1417#define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask))
1418static inline void
1419__dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
1420{
1421 set_bit(tx_type, dstp->bits);
1422}
1423
1424#define dma_cap_clear(tx, mask) __dma_cap_clear((tx), &(mask))
1425static inline void
1426__dma_cap_clear(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
1427{
1428 clear_bit(tx_type, dstp->bits);
1429}
1430
1431#define dma_cap_zero(mask) __dma_cap_zero(&(mask))
1432static inline void __dma_cap_zero(dma_cap_mask_t *dstp)
1433{
1434 bitmap_zero(dstp->bits, DMA_TX_TYPE_END);
1435}
1436
1437#define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask))
1438static inline int
1439__dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp)
1440{
1441 return test_bit(tx_type, srcp->bits);
1442}
1443
1444#define for_each_dma_cap_mask(cap, mask) \
1445 for_each_set_bit(cap, mask.bits, DMA_TX_TYPE_END)
1446
1447/**
1448 * dma_async_issue_pending - flush pending transactions to HW
1449 * @chan: target DMA channel
1450 *
1451 * This allows drivers to push copies to HW in batches,
1452 * reducing MMIO writes where possible.
1453 */
1454static inline void dma_async_issue_pending(struct dma_chan *chan)
1455{
1456 chan->device->device_issue_pending(chan);
1457}
1458
1459/**
1460 * dma_async_is_tx_complete - poll for transaction completion
1461 * @chan: DMA channel
1462 * @cookie: transaction identifier to check status of
1463 * @last: returns last completed cookie, can be NULL
1464 * @used: returns last issued cookie, can be NULL
1465 *
1466 * If @last and @used are passed in, upon return they reflect the driver
1467 * internal state and can be used with dma_async_is_complete() to check
1468 * the status of multiple cookies without re-checking hardware state.
1469 */
1470static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan,
1471 dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used)
1472{
1473 struct dma_tx_state state;
1474 enum dma_status status;
1475
1476 status = chan->device->device_tx_status(chan, cookie, &state);
1477 if (last)
1478 *last = state.last;
1479 if (used)
1480 *used = state.used;
1481 return status;
1482}
1483
1484/**
1485 * dma_async_is_complete - test a cookie against chan state
1486 * @cookie: transaction identifier to test status of
1487 * @last_complete: last know completed transaction
1488 * @last_used: last cookie value handed out
1489 *
1490 * dma_async_is_complete() is used in dma_async_is_tx_complete()
1491 * the test logic is separated for lightweight testing of multiple cookies
1492 */
1493static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie,
1494 dma_cookie_t last_complete, dma_cookie_t last_used)
1495{
1496 if (last_complete <= last_used) {
1497 if ((cookie <= last_complete) || (cookie > last_used))
1498 return DMA_COMPLETE;
1499 } else {
1500 if ((cookie <= last_complete) && (cookie > last_used))
1501 return DMA_COMPLETE;
1502 }
1503 return DMA_IN_PROGRESS;
1504}
1505
1506static inline void
1507dma_set_tx_state(struct dma_tx_state *st, dma_cookie_t last, dma_cookie_t used, u32 residue)
1508{
1509 if (!st)
1510 return;
1511
1512 st->last = last;
1513 st->used = used;
1514 st->residue = residue;
1515}
1516
1517#ifdef CONFIG_DMA_ENGINE
1518struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type);
1519enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie);
1520enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx);
1521void dma_issue_pending_all(void);
1522struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
1523 dma_filter_fn fn, void *fn_param,
1524 struct device_node *np);
1525
1526struct dma_chan *dma_request_chan(struct device *dev, const char *name);
1527struct dma_chan *dma_request_chan_by_mask(const dma_cap_mask_t *mask);
1528struct dma_chan *devm_dma_request_chan(struct device *dev, const char *name);
1529
1530void dma_release_channel(struct dma_chan *chan);
1531int dma_get_slave_caps(struct dma_chan *chan, struct dma_slave_caps *caps);
1532#else
1533static inline struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type)
1534{
1535 return NULL;
1536}
1537static inline enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie)
1538{
1539 return DMA_COMPLETE;
1540}
1541static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
1542{
1543 return DMA_COMPLETE;
1544}
1545static inline void dma_issue_pending_all(void)
1546{
1547}
1548static inline struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
1549 dma_filter_fn fn,
1550 void *fn_param,
1551 struct device_node *np)
1552{
1553 return NULL;
1554}
1555static inline struct dma_chan *dma_request_chan(struct device *dev,
1556 const char *name)
1557{
1558 return ERR_PTR(-ENODEV);
1559}
1560static inline struct dma_chan *dma_request_chan_by_mask(
1561 const dma_cap_mask_t *mask)
1562{
1563 return ERR_PTR(-ENODEV);
1564}
1565
1566static inline struct dma_chan *devm_dma_request_chan(struct device *dev, const char *name)
1567{
1568 return ERR_PTR(-ENODEV);
1569}
1570
1571static inline void dma_release_channel(struct dma_chan *chan)
1572{
1573}
1574static inline int dma_get_slave_caps(struct dma_chan *chan,
1575 struct dma_slave_caps *caps)
1576{
1577 return -ENXIO;
1578}
1579#endif
1580
1581static inline int dmaengine_desc_set_reuse(struct dma_async_tx_descriptor *tx)
1582{
1583 struct dma_slave_caps caps;
1584 int ret;
1585
1586 ret = dma_get_slave_caps(tx->chan, &caps);
1587 if (ret)
1588 return ret;
1589
1590 if (!caps.descriptor_reuse)
1591 return -EPERM;
1592
1593 tx->flags |= DMA_CTRL_REUSE;
1594 return 0;
1595}
1596
1597static inline void dmaengine_desc_clear_reuse(struct dma_async_tx_descriptor *tx)
1598{
1599 tx->flags &= ~DMA_CTRL_REUSE;
1600}
1601
1602static inline bool dmaengine_desc_test_reuse(struct dma_async_tx_descriptor *tx)
1603{
1604 return (tx->flags & DMA_CTRL_REUSE) == DMA_CTRL_REUSE;
1605}
1606
1607static inline int dmaengine_desc_free(struct dma_async_tx_descriptor *desc)
1608{
1609 /* this is supported for reusable desc, so check that */
1610 if (!dmaengine_desc_test_reuse(desc))
1611 return -EPERM;
1612
1613 return desc->desc_free(desc);
1614}
1615
1616/* --- DMA device --- */
1617
1618int dma_async_device_register(struct dma_device *device);
1619int dmaenginem_async_device_register(struct dma_device *device);
1620void dma_async_device_unregister(struct dma_device *device);
1621int dma_async_device_channel_register(struct dma_device *device,
1622 struct dma_chan *chan,
1623 const char *name);
1624void dma_async_device_channel_unregister(struct dma_device *device,
1625 struct dma_chan *chan);
1626void dma_run_dependencies(struct dma_async_tx_descriptor *tx);
1627#define dma_request_channel(mask, x, y) \
1628 __dma_request_channel(&(mask), x, y, NULL)
1629
1630/* Deprecated, please use dma_request_chan() directly */
1631static inline struct dma_chan * __deprecated
1632dma_request_slave_channel(struct device *dev, const char *name)
1633{
1634 struct dma_chan *ch = dma_request_chan(dev, name);
1635
1636 return IS_ERR(ch) ? NULL : ch;
1637}
1638
1639static inline struct dma_chan
1640*dma_request_slave_channel_compat(const dma_cap_mask_t mask,
1641 dma_filter_fn fn, void *fn_param,
1642 struct device *dev, const char *name)
1643{
1644 struct dma_chan *chan;
1645
1646 chan = dma_request_chan(dev, name);
1647 if (!IS_ERR(chan))
1648 return chan;
1649
1650 if (!fn || !fn_param)
1651 return NULL;
1652
1653 return dma_request_channel(mask, fn, fn_param);
1654}
1655
1656static inline char *
1657dmaengine_get_direction_text(enum dma_transfer_direction dir)
1658{
1659 switch (dir) {
1660 case DMA_DEV_TO_MEM:
1661 return "DEV_TO_MEM";
1662 case DMA_MEM_TO_DEV:
1663 return "MEM_TO_DEV";
1664 case DMA_MEM_TO_MEM:
1665 return "MEM_TO_MEM";
1666 case DMA_DEV_TO_DEV:
1667 return "DEV_TO_DEV";
1668 default:
1669 return "invalid";
1670 }
1671}
1672
1673static inline struct device *dmaengine_get_dma_device(struct dma_chan *chan)
1674{
1675 if (chan->dev->chan_dma_dev)
1676 return &chan->dev->device;
1677
1678 return chan->device->dev;
1679}
1680
1681#endif /* DMAENGINE_H */