| 1 |
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| 2 | #ifndef _LINUX_PGTABLE_H
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| 3 | #define _LINUX_PGTABLE_H
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| 4 |
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| 5 | #include <linux/pfn.h>
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| 6 | #include <asm/pgtable.h>
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| 7 |
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| 8 | #define PMD_ORDER (PMD_SHIFT - PAGE_SHIFT)
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| 9 | #define PUD_ORDER (PUD_SHIFT - PAGE_SHIFT)
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| 10 |
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| 11 | #ifndef __ASSEMBLY__
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| 12 | #ifdef CONFIG_MMU
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| 13 |
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| 14 | #include <linux/mm_types.h>
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| 15 | #include <linux/bug.h>
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| 16 | #include <linux/errno.h>
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| 17 | #include <asm-generic/pgtable_uffd.h>
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| 18 | #include <linux/page_table_check.h>
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| 19 |
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| 20 | #if 5 - defined(__PAGETABLE_P4D_FOLDED) - defined(__PAGETABLE_PUD_FOLDED) - \
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| 21 | defined(__PAGETABLE_PMD_FOLDED) != CONFIG_PGTABLE_LEVELS
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| 22 | #error CONFIG_PGTABLE_LEVELS is not consistent with __PAGETABLE_{P4D,PUD,PMD}_FOLDED
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| 23 | #endif
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| 24 |
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| 25 | |
| 26 | * This defines the generic helper for accessing PMD page
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| 27 | * table page. Although platforms can still override this
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| 28 | * via their respective <asm/pgtable.h>.
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| 29 |
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| 30 | #ifndef pmd_pgtable
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| 31 | #define pmd_pgtable(pmd) pmd_page(pmd)
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| 32 | #endif
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| 33 |
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| 34 | #define pmd_folio(pmd) page_folio(pmd_page(pmd))
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| 35 |
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| 36 | |
| 37 | * A page table page can be thought of an array like this: pXd_t[PTRS_PER_PxD]
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| 38 | *
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| 39 | * The pXx_index() functions return the index of the entry in the page
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| 40 | * table page which would control the given virtual address
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| 41 | *
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| 42 | * As these functions may be used by the same code for different levels of
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| 43 | * the page table folding, they are always available, regardless of
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| 44 | * CONFIG_PGTABLE_LEVELS value. For the folded levels they simply return 0
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| 45 | * because in such cases PTRS_PER_PxD equals 1.
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| 46 |
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| 47 |
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| 48 | static inline unsigned long pte_index(unsigned long address)
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| 49 | {
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| 50 | return (address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1);
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| 51 | }
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| 52 |
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| 53 | #ifndef pmd_index
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| 54 | static inline unsigned long pmd_index(unsigned long address)
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| 55 | {
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| 56 | return (address >> PMD_SHIFT) & (PTRS_PER_PMD - 1);
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| 57 | }
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| 58 | #define pmd_index pmd_index
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| 59 | #endif
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| 60 |
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| 61 | #ifndef pud_index
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| 62 | static inline unsigned long pud_index(unsigned long address)
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| 63 | {
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| 64 | return (address >> PUD_SHIFT) & (PTRS_PER_PUD - 1);
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| 65 | }
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| 66 | #define pud_index pud_index
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| 67 | #endif
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| 68 |
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| 69 | #ifndef pgd_index
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| 70 |
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| 71 | #define pgd_index(a) (((a) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
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| 72 | #endif
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| 73 |
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| 74 | #ifndef kernel_pte_init
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| 75 | static inline void kernel_pte_init(void *addr)
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| 76 | {
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| 77 | }
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| 78 | #define kernel_pte_init kernel_pte_init
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| 79 | #endif
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| 80 |
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| 81 | #ifndef pmd_init
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| 82 | static inline void pmd_init(void *addr)
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| 83 | {
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| 84 | }
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| 85 | #define pmd_init pmd_init
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| 86 | #endif
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| 87 |
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| 88 | #ifndef pud_init
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| 89 | static inline void pud_init(void *addr)
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| 90 | {
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| 91 | }
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| 92 | #define pud_init pud_init
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| 93 | #endif
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| 94 |
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| 95 | #ifndef pte_offset_kernel
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| 96 | static inline pte_t *pte_offset_kernel(pmd_t *pmd, unsigned long address)
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| 97 | {
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| 98 | return (pte_t *)pmd_page_vaddr(*pmd) + pte_index(address);
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| 99 | }
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| 100 | #define pte_offset_kernel pte_offset_kernel
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| 101 | #endif
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| 102 |
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| 103 | #ifdef CONFIG_HIGHPTE
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| 104 | #define __pte_map(pmd, address) \
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| 105 | ((pte_t *)kmap_local_page(pmd_page(*(pmd))) + pte_index((address)))
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| 106 | #define pte_unmap(pte) do { \
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| 107 | kunmap_local((pte)); \
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| 108 | rcu_read_unlock(); \
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| 109 | } while (0)
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| 110 | #else
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| 111 | static inline pte_t *__pte_map(pmd_t *pmd, unsigned long address)
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| 112 | {
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| 113 | return pte_offset_kernel(pmd, address);
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| 114 | }
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| 115 | static inline void pte_unmap(pte_t *pte)
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| 116 | {
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| 117 | rcu_read_unlock();
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| 118 | }
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| 119 | #endif
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| 120 |
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| 121 | void pte_free_defer(struct mm_struct *mm, pgtable_t pgtable);
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| 122 |
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| 123 |
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| 124 | #ifndef pmd_offset
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| 125 | static inline pmd_t *pmd_offset(pud_t *pud, unsigned long address)
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| 126 | {
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| 127 | return pud_pgtable(*pud) + pmd_index(address);
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| 128 | }
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| 129 | #define pmd_offset pmd_offset
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| 130 | #endif
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| 131 |
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| 132 | #ifndef pud_offset
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| 133 | static inline pud_t *pud_offset(p4d_t *p4d, unsigned long address)
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| 134 | {
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| 135 | return p4d_pgtable(*p4d) + pud_index(address);
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| 136 | }
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| 137 | #define pud_offset pud_offset
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| 138 | #endif
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| 139 |
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| 140 | static inline pgd_t *pgd_offset_pgd(pgd_t *pgd, unsigned long address)
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| 141 | {
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| 142 | return (pgd + pgd_index(address));
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| 143 | };
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| 144 |
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| 145 | |
| 146 | * a shortcut to get a pgd_t in a given mm
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| 147 |
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| 148 | #ifndef pgd_offset
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| 149 | #define pgd_offset(mm, address) pgd_offset_pgd((mm)->pgd, (address))
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| 150 | #endif
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| 151 |
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| 152 | |
| 153 | * a shortcut which implies the use of the kernel's pgd, instead
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| 154 | * of a process's
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| 155 |
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| 156 | #define pgd_offset_k(address) pgd_offset(&init_mm, (address))
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| 157 |
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| 158 | |
| 159 | * In many cases it is known that a virtual address is mapped at PMD or PTE
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| 160 | * level, so instead of traversing all the page table levels, we can get a
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| 161 | * pointer to the PMD entry in user or kernel page table or translate a virtual
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| 162 | * address to the pointer in the PTE in the kernel page tables with simple
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| 163 | * helpers.
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| 164 |
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| 165 | static inline pmd_t *pmd_off(struct mm_struct *mm, unsigned long va)
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| 166 | {
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| 167 | return pmd_offset(pud_offset(p4d_offset(pgd_offset(mm, va), va), va), va);
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| 168 | }
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| 169 |
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| 170 | static inline pmd_t *pmd_off_k(unsigned long va)
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| 171 | {
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| 172 | return pmd_offset(pud_offset(p4d_offset(pgd_offset_k(va), va), va), va);
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| 173 | }
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| 174 |
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| 175 | static inline pte_t *virt_to_kpte(unsigned long vaddr)
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| 176 | {
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| 177 | pmd_t *pmd = pmd_off_k(vaddr);
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| 178 |
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| 179 | return pmd_none(*pmd) ? NULL : pte_offset_kernel(pmd, vaddr);
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| 180 | }
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| 181 |
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| 182 | #ifndef pmd_young
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| 183 | static inline int pmd_young(pmd_t pmd)
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| 184 | {
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| 185 | return 0;
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| 186 | }
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| 187 | #endif
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| 188 |
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| 189 | #ifndef pmd_dirty
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| 190 | static inline int pmd_dirty(pmd_t pmd)
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| 191 | {
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| 192 | return 0;
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| 193 | }
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| 194 | #endif
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| 195 |
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| 196 | |
| 197 | * A facility to provide lazy MMU batching. This allows PTE updates and
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| 198 | * page invalidations to be delayed until a call to leave lazy MMU mode
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| 199 | * is issued. Some architectures may benefit from doing this, and it is
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| 200 | * beneficial for both shadow and direct mode hypervisors, which may batch
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| 201 | * the PTE updates which happen during this window. Note that using this
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| 202 | * interface requires that read hazards be removed from the code. A read
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| 203 | * hazard could result in the direct mode hypervisor case, since the actual
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| 204 | * write to the page tables may not yet have taken place, so reads though
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| 205 | * a raw PTE pointer after it has been modified are not guaranteed to be
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| 206 | * up to date.
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| 207 | *
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| 208 | * In the general case, no lock is guaranteed to be held between entry and exit
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| 209 | * of the lazy mode. (In practice, for user PTE updates, the appropriate page
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| 210 | * table lock(s) are held, but for kernel PTE updates, no lock is held).
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| 211 | * The implementation must therefore assume preemption may be enabled upon
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| 212 | * entry to the mode and cpu migration is possible; it must take steps to be
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| 213 | * robust against this. An implementation may handle this by disabling
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| 214 | * preemption, as a consequence generic code may not sleep while the lazy MMU
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| 215 | * mode is active.
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| 216 | *
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| 217 | * The mode is disabled in interrupt context and calls to the lazy_mmu API have
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| 218 | * no effect.
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| 219 | *
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| 220 | * The lazy MMU mode is enabled for a given block of code using:
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| 221 | *
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| 222 | * lazy_mmu_mode_enable();
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| 223 | * <code>
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| 224 | * lazy_mmu_mode_disable();
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| 225 | *
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| 226 | * Nesting is permitted: <code> may itself use an enable()/disable() pair.
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| 227 | * A nested call to enable() has no functional effect; however disable() causes
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| 228 | * any batched architectural state to be flushed regardless of nesting. After a
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| 229 | * call to disable(), the caller can therefore rely on all previous page table
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| 230 | * modifications to have taken effect, but the lazy MMU mode may still be
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| 231 | * enabled.
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| 232 | *
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| 233 | * In certain cases, it may be desirable to temporarily pause the lazy MMU mode.
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| 234 | * This can be done using:
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| 235 | *
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| 236 | * lazy_mmu_mode_pause();
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| 237 | * <code>
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| 238 | * lazy_mmu_mode_resume();
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| 239 | *
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| 240 | * pause() ensures that the mode is exited regardless of the nesting level;
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| 241 | * resume() re-enters the mode at the same nesting level. Any call to the
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| 242 | * lazy_mmu_mode_* API between those two calls has no effect. In particular,
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| 243 | * this means that pause()/resume() pairs may nest.
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| 244 | *
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| 245 | * is_lazy_mmu_mode_active() can be used to check whether the lazy MMU mode is
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| 246 | * currently enabled.
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| 247 |
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| 248 | #ifdef CONFIG_ARCH_HAS_LAZY_MMU_MODE
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| 249 | |
| 250 | * lazy_mmu_mode_enable() - Enable the lazy MMU mode.
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| 251 | *
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| 252 | * Enters a new lazy MMU mode section; if the mode was not already enabled,
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| 253 | * enables it and calls arch_enter_lazy_mmu_mode().
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| 254 | *
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| 255 | * Must be paired with a call to lazy_mmu_mode_disable().
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| 256 | *
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| 257 | * Has no effect if called:
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| 258 | * - While paused - see lazy_mmu_mode_pause()
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| 259 | * - In interrupt context
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| 260 |
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| 261 | static inline void lazy_mmu_mode_enable(void)
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| 262 | {
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| 263 | struct lazy_mmu_state *state = ¤t->lazy_mmu_state;
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| 264 |
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| 265 | if (in_interrupt() || state->pause_count > 0)
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| 266 | return;
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| 267 |
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| 268 | VM_WARN_ON_ONCE(state->enable_count == U8_MAX);
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| 269 |
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| 270 | if (state->enable_count++ == 0)
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| 271 | arch_enter_lazy_mmu_mode();
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| 272 | }
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| 273 |
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| 274 | |
| 275 | * lazy_mmu_mode_disable() - Disable the lazy MMU mode.
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| 276 | *
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| 277 | * Exits the current lazy MMU mode section. If it is the outermost section,
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| 278 | * disables the mode and calls arch_leave_lazy_mmu_mode(). Otherwise (nested
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| 279 | * section), calls arch_flush_lazy_mmu_mode().
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| 280 | *
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| 281 | * Must match a call to lazy_mmu_mode_enable().
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| 282 | *
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| 283 | * Has no effect if called:
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| 284 | * - While paused - see lazy_mmu_mode_pause()
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| 285 | * - In interrupt context
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| 286 |
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| 287 | static inline void lazy_mmu_mode_disable(void)
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| 288 | {
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| 289 | struct lazy_mmu_state *state = ¤t->lazy_mmu_state;
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| 290 |
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| 291 | if (in_interrupt() || state->pause_count > 0)
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| 292 | return;
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| 293 |
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| 294 | VM_WARN_ON_ONCE(state->enable_count == 0);
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| 295 |
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| 296 | if (--state->enable_count == 0)
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| 297 | arch_leave_lazy_mmu_mode();
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| 298 | else
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| 299 | arch_flush_lazy_mmu_mode();
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| 300 |
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| 301 | }
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| 302 |
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| 303 | |
| 304 | * __task_lazy_mmu_mode_pause() - Pause the lazy MMU mode for a task.
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| 305 | * @tsk: The task to check.
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| 306 | *
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| 307 | * Pauses the lazy MMU mode of @tsk.
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| 308 | *
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| 309 | * This function only operates on the state saved in task_struct; to pause
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| 310 | * current lazy_mmu_mode_pause() should be used instead.
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| 311 | *
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| 312 | * This function is intended for architectures that implement the lazy MMU
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| 313 | * mode; it must not be called from generic code.
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| 314 |
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| 315 | static inline void __task_lazy_mmu_mode_pause(struct task_struct *tsk)
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| 316 | {
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| 317 | struct lazy_mmu_state *state = &tsk->lazy_mmu_state;
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| 318 |
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| 319 | VM_WARN_ON_ONCE(state->pause_count == U8_MAX);
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| 320 |
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| 321 | if (state->pause_count++ == 0 && state->enable_count > 0)
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| 322 | arch_leave_lazy_mmu_mode();
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| 323 | }
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| 324 |
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| 325 | |
| 326 | * lazy_mmu_mode_pause() - Pause the lazy MMU mode.
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| 327 | *
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| 328 | * Pauses the lazy MMU mode; if it is currently active, disables it and calls
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| 329 | * arch_leave_lazy_mmu_mode().
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| 330 | *
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| 331 | * Must be paired with a call to lazy_mmu_mode_resume(). Calls to the
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| 332 | * lazy_mmu_mode_* API have no effect until the matching resume() call.
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| 333 | *
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| 334 | * Has no effect if called:
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| 335 | * - While paused (inside another pause()/resume() pair)
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| 336 | * - In interrupt context
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| 337 |
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| 338 | static inline void lazy_mmu_mode_pause(void)
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| 339 | {
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| 340 | if (in_interrupt())
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| 341 | return;
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| 342 |
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| 343 | __task_lazy_mmu_mode_pause(current);
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| 344 | }
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| 345 |
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| 346 | |
| 347 | * __task_lazy_mmu_mode_resume() - Resume the lazy MMU mode for a task.
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| 348 | * @tsk: The task to check.
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| 349 | *
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| 350 | * Resumes the lazy MMU mode of @tsk.
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| 351 | *
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| 352 | * This function only operates on the state saved in task_struct; to resume
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| 353 | * current lazy_mmu_mode_resume() should be used instead.
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| 354 | *
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| 355 | * This function is intended for architectures that implement the lazy MMU
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| 356 | * mode; it must not be called from generic code.
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| 357 |
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| 358 | static inline void __task_lazy_mmu_mode_resume(struct task_struct *tsk)
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| 359 | {
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| 360 | struct lazy_mmu_state *state = &tsk->lazy_mmu_state;
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| 361 |
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| 362 | VM_WARN_ON_ONCE(state->pause_count == 0);
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| 363 |
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| 364 | if (--state->pause_count == 0 && state->enable_count > 0)
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| 365 | arch_enter_lazy_mmu_mode();
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| 366 | }
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| 367 |
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| 368 | |
| 369 | * lazy_mmu_mode_resume() - Resume the lazy MMU mode.
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| 370 | *
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| 371 | * Resumes the lazy MMU mode; if it was active at the point where the matching
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| 372 | * call to lazy_mmu_mode_pause() was made, re-enables it and calls
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| 373 | * arch_enter_lazy_mmu_mode().
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| 374 | *
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| 375 | * Must match a call to lazy_mmu_mode_pause().
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| 376 | *
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| 377 | * Has no effect if called:
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| 378 | * - While paused (inside another pause()/resume() pair)
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| 379 | * - In interrupt context
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| 380 |
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| 381 | static inline void lazy_mmu_mode_resume(void)
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| 382 | {
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| 383 | if (in_interrupt())
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| 384 | return;
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| 385 |
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| 386 | __task_lazy_mmu_mode_resume(current);
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| 387 | }
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| 388 | #else
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| 389 | static inline void lazy_mmu_mode_enable(void) {}
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| 390 | static inline void lazy_mmu_mode_disable(void) {}
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| 391 | static inline void lazy_mmu_mode_pause(void) {}
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| 392 | static inline void lazy_mmu_mode_resume(void) {}
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| 393 | #endif
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| 394 |
|
| 395 | #ifndef pte_batch_hint
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| 396 | |
| 397 | * pte_batch_hint - Number of pages that can be added to batch without scanning.
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| 398 | * @ptep: Page table pointer for the entry.
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| 399 | * @pte: Page table entry.
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| 400 | *
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| 401 | * Some architectures know that a set of contiguous ptes all map the same
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| 402 | * contiguous memory with the same permissions. In this case, it can provide a
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| 403 | * hint to aid pte batching without the core code needing to scan every pte.
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| 404 | *
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| 405 | * An architecture implementation may ignore the PTE accessed state. Further,
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| 406 | * the dirty state must apply atomically to all the PTEs described by the hint.
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| 407 | *
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| 408 | * May be overridden by the architecture, else pte_batch_hint is always 1.
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| 409 |
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| 410 | static inline unsigned int pte_batch_hint(pte_t *ptep, pte_t pte)
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| 411 | {
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| 412 | return 1;
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| 413 | }
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| 414 | #endif
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| 415 |
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| 416 | #ifndef pte_advance_pfn
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| 417 | static inline pte_t pte_advance_pfn(pte_t pte, unsigned long nr)
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| 418 | {
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| 419 | return __pte(pte_val(pte) + (nr << PFN_PTE_SHIFT));
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| 420 | }
|
| 421 | #endif
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| 422 |
|
| 423 | #define pte_next_pfn(pte) pte_advance_pfn(pte, 1)
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| 424 |
|
| 425 | #ifndef set_ptes
|
| 426 | |
| 427 | * set_ptes - Map consecutive pages to a contiguous range of addresses.
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| 428 | * @mm: Address space to map the pages into.
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| 429 | * @addr: Address to map the first page at.
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| 430 | * @ptep: Page table pointer for the first entry.
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| 431 | * @pte: Page table entry for the first page.
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| 432 | * @nr: Number of pages to map.
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| 433 | *
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| 434 | * When nr==1, initial state of pte may be present or not present, and new state
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| 435 | * may be present or not present. When nr>1, initial state of all ptes must be
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| 436 | * not present, and new state must be present.
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| 437 | *
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| 438 | * May be overridden by the architecture, or the architecture can define
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| 439 | * set_pte() and PFN_PTE_SHIFT.
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| 440 | *
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| 441 | * Context: The caller holds the page table lock. The pages all belong
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| 442 | * to the same folio. The PTEs are all in the same PMD.
|
| 443 |
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| 444 | static inline void set_ptes(struct mm_struct *mm, unsigned long addr,
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| 445 | pte_t *ptep, pte_t pte, unsigned int nr)
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| 446 | {
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| 447 | page_table_check_ptes_set(mm, addr, ptep, pte, nr);
|
| 448 |
|
| 449 | for (;;) {
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| 450 | set_pte(ptep, pte);
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| 451 | if (--nr == 0)
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| 452 | break;
|
| 453 | ptep++;
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| 454 | pte = pte_next_pfn(pte);
|
| 455 | }
|
| 456 | }
|
| 457 | #endif
|
| 458 | #define set_pte_at(mm, addr, ptep, pte) set_ptes(mm, addr, ptep, pte, 1)
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| 459 |
|
| 460 | #ifndef __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
|
| 461 | extern int ptep_set_access_flags(struct vm_area_struct *vma,
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| 462 | unsigned long address, pte_t *ptep,
|
| 463 | pte_t entry, int dirty);
|
| 464 | #endif
|
| 465 |
|
| 466 | #ifndef __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS
|
| 467 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE
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| 468 | extern int pmdp_set_access_flags(struct vm_area_struct *vma,
|
| 469 | unsigned long address, pmd_t *pmdp,
|
| 470 | pmd_t entry, int dirty);
|
| 471 | extern int pudp_set_access_flags(struct vm_area_struct *vma,
|
| 472 | unsigned long address, pud_t *pudp,
|
| 473 | pud_t entry, int dirty);
|
| 474 | #else
|
| 475 | static inline int pmdp_set_access_flags(struct vm_area_struct *vma,
|
| 476 | unsigned long address, pmd_t *pmdp,
|
| 477 | pmd_t entry, int dirty)
|
| 478 | {
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| 479 | BUILD_BUG();
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| 480 | return 0;
|
| 481 | }
|
| 482 | static inline int pudp_set_access_flags(struct vm_area_struct *vma,
|
| 483 | unsigned long address, pud_t *pudp,
|
| 484 | pud_t entry, int dirty)
|
| 485 | {
|
| 486 | BUILD_BUG();
|
| 487 | return 0;
|
| 488 | }
|
| 489 | #endif
|
| 490 | #endif
|
| 491 |
|
| 492 | #ifndef ptep_get
|
| 493 | static inline pte_t ptep_get(pte_t *ptep)
|
| 494 | {
|
| 495 | return READ_ONCE(*ptep);
|
| 496 | }
|
| 497 | #endif
|
| 498 |
|
| 499 | #ifndef pmdp_get
|
| 500 | static inline pmd_t pmdp_get(pmd_t *pmdp)
|
| 501 | {
|
| 502 | return READ_ONCE(*pmdp);
|
| 503 | }
|
| 504 | #endif
|
| 505 |
|
| 506 | #ifndef pudp_get
|
| 507 | static inline pud_t pudp_get(pud_t *pudp)
|
| 508 | {
|
| 509 | return READ_ONCE(*pudp);
|
| 510 | }
|
| 511 | #endif
|
| 512 |
|
| 513 | #ifndef p4dp_get
|
| 514 | static inline p4d_t p4dp_get(p4d_t *p4dp)
|
| 515 | {
|
| 516 | return READ_ONCE(*p4dp);
|
| 517 | }
|
| 518 | #endif
|
| 519 |
|
| 520 | #ifndef pgdp_get
|
| 521 | static inline pgd_t pgdp_get(pgd_t *pgdp)
|
| 522 | {
|
| 523 | return READ_ONCE(*pgdp);
|
| 524 | }
|
| 525 | #endif
|
| 526 |
|
| 527 | #ifndef __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
|
| 528 | static inline bool ptep_test_and_clear_young(struct vm_area_struct *vma,
|
| 529 | unsigned long address, pte_t *ptep)
|
| 530 | {
|
| 531 | pte_t pte = ptep_get(ptep);
|
| 532 | bool young = true;
|
| 533 |
|
| 534 | if (!pte_young(pte))
|
| 535 | young = false;
|
| 536 | else
|
| 537 | set_pte_at(vma->vm_mm, address, ptep, pte_mkold(pte));
|
| 538 | return young;
|
| 539 | }
|
| 540 | #endif
|
| 541 |
|
| 542 | #ifndef __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
|
| 543 | #if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined(CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG)
|
| 544 | static inline bool pmdp_test_and_clear_young(struct vm_area_struct *vma,
|
| 545 | unsigned long address, pmd_t *pmdp)
|
| 546 | {
|
| 547 | pmd_t pmd = *pmdp;
|
| 548 | bool young = true;
|
| 549 |
|
| 550 | if (!pmd_young(pmd))
|
| 551 | young = false;
|
| 552 | else
|
| 553 | set_pmd_at(vma->vm_mm, address, pmdp, pmd_mkold(pmd));
|
| 554 | return young;
|
| 555 | }
|
| 556 | #else
|
| 557 | static inline bool pmdp_test_and_clear_young(struct vm_area_struct *vma,
|
| 558 | unsigned long address, pmd_t *pmdp)
|
| 559 | {
|
| 560 | BUILD_BUG();
|
| 561 | return false;
|
| 562 | }
|
| 563 | #endif
|
| 564 | #endif
|
| 565 |
|
| 566 | #ifndef __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
|
| 567 | bool ptep_clear_flush_young(struct vm_area_struct *vma,
|
| 568 | unsigned long address, pte_t *ptep);
|
| 569 | #endif
|
| 570 |
|
| 571 | #ifndef __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH
|
| 572 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE
|
| 573 | bool pmdp_clear_flush_young(struct vm_area_struct *vma,
|
| 574 | unsigned long address, pmd_t *pmdp);
|
| 575 | #else
|
| 576 | |
| 577 | * Despite relevant to THP only, this API is called from generic rmap code
|
| 578 | * under PageTransHuge(), hence needs a dummy implementation for !THP
|
| 579 |
|
| 580 | static inline bool pmdp_clear_flush_young(struct vm_area_struct *vma,
|
| 581 | unsigned long address, pmd_t *pmdp)
|
| 582 | {
|
| 583 | BUILD_BUG();
|
| 584 | return false;
|
| 585 | }
|
| 586 | #endif
|
| 587 | #endif
|
| 588 |
|
| 589 | #ifndef arch_has_hw_nonleaf_pmd_young
|
| 590 | |
| 591 | * Return whether the accessed bit in non-leaf PMD entries is supported on the
|
| 592 | * local CPU.
|
| 593 |
|
| 594 | static inline bool arch_has_hw_nonleaf_pmd_young(void)
|
| 595 | {
|
| 596 | return IS_ENABLED(CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG);
|
| 597 | }
|
| 598 | #endif
|
| 599 |
|
| 600 | #ifndef arch_has_hw_pte_young
|
| 601 | |
| 602 | * Return whether the accessed bit is supported on the local CPU.
|
| 603 | *
|
| 604 | * This stub assumes accessing through an old PTE triggers a page fault.
|
| 605 | * Architectures that automatically set the access bit should overwrite it.
|
| 606 |
|
| 607 | static inline bool arch_has_hw_pte_young(void)
|
| 608 | {
|
| 609 | return IS_ENABLED(CONFIG_ARCH_HAS_HW_PTE_YOUNG);
|
| 610 | }
|
| 611 | #endif
|
| 612 |
|
| 613 | #ifndef exec_folio_order
|
| 614 | |
| 615 | * Returns preferred minimum folio order for executable file-backed memory. Must
|
| 616 | * be in range [0, PMD_ORDER). Default to order-0.
|
| 617 |
|
| 618 | static inline unsigned int exec_folio_order(void)
|
| 619 | {
|
| 620 | return 0;
|
| 621 | }
|
| 622 | #endif
|
| 623 |
|
| 624 | #ifndef arch_check_zapped_pte
|
| 625 | static inline void arch_check_zapped_pte(struct vm_area_struct *vma,
|
| 626 | pte_t pte)
|
| 627 | {
|
| 628 | }
|
| 629 | #endif
|
| 630 |
|
| 631 | #ifndef arch_check_zapped_pmd
|
| 632 | static inline void arch_check_zapped_pmd(struct vm_area_struct *vma,
|
| 633 | pmd_t pmd)
|
| 634 | {
|
| 635 | }
|
| 636 | #endif
|
| 637 |
|
| 638 | #ifndef arch_check_zapped_pud
|
| 639 | static inline void arch_check_zapped_pud(struct vm_area_struct *vma, pud_t pud)
|
| 640 | {
|
| 641 | }
|
| 642 | #endif
|
| 643 |
|
| 644 | #ifndef __HAVE_ARCH_PTEP_GET_AND_CLEAR
|
| 645 | static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
|
| 646 | unsigned long address,
|
| 647 | pte_t *ptep)
|
| 648 | {
|
| 649 | pte_t pte = ptep_get(ptep);
|
| 650 | pte_clear(mm, address, ptep);
|
| 651 | page_table_check_pte_clear(mm, address, pte);
|
| 652 | return pte;
|
| 653 | }
|
| 654 | #endif
|
| 655 |
|
| 656 | #ifndef clear_young_dirty_ptes
|
| 657 | |
| 658 | * clear_young_dirty_ptes - Mark PTEs that map consecutive pages of the
|
| 659 | * same folio as old/clean.
|
| 660 | * @mm: Address space the pages are mapped into.
|
| 661 | * @addr: Address the first page is mapped at.
|
| 662 | * @ptep: Page table pointer for the first entry.
|
| 663 | * @nr: Number of entries to mark old/clean.
|
| 664 | * @flags: Flags to modify the PTE batch semantics.
|
| 665 | *
|
| 666 | * May be overridden by the architecture; otherwise, implemented by
|
| 667 | * get_and_clear/modify/set for each pte in the range.
|
| 668 | *
|
| 669 | * Note that PTE bits in the PTE range besides the PFN can differ. For example,
|
| 670 | * some PTEs might be write-protected.
|
| 671 | *
|
| 672 | * Context: The caller holds the page table lock. The PTEs map consecutive
|
| 673 | * pages that belong to the same folio. The PTEs are all in the same PMD.
|
| 674 |
|
| 675 | static inline void clear_young_dirty_ptes(struct vm_area_struct *vma,
|
| 676 | unsigned long addr, pte_t *ptep,
|
| 677 | unsigned int nr, cydp_t flags)
|
| 678 | {
|
| 679 | pte_t pte;
|
| 680 |
|
| 681 | for (;;) {
|
| 682 | if (flags == CYDP_CLEAR_YOUNG)
|
| 683 | ptep_test_and_clear_young(vma, addr, ptep);
|
| 684 | else {
|
| 685 | pte = ptep_get_and_clear(vma->vm_mm, addr, ptep);
|
| 686 | if (flags & CYDP_CLEAR_YOUNG)
|
| 687 | pte = pte_mkold(pte);
|
| 688 | if (flags & CYDP_CLEAR_DIRTY)
|
| 689 | pte = pte_mkclean(pte);
|
| 690 | set_pte_at(vma->vm_mm, addr, ptep, pte);
|
| 691 | }
|
| 692 | if (--nr == 0)
|
| 693 | break;
|
| 694 | ptep++;
|
| 695 | addr += PAGE_SIZE;
|
| 696 | }
|
| 697 | }
|
| 698 | #endif
|
| 699 |
|
| 700 | static inline void ptep_clear(struct mm_struct *mm, unsigned long addr,
|
| 701 | pte_t *ptep)
|
| 702 | {
|
| 703 | pte_t pte = ptep_get(ptep);
|
| 704 |
|
| 705 | pte_clear(mm, addr, ptep);
|
| 706 | |
| 707 | * No need for ptep_get_and_clear(): page table check doesn't care about
|
| 708 | * any bits that could have been set by HW concurrently.
|
| 709 |
|
| 710 | page_table_check_pte_clear(mm, addr, pte);
|
| 711 | }
|
| 712 |
|
| 713 | #ifdef CONFIG_GUP_GET_PXX_LOW_HIGH
|
| 714 | |
| 715 | * For walking the pagetables without holding any locks. Some architectures
|
| 716 | * (eg x86-32 PAE) cannot load the entries atomically without using expensive
|
| 717 | * instructions. We are guaranteed that a PTE will only either go from not
|
| 718 | * present to present, or present to not present -- it will not switch to a
|
| 719 | * completely different present page without a TLB flush inbetween; which we
|
| 720 | * are blocking by holding interrupts off.
|
| 721 | *
|
| 722 | * Setting ptes from not present to present goes:
|
| 723 | *
|
| 724 | * ptep->pte_high = h;
|
| 725 | * smp_wmb();
|
| 726 | * ptep->pte_low = l;
|
| 727 | *
|
| 728 | * And present to not present goes:
|
| 729 | *
|
| 730 | * ptep->pte_low = 0;
|
| 731 | * smp_wmb();
|
| 732 | * ptep->pte_high = 0;
|
| 733 | *
|
| 734 | * We must ensure here that the load of pte_low sees 'l' IFF pte_high sees 'h'.
|
| 735 | * We load pte_high *after* loading pte_low, which ensures we don't see an older
|
| 736 | * value of pte_high. *Then* we recheck pte_low, which ensures that we haven't
|
| 737 | * picked up a changed pte high. We might have gotten rubbish values from
|
| 738 | * pte_low and pte_high, but we are guaranteed that pte_low will not have the
|
| 739 | * present bit set *unless* it is 'l'. Because get_user_pages_fast() only
|
| 740 | * operates on present ptes we're safe.
|
| 741 |
|
| 742 | static inline pte_t ptep_get_lockless(pte_t *ptep)
|
| 743 | {
|
| 744 | pte_t pte;
|
| 745 |
|
| 746 | do {
|
| 747 | pte.pte_low = ptep->pte_low;
|
| 748 | smp_rmb();
|
| 749 | pte.pte_high = ptep->pte_high;
|
| 750 | smp_rmb();
|
| 751 | } while (unlikely(pte.pte_low != ptep->pte_low));
|
| 752 |
|
| 753 | return pte;
|
| 754 | }
|
| 755 | #define ptep_get_lockless ptep_get_lockless
|
| 756 |
|
| 757 | #if CONFIG_PGTABLE_LEVELS > 2
|
| 758 | static inline pmd_t pmdp_get_lockless(pmd_t *pmdp)
|
| 759 | {
|
| 760 | pmd_t pmd;
|
| 761 |
|
| 762 | do {
|
| 763 | pmd.pmd_low = pmdp->pmd_low;
|
| 764 | smp_rmb();
|
| 765 | pmd.pmd_high = pmdp->pmd_high;
|
| 766 | smp_rmb();
|
| 767 | } while (unlikely(pmd.pmd_low != pmdp->pmd_low));
|
| 768 |
|
| 769 | return pmd;
|
| 770 | }
|
| 771 | #define pmdp_get_lockless pmdp_get_lockless
|
| 772 | #define pmdp_get_lockless_sync() tlb_remove_table_sync_one()
|
| 773 | #endif
|
| 774 | #endif
|
| 775 |
|
| 776 | |
| 777 | * We require that the PTE can be read atomically.
|
| 778 |
|
| 779 | #ifndef ptep_get_lockless
|
| 780 | static inline pte_t ptep_get_lockless(pte_t *ptep)
|
| 781 | {
|
| 782 | return ptep_get(ptep);
|
| 783 | }
|
| 784 | #endif
|
| 785 |
|
| 786 | #ifndef pmdp_get_lockless
|
| 787 | static inline pmd_t pmdp_get_lockless(pmd_t *pmdp)
|
| 788 | {
|
| 789 | return pmdp_get(pmdp);
|
| 790 | }
|
| 791 | static inline void pmdp_get_lockless_sync(void)
|
| 792 | {
|
| 793 | }
|
| 794 | #endif
|
| 795 |
|
| 796 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE
|
| 797 | #ifndef __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR
|
| 798 | static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm,
|
| 799 | unsigned long address,
|
| 800 | pmd_t *pmdp)
|
| 801 | {
|
| 802 | pmd_t pmd = *pmdp;
|
| 803 |
|
| 804 | pmd_clear(pmdp);
|
| 805 | page_table_check_pmd_clear(mm, address, pmd);
|
| 806 |
|
| 807 | return pmd;
|
| 808 | }
|
| 809 | #endif
|
| 810 | #ifndef __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR
|
| 811 | static inline pud_t pudp_huge_get_and_clear(struct mm_struct *mm,
|
| 812 | unsigned long address,
|
| 813 | pud_t *pudp)
|
| 814 | {
|
| 815 | pud_t pud = *pudp;
|
| 816 |
|
| 817 | pud_clear(pudp);
|
| 818 | page_table_check_pud_clear(mm, address, pud);
|
| 819 |
|
| 820 | return pud;
|
| 821 | }
|
| 822 | #endif
|
| 823 | #endif
|
| 824 |
|
| 825 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE
|
| 826 | #ifndef __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR_FULL
|
| 827 | static inline pmd_t pmdp_huge_get_and_clear_full(struct vm_area_struct *vma,
|
| 828 | unsigned long address, pmd_t *pmdp,
|
| 829 | int full)
|
| 830 | {
|
| 831 | return pmdp_huge_get_and_clear(vma->vm_mm, address, pmdp);
|
| 832 | }
|
| 833 | #endif
|
| 834 |
|
| 835 | #ifndef __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR_FULL
|
| 836 | static inline pud_t pudp_huge_get_and_clear_full(struct vm_area_struct *vma,
|
| 837 | unsigned long address, pud_t *pudp,
|
| 838 | int full)
|
| 839 | {
|
| 840 | return pudp_huge_get_and_clear(vma->vm_mm, address, pudp);
|
| 841 | }
|
| 842 | #endif
|
| 843 | #endif
|
| 844 |
|
| 845 | #ifndef __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL
|
| 846 | static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm,
|
| 847 | unsigned long address, pte_t *ptep,
|
| 848 | int full)
|
| 849 | {
|
| 850 | return ptep_get_and_clear(mm, address, ptep);
|
| 851 | }
|
| 852 | #endif
|
| 853 |
|
| 854 | #ifndef get_and_clear_full_ptes
|
| 855 | |
| 856 | * get_and_clear_full_ptes - Clear present PTEs that map consecutive pages of
|
| 857 | * the same folio, collecting dirty/accessed bits.
|
| 858 | * @mm: Address space the pages are mapped into.
|
| 859 | * @addr: Address the first page is mapped at.
|
| 860 | * @ptep: Page table pointer for the first entry.
|
| 861 | * @nr: Number of entries to clear.
|
| 862 | * @full: Whether we are clearing a full mm.
|
| 863 | *
|
| 864 | * May be overridden by the architecture; otherwise, implemented as a simple
|
| 865 | * loop over ptep_get_and_clear_full(), merging dirty/accessed bits into the
|
| 866 | * returned PTE.
|
| 867 | *
|
| 868 | * Note that PTE bits in the PTE range besides the PFN can differ. For example,
|
| 869 | * some PTEs might be write-protected.
|
| 870 | *
|
| 871 | * Context: The caller holds the page table lock. The PTEs map consecutive
|
| 872 | * pages that belong to the same folio. The PTEs are all in the same PMD.
|
| 873 |
|
| 874 | static inline pte_t get_and_clear_full_ptes(struct mm_struct *mm,
|
| 875 | unsigned long addr, pte_t *ptep, unsigned int nr, int full)
|
| 876 | {
|
| 877 | pte_t pte, tmp_pte;
|
| 878 |
|
| 879 | pte = ptep_get_and_clear_full(mm, addr, ptep, full);
|
| 880 | while (--nr) {
|
| 881 | ptep++;
|
| 882 | addr += PAGE_SIZE;
|
| 883 | tmp_pte = ptep_get_and_clear_full(mm, addr, ptep, full);
|
| 884 | if (pte_dirty(tmp_pte))
|
| 885 | pte = pte_mkdirty(pte);
|
| 886 | if (pte_young(tmp_pte))
|
| 887 | pte = pte_mkyoung(pte);
|
| 888 | }
|
| 889 | return pte;
|
| 890 | }
|
| 891 | #endif
|
| 892 |
|
| 893 | |
| 894 | * get_and_clear_ptes - Clear present PTEs that map consecutive pages of
|
| 895 | * the same folio, collecting dirty/accessed bits.
|
| 896 | * @mm: Address space the pages are mapped into.
|
| 897 | * @addr: Address the first page is mapped at.
|
| 898 | * @ptep: Page table pointer for the first entry.
|
| 899 | * @nr: Number of entries to clear.
|
| 900 | *
|
| 901 | * Use this instead of get_and_clear_full_ptes() if it is known that we don't
|
| 902 | * need to clear the full mm, which is mostly the case.
|
| 903 | *
|
| 904 | * Note that PTE bits in the PTE range besides the PFN can differ. For example,
|
| 905 | * some PTEs might be write-protected.
|
| 906 | *
|
| 907 | * Context: The caller holds the page table lock. The PTEs map consecutive
|
| 908 | * pages that belong to the same folio. The PTEs are all in the same PMD.
|
| 909 |
|
| 910 | static inline pte_t get_and_clear_ptes(struct mm_struct *mm, unsigned long addr,
|
| 911 | pte_t *ptep, unsigned int nr)
|
| 912 | {
|
| 913 | return get_and_clear_full_ptes(mm, addr, ptep, nr, 0);
|
| 914 | }
|
| 915 |
|
| 916 | #ifndef clear_full_ptes
|
| 917 | |
| 918 | * clear_full_ptes - Clear present PTEs that map consecutive pages of the same
|
| 919 | * folio.
|
| 920 | * @mm: Address space the pages are mapped into.
|
| 921 | * @addr: Address the first page is mapped at.
|
| 922 | * @ptep: Page table pointer for the first entry.
|
| 923 | * @nr: Number of entries to clear.
|
| 924 | * @full: Whether we are clearing a full mm.
|
| 925 | *
|
| 926 | * May be overridden by the architecture; otherwise, implemented as a simple
|
| 927 | * loop over ptep_get_and_clear_full().
|
| 928 | *
|
| 929 | * Note that PTE bits in the PTE range besides the PFN can differ. For example,
|
| 930 | * some PTEs might be write-protected.
|
| 931 | *
|
| 932 | * Context: The caller holds the page table lock. The PTEs map consecutive
|
| 933 | * pages that belong to the same folio. The PTEs are all in the same PMD.
|
| 934 |
|
| 935 | static inline void clear_full_ptes(struct mm_struct *mm, unsigned long addr,
|
| 936 | pte_t *ptep, unsigned int nr, int full)
|
| 937 | {
|
| 938 | for (;;) {
|
| 939 | ptep_get_and_clear_full(mm, addr, ptep, full);
|
| 940 | if (--nr == 0)
|
| 941 | break;
|
| 942 | ptep++;
|
| 943 | addr += PAGE_SIZE;
|
| 944 | }
|
| 945 | }
|
| 946 | #endif
|
| 947 |
|
| 948 | |
| 949 | * clear_ptes - Clear present PTEs that map consecutive pages of the same folio.
|
| 950 | * @mm: Address space the pages are mapped into.
|
| 951 | * @addr: Address the first page is mapped at.
|
| 952 | * @ptep: Page table pointer for the first entry.
|
| 953 | * @nr: Number of entries to clear.
|
| 954 | *
|
| 955 | * Use this instead of clear_full_ptes() if it is known that we don't need to
|
| 956 | * clear the full mm, which is mostly the case.
|
| 957 | *
|
| 958 | * Note that PTE bits in the PTE range besides the PFN can differ. For example,
|
| 959 | * some PTEs might be write-protected.
|
| 960 | *
|
| 961 | * Context: The caller holds the page table lock. The PTEs map consecutive
|
| 962 | * pages that belong to the same folio. The PTEs are all in the same PMD.
|
| 963 |
|
| 964 | static inline void clear_ptes(struct mm_struct *mm, unsigned long addr,
|
| 965 | pte_t *ptep, unsigned int nr)
|
| 966 | {
|
| 967 | clear_full_ptes(mm, addr, ptep, nr, 0);
|
| 968 | }
|
| 969 |
|
| 970 | |
| 971 | * If two threads concurrently fault at the same page, the thread that
|
| 972 | * won the race updates the PTE and its local TLB/Cache. The other thread
|
| 973 | * gives up, simply does nothing, and continues; on architectures where
|
| 974 | * software can update TLB, local TLB can be updated here to avoid next page
|
| 975 | * fault. This function updates TLB only, do nothing with cache or others.
|
| 976 | * It is the difference with function update_mmu_cache.
|
| 977 |
|
| 978 | #ifndef update_mmu_tlb_range
|
| 979 | static inline void update_mmu_tlb_range(struct vm_area_struct *vma,
|
| 980 | unsigned long address, pte_t *ptep, unsigned int nr)
|
| 981 | {
|
| 982 | }
|
| 983 | #endif
|
| 984 |
|
| 985 | static inline void update_mmu_tlb(struct vm_area_struct *vma,
|
| 986 | unsigned long address, pte_t *ptep)
|
| 987 | {
|
| 988 | update_mmu_tlb_range(vma, address, ptep, 1);
|
| 989 | }
|
| 990 |
|
| 991 | |
| 992 | * Some architectures may be able to avoid expensive synchronization
|
| 993 | * primitives when modifications are made to PTE's which are already
|
| 994 | * not present, or in the process of an address space destruction.
|
| 995 |
|
| 996 | #ifndef __HAVE_ARCH_PTE_CLEAR_NOT_PRESENT_FULL
|
| 997 | static inline void pte_clear_not_present_full(struct mm_struct *mm,
|
| 998 | unsigned long address,
|
| 999 | pte_t *ptep,
|
| 1000 | int full)
|
| 1001 | {
|
| 1002 | pte_clear(mm, address, ptep);
|
| 1003 | }
|
| 1004 | #endif
|
| 1005 |
|
| 1006 | #ifndef clear_not_present_full_ptes
|
| 1007 | |
| 1008 | * clear_not_present_full_ptes - Clear multiple not present PTEs which are
|
| 1009 | * consecutive in the pgtable.
|
| 1010 | * @mm: Address space the ptes represent.
|
| 1011 | * @addr: Address of the first pte.
|
| 1012 | * @ptep: Page table pointer for the first entry.
|
| 1013 | * @nr: Number of entries to clear.
|
| 1014 | * @full: Whether we are clearing a full mm.
|
| 1015 | *
|
| 1016 | * May be overridden by the architecture; otherwise, implemented as a simple
|
| 1017 | * loop over pte_clear_not_present_full().
|
| 1018 | *
|
| 1019 | * Context: The caller holds the page table lock. The PTEs are all not present.
|
| 1020 | * The PTEs are all in the same PMD.
|
| 1021 |
|
| 1022 | static inline void clear_not_present_full_ptes(struct mm_struct *mm,
|
| 1023 | unsigned long addr, pte_t *ptep, unsigned int nr, int full)
|
| 1024 | {
|
| 1025 | for (;;) {
|
| 1026 | pte_clear_not_present_full(mm, addr, ptep, full);
|
| 1027 | if (--nr == 0)
|
| 1028 | break;
|
| 1029 | ptep++;
|
| 1030 | addr += PAGE_SIZE;
|
| 1031 | }
|
| 1032 | }
|
| 1033 | #endif
|
| 1034 |
|
| 1035 | #ifndef __HAVE_ARCH_PTEP_CLEAR_FLUSH
|
| 1036 | extern pte_t ptep_clear_flush(struct vm_area_struct *vma,
|
| 1037 | unsigned long address,
|
| 1038 | pte_t *ptep);
|
| 1039 | #endif
|
| 1040 |
|
| 1041 | #ifndef __HAVE_ARCH_PMDP_HUGE_CLEAR_FLUSH
|
| 1042 | extern pmd_t pmdp_huge_clear_flush(struct vm_area_struct *vma,
|
| 1043 | unsigned long address,
|
| 1044 | pmd_t *pmdp);
|
| 1045 | extern pud_t pudp_huge_clear_flush(struct vm_area_struct *vma,
|
| 1046 | unsigned long address,
|
| 1047 | pud_t *pudp);
|
| 1048 | #endif
|
| 1049 |
|
| 1050 | #ifndef pte_mkwrite
|
| 1051 | static inline pte_t pte_mkwrite(pte_t pte, struct vm_area_struct *vma)
|
| 1052 | {
|
| 1053 | return pte_mkwrite_novma(pte);
|
| 1054 | }
|
| 1055 | #endif
|
| 1056 |
|
| 1057 | #if defined(CONFIG_ARCH_WANT_PMD_MKWRITE) && !defined(pmd_mkwrite)
|
| 1058 | static inline pmd_t pmd_mkwrite(pmd_t pmd, struct vm_area_struct *vma)
|
| 1059 | {
|
| 1060 | return pmd_mkwrite_novma(pmd);
|
| 1061 | }
|
| 1062 | #endif
|
| 1063 |
|
| 1064 | #ifndef __HAVE_ARCH_PTEP_SET_WRPROTECT
|
| 1065 | struct mm_struct;
|
| 1066 | static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep)
|
| 1067 | {
|
| 1068 | pte_t old_pte = ptep_get(ptep);
|
| 1069 | set_pte_at(mm, address, ptep, pte_wrprotect(old_pte));
|
| 1070 | }
|
| 1071 | #endif
|
| 1072 |
|
| 1073 | #ifndef ptep_try_set
|
| 1074 | |
| 1075 | * ptep_try_set - atomically set an empty kernel PTE
|
| 1076 | * @ptep: page table entry
|
| 1077 | * @new_pte: value to install
|
| 1078 | *
|
| 1079 | * Atomically set *@ptep to @new_pte iff *@ptep is pte_none(). Return true on
|
| 1080 | * success, false if the slot was already populated or the arch has no
|
| 1081 | * implementation.
|
| 1082 | *
|
| 1083 | * For special kernel page tables only - never user page tables. The caller must
|
| 1084 | * prevent concurrent teardown of @ptep and must accept that other writers may
|
| 1085 | * race. Concurrent clearers must use ptep_get_and_clear() so racing accesses
|
| 1086 | * agree on the outcome.
|
| 1087 | *
|
| 1088 | * Architectures opt in by providing a cmpxchg-based override and defining
|
| 1089 | * ptep_try_set as an identity macro. The generic stub returns false, which is
|
| 1090 | * correct for callers that fall through to oops on failure.
|
| 1091 |
|
| 1092 | static inline bool ptep_try_set(pte_t *ptep, pte_t new_pte)
|
| 1093 | {
|
| 1094 | return false;
|
| 1095 | }
|
| 1096 | #endif
|
| 1097 |
|
| 1098 | #ifndef flush_tlb_before_set
|
| 1099 | |
| 1100 | * flush_tlb_before_set - invalidate a kernel PTE's TLB before re-setting it
|
| 1101 | * @addr: kernel virtual address whose PTE was just cleared
|
| 1102 | *
|
| 1103 | * Some architectures (e.g. arm64) do not allow a live page-table entry to be
|
| 1104 | * repointed at a different page in one step. The old entry must first be made
|
| 1105 | * invalid and its translation flushed from every TLB, and only then may the new
|
| 1106 | * entry be written.
|
| 1107 | *
|
| 1108 | * This is only for the lockless atomic kernel-PTE installers (ptep_try_set()).
|
| 1109 | * It must be callable with interrupts disabled.
|
| 1110 |
|
| 1111 | static inline void flush_tlb_before_set(unsigned long addr)
|
| 1112 | {
|
| 1113 | }
|
| 1114 | #endif
|
| 1115 |
|
| 1116 | #ifndef wrprotect_ptes
|
| 1117 | |
| 1118 | * wrprotect_ptes - Write-protect PTEs that map consecutive pages of the same
|
| 1119 | * folio.
|
| 1120 | * @mm: Address space the pages are mapped into.
|
| 1121 | * @addr: Address the first page is mapped at.
|
| 1122 | * @ptep: Page table pointer for the first entry.
|
| 1123 | * @nr: Number of entries to write-protect.
|
| 1124 | *
|
| 1125 | * May be overridden by the architecture; otherwise, implemented as a simple
|
| 1126 | * loop over ptep_set_wrprotect().
|
| 1127 | *
|
| 1128 | * Note that PTE bits in the PTE range besides the PFN can differ. For example,
|
| 1129 | * some PTEs might be write-protected.
|
| 1130 | *
|
| 1131 | * Context: The caller holds the page table lock. The PTEs map consecutive
|
| 1132 | * pages that belong to the same folio. The PTEs are all in the same PMD.
|
| 1133 |
|
| 1134 | static inline void wrprotect_ptes(struct mm_struct *mm, unsigned long addr,
|
| 1135 | pte_t *ptep, unsigned int nr)
|
| 1136 | {
|
| 1137 | for (;;) {
|
| 1138 | ptep_set_wrprotect(mm, addr, ptep);
|
| 1139 | if (--nr == 0)
|
| 1140 | break;
|
| 1141 | ptep++;
|
| 1142 | addr += PAGE_SIZE;
|
| 1143 | }
|
| 1144 | }
|
| 1145 | #endif
|
| 1146 |
|
| 1147 | #ifndef clear_flush_young_ptes
|
| 1148 | |
| 1149 | * clear_flush_young_ptes - Mark PTEs that map consecutive pages of the same
|
| 1150 | * folio as old and flush the TLB.
|
| 1151 | * @vma: The virtual memory area the pages are mapped into.
|
| 1152 | * @addr: Address the first page is mapped at.
|
| 1153 | * @ptep: Page table pointer for the first entry.
|
| 1154 | * @nr: Number of entries to clear access bit.
|
| 1155 | *
|
| 1156 | * May be overridden by the architecture; otherwise, implemented as a simple
|
| 1157 | * loop over ptep_clear_flush_young().
|
| 1158 | *
|
| 1159 | * Note that PTE bits in the PTE range besides the PFN can differ. For example,
|
| 1160 | * some PTEs might be write-protected.
|
| 1161 | *
|
| 1162 | * Context: The caller holds the page table lock. The PTEs map consecutive
|
| 1163 | * pages that belong to the same folio. The PTEs are all in the same PMD.
|
| 1164 |
|
| 1165 | static inline bool clear_flush_young_ptes(struct vm_area_struct *vma,
|
| 1166 | unsigned long addr, pte_t *ptep, unsigned int nr)
|
| 1167 | {
|
| 1168 | bool young = false;
|
| 1169 |
|
| 1170 | for (;;) {
|
| 1171 | young |= ptep_clear_flush_young(vma, addr, ptep);
|
| 1172 | if (--nr == 0)
|
| 1173 | break;
|
| 1174 | ptep++;
|
| 1175 | addr += PAGE_SIZE;
|
| 1176 | }
|
| 1177 |
|
| 1178 | return young;
|
| 1179 | }
|
| 1180 | #endif
|
| 1181 |
|
| 1182 | #ifndef test_and_clear_young_ptes
|
| 1183 | |
| 1184 | * test_and_clear_young_ptes - Mark PTEs that map consecutive pages of the same
|
| 1185 | * folio as old
|
| 1186 | * @vma: The virtual memory area the pages are mapped into.
|
| 1187 | * @addr: Address the first page is mapped at.
|
| 1188 | * @ptep: Page table pointer for the first entry.
|
| 1189 | * @nr: Number of entries to clear access bit.
|
| 1190 | *
|
| 1191 | * May be overridden by the architecture; otherwise, implemented as a simple
|
| 1192 | * loop over ptep_test_and_clear_young().
|
| 1193 | *
|
| 1194 | * Note that PTE bits in the PTE range besides the PFN can differ. For example,
|
| 1195 | * some PTEs might be write-protected.
|
| 1196 | *
|
| 1197 | * Context: The caller holds the page table lock. The PTEs map consecutive
|
| 1198 | * pages that belong to the same folio. The PTEs are all in the same PMD.
|
| 1199 | *
|
| 1200 | * Returns: whether any PTE was young.
|
| 1201 |
|
| 1202 | static inline bool test_and_clear_young_ptes(struct vm_area_struct *vma,
|
| 1203 | unsigned long addr, pte_t *ptep, unsigned int nr)
|
| 1204 | {
|
| 1205 | bool young = false;
|
| 1206 |
|
| 1207 | for (;;) {
|
| 1208 | young |= ptep_test_and_clear_young(vma, addr, ptep);
|
| 1209 | if (--nr == 0)
|
| 1210 | break;
|
| 1211 | ptep++;
|
| 1212 | addr += PAGE_SIZE;
|
| 1213 | }
|
| 1214 |
|
| 1215 | return young;
|
| 1216 | }
|
| 1217 | #endif
|
| 1218 |
|
| 1219 | |
| 1220 | * On some architectures hardware does not set page access bit when accessing
|
| 1221 | * memory page, it is responsibility of software setting this bit. It brings
|
| 1222 | * out extra page fault penalty to track page access bit. For optimization page
|
| 1223 | * access bit can be set during all page fault flow on these arches.
|
| 1224 | * To be differentiate with macro pte_mkyoung, this macro is used on platforms
|
| 1225 | * where software maintains page access bit.
|
| 1226 |
|
| 1227 | #ifndef pte_sw_mkyoung
|
| 1228 | static inline pte_t pte_sw_mkyoung(pte_t pte)
|
| 1229 | {
|
| 1230 | return pte;
|
| 1231 | }
|
| 1232 | #define pte_sw_mkyoung pte_sw_mkyoung
|
| 1233 | #endif
|
| 1234 |
|
| 1235 | #ifndef __HAVE_ARCH_PMDP_SET_WRPROTECT
|
| 1236 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE
|
| 1237 | static inline void pmdp_set_wrprotect(struct mm_struct *mm,
|
| 1238 | unsigned long address, pmd_t *pmdp)
|
| 1239 | {
|
| 1240 | pmd_t old_pmd = *pmdp;
|
| 1241 | set_pmd_at(mm, address, pmdp, pmd_wrprotect(old_pmd));
|
| 1242 | }
|
| 1243 | #else
|
| 1244 | static inline void pmdp_set_wrprotect(struct mm_struct *mm,
|
| 1245 | unsigned long address, pmd_t *pmdp)
|
| 1246 | {
|
| 1247 | BUILD_BUG();
|
| 1248 | }
|
| 1249 | #endif
|
| 1250 | #endif
|
| 1251 | #ifndef __HAVE_ARCH_PUDP_SET_WRPROTECT
|
| 1252 | #ifdef CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD
|
| 1253 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE
|
| 1254 | static inline void pudp_set_wrprotect(struct mm_struct *mm,
|
| 1255 | unsigned long address, pud_t *pudp)
|
| 1256 | {
|
| 1257 | pud_t old_pud = *pudp;
|
| 1258 |
|
| 1259 | set_pud_at(mm, address, pudp, pud_wrprotect(old_pud));
|
| 1260 | }
|
| 1261 | #else
|
| 1262 | static inline void pudp_set_wrprotect(struct mm_struct *mm,
|
| 1263 | unsigned long address, pud_t *pudp)
|
| 1264 | {
|
| 1265 | BUILD_BUG();
|
| 1266 | }
|
| 1267 | #endif
|
| 1268 | #endif
|
| 1269 | #endif
|
| 1270 |
|
| 1271 | #ifndef pmdp_collapse_flush
|
| 1272 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE
|
| 1273 | extern pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
|
| 1274 | unsigned long address, pmd_t *pmdp);
|
| 1275 | #else
|
| 1276 | static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
|
| 1277 | unsigned long address,
|
| 1278 | pmd_t *pmdp)
|
| 1279 | {
|
| 1280 | BUILD_BUG();
|
| 1281 | return *pmdp;
|
| 1282 | }
|
| 1283 | #define pmdp_collapse_flush pmdp_collapse_flush
|
| 1284 | #endif
|
| 1285 | #endif
|
| 1286 |
|
| 1287 | #ifndef __HAVE_ARCH_PGTABLE_DEPOSIT
|
| 1288 | extern void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
|
| 1289 | pgtable_t pgtable);
|
| 1290 | #endif
|
| 1291 |
|
| 1292 | #ifndef __HAVE_ARCH_PGTABLE_WITHDRAW
|
| 1293 | extern pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp);
|
| 1294 | #endif
|
| 1295 |
|
| 1296 | #ifndef arch_needs_pgtable_deposit
|
| 1297 | #define arch_needs_pgtable_deposit() (false)
|
| 1298 | #endif
|
| 1299 |
|
| 1300 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE
|
| 1301 | |
| 1302 | * This is an implementation of pmdp_establish() that is only suitable for an
|
| 1303 | * architecture that doesn't have hardware dirty/accessed bits. In this case we
|
| 1304 | * can't race with CPU which sets these bits and non-atomic approach is fine.
|
| 1305 |
|
| 1306 | static inline pmd_t generic_pmdp_establish(struct vm_area_struct *vma,
|
| 1307 | unsigned long address, pmd_t *pmdp, pmd_t pmd)
|
| 1308 | {
|
| 1309 | pmd_t old_pmd = *pmdp;
|
| 1310 | set_pmd_at(vma->vm_mm, address, pmdp, pmd);
|
| 1311 | return old_pmd;
|
| 1312 | }
|
| 1313 | #endif
|
| 1314 |
|
| 1315 | #ifndef __HAVE_ARCH_PMDP_INVALIDATE
|
| 1316 | extern pmd_t pmdp_invalidate(struct vm_area_struct *vma, unsigned long address,
|
| 1317 | pmd_t *pmdp);
|
| 1318 | #endif
|
| 1319 |
|
| 1320 | #ifndef __HAVE_ARCH_PMDP_INVALIDATE_AD
|
| 1321 |
|
| 1322 | |
| 1323 | * pmdp_invalidate_ad() invalidates the PMD while changing a transparent
|
| 1324 | * hugepage mapping in the page tables. This function is similar to
|
| 1325 | * pmdp_invalidate(), but should only be used if the access and dirty bits would
|
| 1326 | * not be cleared by the software in the new PMD value. The function ensures
|
| 1327 | * that hardware changes of the access and dirty bits updates would not be lost.
|
| 1328 | *
|
| 1329 | * Doing so can allow in certain architectures to avoid a TLB flush in most
|
| 1330 | * cases. Yet, another TLB flush might be necessary later if the PMD update
|
| 1331 | * itself requires such flush (e.g., if protection was set to be stricter). Yet,
|
| 1332 | * even when a TLB flush is needed because of the update, the caller may be able
|
| 1333 | * to batch these TLB flushing operations, so fewer TLB flush operations are
|
| 1334 | * needed.
|
| 1335 |
|
| 1336 | extern pmd_t pmdp_invalidate_ad(struct vm_area_struct *vma,
|
| 1337 | unsigned long address, pmd_t *pmdp);
|
| 1338 | #endif
|
| 1339 |
|
| 1340 | #ifndef __HAVE_ARCH_PTE_SAME
|
| 1341 | static inline int pte_same(pte_t pte_a, pte_t pte_b)
|
| 1342 | {
|
| 1343 | return pte_val(pte_a) == pte_val(pte_b);
|
| 1344 | }
|
| 1345 | #endif
|
| 1346 |
|
| 1347 | #ifndef __HAVE_ARCH_PTE_UNUSED
|
| 1348 | |
| 1349 | * Some architectures provide facilities to virtualization guests
|
| 1350 | * so that they can flag allocated pages as unused. This allows the
|
| 1351 | * host to transparently reclaim unused pages. This function returns
|
| 1352 | * whether the pte's page is unused.
|
| 1353 |
|
| 1354 | static inline int pte_unused(pte_t pte)
|
| 1355 | {
|
| 1356 | return 0;
|
| 1357 | }
|
| 1358 | #endif
|
| 1359 |
|
| 1360 | #ifndef pte_access_permitted
|
| 1361 | #define pte_access_permitted(pte, write) \
|
| 1362 | (pte_present(pte) && (!(write) || pte_write(pte)))
|
| 1363 | #endif
|
| 1364 |
|
| 1365 | #ifndef pmd_access_permitted
|
| 1366 | #define pmd_access_permitted(pmd, write) \
|
| 1367 | (pmd_present(pmd) && (!(write) || pmd_write(pmd)))
|
| 1368 | #endif
|
| 1369 |
|
| 1370 | #ifndef pud_access_permitted
|
| 1371 | #define pud_access_permitted(pud, write) \
|
| 1372 | (pud_present(pud) && (!(write) || pud_write(pud)))
|
| 1373 | #endif
|
| 1374 |
|
| 1375 | #ifndef p4d_access_permitted
|
| 1376 | #define p4d_access_permitted(p4d, write) \
|
| 1377 | (p4d_present(p4d) && (!(write) || p4d_write(p4d)))
|
| 1378 | #endif
|
| 1379 |
|
| 1380 | #ifndef pgd_access_permitted
|
| 1381 | #define pgd_access_permitted(pgd, write) \
|
| 1382 | (pgd_present(pgd) && (!(write) || pgd_write(pgd)))
|
| 1383 | #endif
|
| 1384 |
|
| 1385 | #ifndef __HAVE_ARCH_PMD_SAME
|
| 1386 | static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b)
|
| 1387 | {
|
| 1388 | return pmd_val(pmd_a) == pmd_val(pmd_b);
|
| 1389 | }
|
| 1390 | #endif
|
| 1391 |
|
| 1392 | #ifndef pud_same
|
| 1393 | static inline int pud_same(pud_t pud_a, pud_t pud_b)
|
| 1394 | {
|
| 1395 | return pud_val(pud_a) == pud_val(pud_b);
|
| 1396 | }
|
| 1397 | #define pud_same pud_same
|
| 1398 | #endif
|
| 1399 |
|
| 1400 | #ifndef __HAVE_ARCH_P4D_SAME
|
| 1401 | static inline int p4d_same(p4d_t p4d_a, p4d_t p4d_b)
|
| 1402 | {
|
| 1403 | return p4d_val(p4d_a) == p4d_val(p4d_b);
|
| 1404 | }
|
| 1405 | #endif
|
| 1406 |
|
| 1407 | #ifndef __HAVE_ARCH_PGD_SAME
|
| 1408 | static inline int pgd_same(pgd_t pgd_a, pgd_t pgd_b)
|
| 1409 | {
|
| 1410 | return pgd_val(pgd_a) == pgd_val(pgd_b);
|
| 1411 | }
|
| 1412 | #endif
|
| 1413 |
|
| 1414 | #ifndef __HAVE_ARCH_DO_SWAP_PAGE
|
| 1415 | static inline void arch_do_swap_page_nr(struct mm_struct *mm,
|
| 1416 | struct vm_area_struct *vma,
|
| 1417 | unsigned long addr,
|
| 1418 | pte_t pte, pte_t oldpte,
|
| 1419 | int nr)
|
| 1420 | {
|
| 1421 |
|
| 1422 | }
|
| 1423 | #else
|
| 1424 | |
| 1425 | * Some architectures support metadata associated with a page. When a
|
| 1426 | * page is being swapped out, this metadata must be saved so it can be
|
| 1427 | * restored when the page is swapped back in. SPARC M7 and newer
|
| 1428 | * processors support an ADI (Application Data Integrity) tag for the
|
| 1429 | * page as metadata for the page. arch_do_swap_page() can restore this
|
| 1430 | * metadata when a page is swapped back in.
|
| 1431 |
|
| 1432 | static inline void arch_do_swap_page_nr(struct mm_struct *mm,
|
| 1433 | struct vm_area_struct *vma,
|
| 1434 | unsigned long addr,
|
| 1435 | pte_t pte, pte_t oldpte,
|
| 1436 | int nr)
|
| 1437 | {
|
| 1438 | for (int i = 0; i < nr; i++) {
|
| 1439 | arch_do_swap_page(vma->vm_mm, vma, addr + i * PAGE_SIZE,
|
| 1440 | pte_advance_pfn(pte, i),
|
| 1441 | pte_advance_pfn(oldpte, i));
|
| 1442 | }
|
| 1443 | }
|
| 1444 | #endif
|
| 1445 |
|
| 1446 | #ifndef __HAVE_ARCH_UNMAP_ONE
|
| 1447 | |
| 1448 | * Some architectures support metadata associated with a page. When a
|
| 1449 | * page is being swapped out, this metadata must be saved so it can be
|
| 1450 | * restored when the page is swapped back in. SPARC M7 and newer
|
| 1451 | * processors support an ADI (Application Data Integrity) tag for the
|
| 1452 | * page as metadata for the page. arch_unmap_one() can save this
|
| 1453 | * metadata on a swap-out of a page.
|
| 1454 |
|
| 1455 | static inline int arch_unmap_one(struct mm_struct *mm,
|
| 1456 | struct vm_area_struct *vma,
|
| 1457 | unsigned long addr,
|
| 1458 | pte_t orig_pte)
|
| 1459 | {
|
| 1460 | return 0;
|
| 1461 | }
|
| 1462 | #endif
|
| 1463 |
|
| 1464 | |
| 1465 | * Allow architectures to preserve additional metadata associated with
|
| 1466 | * swapped-out pages. The corresponding __HAVE_ARCH_SWAP_* macros and function
|
| 1467 | * prototypes must be defined in the arch-specific asm/pgtable.h file.
|
| 1468 |
|
| 1469 | #ifndef __HAVE_ARCH_PREPARE_TO_SWAP
|
| 1470 | static inline int arch_prepare_to_swap(struct folio *folio)
|
| 1471 | {
|
| 1472 | return 0;
|
| 1473 | }
|
| 1474 | #endif
|
| 1475 |
|
| 1476 | #ifndef __HAVE_ARCH_SWAP_INVALIDATE
|
| 1477 | static inline void arch_swap_invalidate_page(int type, pgoff_t offset)
|
| 1478 | {
|
| 1479 | }
|
| 1480 |
|
| 1481 | static inline void arch_swap_invalidate_area(int type)
|
| 1482 | {
|
| 1483 | }
|
| 1484 | #endif
|
| 1485 |
|
| 1486 | #ifndef __HAVE_ARCH_SWAP_RESTORE
|
| 1487 | static inline void arch_swap_restore(swp_entry_t entry, struct folio *folio)
|
| 1488 | {
|
| 1489 | }
|
| 1490 | #endif
|
| 1491 |
|
| 1492 | #ifndef __HAVE_ARCH_MOVE_PTE
|
| 1493 | #define move_pte(pte, old_addr, new_addr) (pte)
|
| 1494 | #endif
|
| 1495 |
|
| 1496 | #ifndef pte_accessible
|
| 1497 | # define pte_accessible(mm, pte) ((void)(pte), 1)
|
| 1498 | #endif
|
| 1499 |
|
| 1500 | #ifndef flush_tlb_fix_spurious_fault
|
| 1501 | #define flush_tlb_fix_spurious_fault(vma, address, ptep) flush_tlb_page(vma, address)
|
| 1502 | #endif
|
| 1503 |
|
| 1504 | #ifndef flush_tlb_fix_spurious_fault_pmd
|
| 1505 | #define flush_tlb_fix_spurious_fault_pmd(vma, address, pmdp) do { } while (0)
|
| 1506 | #endif
|
| 1507 |
|
| 1508 | |
| 1509 | * When walking page tables, get the address of the next boundary,
|
| 1510 | * or the end address of the range if that comes earlier. Although no
|
| 1511 | * vma end wraps to 0, rounded up __boundary may wrap to 0 throughout.
|
| 1512 |
|
| 1513 |
|
| 1514 | #define pgd_addr_end(addr, end) \
|
| 1515 | ({ unsigned long __boundary = ((addr) + PGDIR_SIZE) & PGDIR_MASK; \
|
| 1516 | (__boundary - 1 < (end) - 1)? __boundary: (end); \
|
| 1517 | })
|
| 1518 |
|
| 1519 | #ifndef p4d_addr_end
|
| 1520 | #define p4d_addr_end(addr, end) \
|
| 1521 | ({ unsigned long __boundary = ((addr) + P4D_SIZE) & P4D_MASK; \
|
| 1522 | (__boundary - 1 < (end) - 1)? __boundary: (end); \
|
| 1523 | })
|
| 1524 | #endif
|
| 1525 |
|
| 1526 | #ifndef pud_addr_end
|
| 1527 | #define pud_addr_end(addr, end) \
|
| 1528 | ({ unsigned long __boundary = ((addr) + PUD_SIZE) & PUD_MASK; \
|
| 1529 | (__boundary - 1 < (end) - 1)? __boundary: (end); \
|
| 1530 | })
|
| 1531 | #endif
|
| 1532 |
|
| 1533 | #ifndef pmd_addr_end
|
| 1534 | #define pmd_addr_end(addr, end) \
|
| 1535 | ({ unsigned long __boundary = ((addr) + PMD_SIZE) & PMD_MASK; \
|
| 1536 | (__boundary - 1 < (end) - 1)? __boundary: (end); \
|
| 1537 | })
|
| 1538 | #endif
|
| 1539 |
|
| 1540 | |
| 1541 | * When walking page tables, we usually want to skip any p?d_none entries;
|
| 1542 | * and any p?d_bad entries - reporting the error before resetting to none.
|
| 1543 | * Do the tests inline, but report and clear the bad entry in mm/memory.c.
|
| 1544 |
|
| 1545 | void pgd_clear_bad(pgd_t *);
|
| 1546 |
|
| 1547 | #ifndef __PAGETABLE_P4D_FOLDED
|
| 1548 | void p4d_clear_bad(p4d_t *);
|
| 1549 | #else
|
| 1550 | #define p4d_clear_bad(p4d) do { } while (0)
|
| 1551 | #endif
|
| 1552 |
|
| 1553 | #ifndef __PAGETABLE_PUD_FOLDED
|
| 1554 | void pud_clear_bad(pud_t *);
|
| 1555 | #else
|
| 1556 | #define pud_clear_bad(p4d) do { } while (0)
|
| 1557 | #endif
|
| 1558 |
|
| 1559 | void pmd_clear_bad(pmd_t *);
|
| 1560 |
|
| 1561 | static inline int pgd_none_or_clear_bad(pgd_t *pgd)
|
| 1562 | {
|
| 1563 | if (pgd_none(*pgd))
|
| 1564 | return 1;
|
| 1565 | if (unlikely(pgd_bad(*pgd))) {
|
| 1566 | pgd_clear_bad(pgd);
|
| 1567 | return 1;
|
| 1568 | }
|
| 1569 | return 0;
|
| 1570 | }
|
| 1571 |
|
| 1572 | static inline int p4d_none_or_clear_bad(p4d_t *p4d)
|
| 1573 | {
|
| 1574 | if (p4d_none(*p4d))
|
| 1575 | return 1;
|
| 1576 | if (unlikely(p4d_bad(*p4d))) {
|
| 1577 | p4d_clear_bad(p4d);
|
| 1578 | return 1;
|
| 1579 | }
|
| 1580 | return 0;
|
| 1581 | }
|
| 1582 |
|
| 1583 | static inline int pud_none_or_clear_bad(pud_t *pud)
|
| 1584 | {
|
| 1585 | if (pud_none(*pud))
|
| 1586 | return 1;
|
| 1587 | if (unlikely(pud_bad(*pud))) {
|
| 1588 | pud_clear_bad(pud);
|
| 1589 | return 1;
|
| 1590 | }
|
| 1591 | return 0;
|
| 1592 | }
|
| 1593 |
|
| 1594 | static inline int pmd_none_or_clear_bad(pmd_t *pmd)
|
| 1595 | {
|
| 1596 | if (pmd_none(*pmd))
|
| 1597 | return 1;
|
| 1598 | if (unlikely(pmd_bad(*pmd))) {
|
| 1599 | pmd_clear_bad(pmd);
|
| 1600 | return 1;
|
| 1601 | }
|
| 1602 | return 0;
|
| 1603 | }
|
| 1604 |
|
| 1605 | static inline pte_t __ptep_modify_prot_start(struct vm_area_struct *vma,
|
| 1606 | unsigned long addr,
|
| 1607 | pte_t *ptep)
|
| 1608 | {
|
| 1609 | |
| 1610 | * Get the current pte state, but zero it out to make it
|
| 1611 | * non-present, preventing the hardware from asynchronously
|
| 1612 | * updating it.
|
| 1613 |
|
| 1614 | return ptep_get_and_clear(vma->vm_mm, addr, ptep);
|
| 1615 | }
|
| 1616 |
|
| 1617 | static inline void __ptep_modify_prot_commit(struct vm_area_struct *vma,
|
| 1618 | unsigned long addr,
|
| 1619 | pte_t *ptep, pte_t pte)
|
| 1620 | {
|
| 1621 | |
| 1622 | * The pte is non-present, so there's no hardware state to
|
| 1623 | * preserve.
|
| 1624 |
|
| 1625 | set_pte_at(vma->vm_mm, addr, ptep, pte);
|
| 1626 | }
|
| 1627 |
|
| 1628 | #ifndef __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION
|
| 1629 | |
| 1630 | * Start a pte protection read-modify-write transaction, which
|
| 1631 | * protects against asynchronous hardware modifications to the pte.
|
| 1632 | * The intention is not to prevent the hardware from making pte
|
| 1633 | * updates, but to prevent any updates it may make from being lost.
|
| 1634 | *
|
| 1635 | * This does not protect against other software modifications of the
|
| 1636 | * pte; the appropriate pte lock must be held over the transaction.
|
| 1637 | *
|
| 1638 | * Note that this interface is intended to be batchable, meaning that
|
| 1639 | * ptep_modify_prot_commit may not actually update the pte, but merely
|
| 1640 | * queue the update to be done at some later time. The update must be
|
| 1641 | * actually committed before the pte lock is released, however.
|
| 1642 |
|
| 1643 | static inline pte_t ptep_modify_prot_start(struct vm_area_struct *vma,
|
| 1644 | unsigned long addr,
|
| 1645 | pte_t *ptep)
|
| 1646 | {
|
| 1647 | return __ptep_modify_prot_start(vma, addr, ptep);
|
| 1648 | }
|
| 1649 |
|
| 1650 | |
| 1651 | * Commit an update to a pte, leaving any hardware-controlled bits in
|
| 1652 | * the PTE unmodified. The pte returned from ptep_modify_prot_start() may
|
| 1653 | * additionally have young and/or dirty bits set where previously they were not,
|
| 1654 | * so the updated pte may have these additional changes.
|
| 1655 |
|
| 1656 | static inline void ptep_modify_prot_commit(struct vm_area_struct *vma,
|
| 1657 | unsigned long addr,
|
| 1658 | pte_t *ptep, pte_t old_pte, pte_t pte)
|
| 1659 | {
|
| 1660 | __ptep_modify_prot_commit(vma, addr, ptep, pte);
|
| 1661 | }
|
| 1662 | #endif
|
| 1663 |
|
| 1664 | |
| 1665 | * modify_prot_start_ptes - Start a pte protection read-modify-write transaction
|
| 1666 | * over a batch of ptes, which protects against asynchronous hardware
|
| 1667 | * modifications to the ptes. The intention is not to prevent the hardware from
|
| 1668 | * making pte updates, but to prevent any updates it may make from being lost.
|
| 1669 | * Please see the comment above ptep_modify_prot_start() for full description.
|
| 1670 | *
|
| 1671 | * @vma: The virtual memory area the pages are mapped into.
|
| 1672 | * @addr: Address the first page is mapped at.
|
| 1673 | * @ptep: Page table pointer for the first entry.
|
| 1674 | * @nr: Number of entries.
|
| 1675 | *
|
| 1676 | * May be overridden by the architecture; otherwise, implemented as a simple
|
| 1677 | * loop over ptep_modify_prot_start(), collecting the a/d bits from each pte
|
| 1678 | * in the batch.
|
| 1679 | *
|
| 1680 | * Note that PTE bits in the PTE batch besides the PFN can differ.
|
| 1681 | *
|
| 1682 | * Context: The caller holds the page table lock. The PTEs map consecutive
|
| 1683 | * pages that belong to the same folio. All other PTE bits must be identical for
|
| 1684 | * all PTEs in the batch except for young and dirty bits. The PTEs are all in
|
| 1685 | * the same PMD.
|
| 1686 |
|
| 1687 | #ifndef modify_prot_start_ptes
|
| 1688 | static inline pte_t modify_prot_start_ptes(struct vm_area_struct *vma,
|
| 1689 | unsigned long addr, pte_t *ptep, unsigned int nr)
|
| 1690 | {
|
| 1691 | pte_t pte, tmp_pte;
|
| 1692 |
|
| 1693 | pte = ptep_modify_prot_start(vma, addr, ptep);
|
| 1694 | while (--nr) {
|
| 1695 | ptep++;
|
| 1696 | addr += PAGE_SIZE;
|
| 1697 | tmp_pte = ptep_modify_prot_start(vma, addr, ptep);
|
| 1698 | if (pte_dirty(tmp_pte))
|
| 1699 | pte = pte_mkdirty(pte);
|
| 1700 | if (pte_young(tmp_pte))
|
| 1701 | pte = pte_mkyoung(pte);
|
| 1702 | }
|
| 1703 | return pte;
|
| 1704 | }
|
| 1705 | #endif
|
| 1706 |
|
| 1707 | |
| 1708 | * modify_prot_commit_ptes - Commit an update to a batch of ptes, leaving any
|
| 1709 | * hardware-controlled bits in the PTE unmodified.
|
| 1710 | *
|
| 1711 | * @vma: The virtual memory area the pages are mapped into.
|
| 1712 | * @addr: Address the first page is mapped at.
|
| 1713 | * @ptep: Page table pointer for the first entry.
|
| 1714 | * @old_pte: Old page table entry (for the first entry) which is now cleared.
|
| 1715 | * @pte: New page table entry to be set.
|
| 1716 | * @nr: Number of entries.
|
| 1717 | *
|
| 1718 | * May be overridden by the architecture; otherwise, implemented as a simple
|
| 1719 | * loop over ptep_modify_prot_commit().
|
| 1720 | *
|
| 1721 | * Context: The caller holds the page table lock. The PTEs are all in the same
|
| 1722 | * PMD. On exit, the set ptes in the batch map the same folio. The ptes set by
|
| 1723 | * ptep_modify_prot_start() may additionally have young and/or dirty bits set
|
| 1724 | * where previously they were not, so the updated ptes may have these
|
| 1725 | * additional changes.
|
| 1726 |
|
| 1727 | #ifndef modify_prot_commit_ptes
|
| 1728 | static inline void modify_prot_commit_ptes(struct vm_area_struct *vma, unsigned long addr,
|
| 1729 | pte_t *ptep, pte_t old_pte, pte_t pte, unsigned int nr)
|
| 1730 | {
|
| 1731 | int i;
|
| 1732 |
|
| 1733 | for (i = 0; i < nr; ++i, ++ptep, addr += PAGE_SIZE) {
|
| 1734 | ptep_modify_prot_commit(vma, addr, ptep, old_pte, pte);
|
| 1735 |
|
| 1736 |
|
| 1737 | old_pte = pte_next_pfn(old_pte);
|
| 1738 | pte = pte_next_pfn(pte);
|
| 1739 | }
|
| 1740 | }
|
| 1741 | #endif
|
| 1742 |
|
| 1743 | |
| 1744 | * Architectures can set this mask to a combination of PGTBL_P?D_MODIFIED values
|
| 1745 | * and let generic vmalloc, ioremap and page table update code know when
|
| 1746 | * arch_sync_kernel_mappings() needs to be called.
|
| 1747 |
|
| 1748 | #ifndef ARCH_PAGE_TABLE_SYNC_MASK
|
| 1749 | #define ARCH_PAGE_TABLE_SYNC_MASK 0
|
| 1750 | #endif
|
| 1751 |
|
| 1752 | |
| 1753 | * There is no default implementation for arch_sync_kernel_mappings(). It is
|
| 1754 | * relied upon the compiler to optimize calls out if ARCH_PAGE_TABLE_SYNC_MASK
|
| 1755 | * is 0.
|
| 1756 |
|
| 1757 | void arch_sync_kernel_mappings(unsigned long start, unsigned long end);
|
| 1758 |
|
| 1759 | #endif
|
| 1760 |
|
| 1761 | |
| 1762 | * On almost all architectures and configurations, 0 can be used as the
|
| 1763 | * upper ceiling to free_pgtables(): on many architectures it has the same
|
| 1764 | * effect as using TASK_SIZE. However, there is one configuration which
|
| 1765 | * must impose a more careful limit, to avoid freeing kernel pgtables.
|
| 1766 |
|
| 1767 | #ifndef USER_PGTABLES_CEILING
|
| 1768 | #define USER_PGTABLES_CEILING 0UL
|
| 1769 | #endif
|
| 1770 |
|
| 1771 | |
| 1772 | * This defines the first usable user address. Platforms
|
| 1773 | * can override its value with custom FIRST_USER_ADDRESS
|
| 1774 | * defined in their respective <asm/pgtable.h>.
|
| 1775 |
|
| 1776 | #ifndef FIRST_USER_ADDRESS
|
| 1777 | #define FIRST_USER_ADDRESS 0UL
|
| 1778 | #endif
|
| 1779 |
|
| 1780 | |
| 1781 | * No-op macros that just return the current protection value. Defined here
|
| 1782 | * because these macros can be used even if CONFIG_MMU is not defined.
|
| 1783 |
|
| 1784 |
|
| 1785 | #ifndef pgprot_nx
|
| 1786 | #define pgprot_nx(prot) (prot)
|
| 1787 | #endif
|
| 1788 |
|
| 1789 | #ifndef pgprot_noncached
|
| 1790 | #define pgprot_noncached(prot) (prot)
|
| 1791 | #endif
|
| 1792 |
|
| 1793 | #ifndef pgprot_writecombine
|
| 1794 | #define pgprot_writecombine pgprot_noncached
|
| 1795 | #endif
|
| 1796 |
|
| 1797 | #ifndef pgprot_writethrough
|
| 1798 | #define pgprot_writethrough pgprot_noncached
|
| 1799 | #endif
|
| 1800 |
|
| 1801 | #ifndef pgprot_device
|
| 1802 | #define pgprot_device pgprot_noncached
|
| 1803 | #endif
|
| 1804 |
|
| 1805 | #ifndef pgprot_mhp
|
| 1806 | #define pgprot_mhp(prot) (prot)
|
| 1807 | #endif
|
| 1808 |
|
| 1809 | #ifdef CONFIG_MMU
|
| 1810 | #ifndef pgprot_modify
|
| 1811 | #define pgprot_modify pgprot_modify
|
| 1812 | static inline pgprot_t pgprot_modify(pgprot_t oldprot, pgprot_t newprot)
|
| 1813 | {
|
| 1814 | if (pgprot_val(oldprot) == pgprot_val(pgprot_noncached(oldprot)))
|
| 1815 | newprot = pgprot_noncached(newprot);
|
| 1816 | if (pgprot_val(oldprot) == pgprot_val(pgprot_writecombine(oldprot)))
|
| 1817 | newprot = pgprot_writecombine(newprot);
|
| 1818 | if (pgprot_val(oldprot) == pgprot_val(pgprot_device(oldprot)))
|
| 1819 | newprot = pgprot_device(newprot);
|
| 1820 | return newprot;
|
| 1821 | }
|
| 1822 | #endif
|
| 1823 | #endif
|
| 1824 |
|
| 1825 | #ifndef pgprot_encrypted
|
| 1826 | #define pgprot_encrypted(prot) (prot)
|
| 1827 | #endif
|
| 1828 |
|
| 1829 | #ifndef pgprot_decrypted
|
| 1830 | #define pgprot_decrypted(prot) (prot)
|
| 1831 | #endif
|
| 1832 |
|
| 1833 | |
| 1834 | * A facility to provide batching of the reload of page tables and
|
| 1835 | * other process state with the actual context switch code for
|
| 1836 | * paravirtualized guests. By convention, only one of the batched
|
| 1837 | * update (lazy) modes (CPU, MMU) should be active at any given time,
|
| 1838 | * entry should never be nested, and entry and exits should always be
|
| 1839 | * paired. This is for sanity of maintaining and reasoning about the
|
| 1840 | * kernel code. In this case, the exit (end of the context switch) is
|
| 1841 | * in architecture-specific code, and so doesn't need a generic
|
| 1842 | * definition.
|
| 1843 |
|
| 1844 | #ifndef __HAVE_ARCH_START_CONTEXT_SWITCH
|
| 1845 | #define arch_start_context_switch(prev) do {} while (0)
|
| 1846 | #endif
|
| 1847 |
|
| 1848 | |
| 1849 | * Some platforms can customize the PTE soft-dirty bit making it unavailable
|
| 1850 | * even if the architecture provides the resource.
|
| 1851 | * Adding this API allows architectures to add their own checks for the
|
| 1852 | * devices on which the kernel is running.
|
| 1853 | * Note: When overriding it, please make sure the CONFIG_MEM_SOFT_DIRTY
|
| 1854 | * is part of this macro.
|
| 1855 |
|
| 1856 | #ifndef pgtable_supports_soft_dirty
|
| 1857 | #define pgtable_supports_soft_dirty() IS_ENABLED(CONFIG_MEM_SOFT_DIRTY)
|
| 1858 | #endif
|
| 1859 |
|
| 1860 | #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
|
| 1861 | #ifndef CONFIG_ARCH_ENABLE_THP_MIGRATION
|
| 1862 | static inline pmd_t pmd_swp_mksoft_dirty(pmd_t pmd)
|
| 1863 | {
|
| 1864 | return pmd;
|
| 1865 | }
|
| 1866 |
|
| 1867 | static inline int pmd_swp_soft_dirty(pmd_t pmd)
|
| 1868 | {
|
| 1869 | return 0;
|
| 1870 | }
|
| 1871 |
|
| 1872 | static inline pmd_t pmd_swp_clear_soft_dirty(pmd_t pmd)
|
| 1873 | {
|
| 1874 | return pmd;
|
| 1875 | }
|
| 1876 | #endif
|
| 1877 | #else
|
| 1878 | static inline int pte_soft_dirty(pte_t pte)
|
| 1879 | {
|
| 1880 | return 0;
|
| 1881 | }
|
| 1882 |
|
| 1883 | static inline int pmd_soft_dirty(pmd_t pmd)
|
| 1884 | {
|
| 1885 | return 0;
|
| 1886 | }
|
| 1887 |
|
| 1888 | static inline pte_t pte_mksoft_dirty(pte_t pte)
|
| 1889 | {
|
| 1890 | return pte;
|
| 1891 | }
|
| 1892 |
|
| 1893 | static inline pmd_t pmd_mksoft_dirty(pmd_t pmd)
|
| 1894 | {
|
| 1895 | return pmd;
|
| 1896 | }
|
| 1897 |
|
| 1898 | static inline pte_t pte_clear_soft_dirty(pte_t pte)
|
| 1899 | {
|
| 1900 | return pte;
|
| 1901 | }
|
| 1902 |
|
| 1903 | static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd)
|
| 1904 | {
|
| 1905 | return pmd;
|
| 1906 | }
|
| 1907 |
|
| 1908 | static inline pte_t pte_swp_mksoft_dirty(pte_t pte)
|
| 1909 | {
|
| 1910 | return pte;
|
| 1911 | }
|
| 1912 |
|
| 1913 | static inline int pte_swp_soft_dirty(pte_t pte)
|
| 1914 | {
|
| 1915 | return 0;
|
| 1916 | }
|
| 1917 |
|
| 1918 | static inline pte_t pte_swp_clear_soft_dirty(pte_t pte)
|
| 1919 | {
|
| 1920 | return pte;
|
| 1921 | }
|
| 1922 |
|
| 1923 | static inline pmd_t pmd_swp_mksoft_dirty(pmd_t pmd)
|
| 1924 | {
|
| 1925 | return pmd;
|
| 1926 | }
|
| 1927 |
|
| 1928 | static inline int pmd_swp_soft_dirty(pmd_t pmd)
|
| 1929 | {
|
| 1930 | return 0;
|
| 1931 | }
|
| 1932 |
|
| 1933 | static inline pmd_t pmd_swp_clear_soft_dirty(pmd_t pmd)
|
| 1934 | {
|
| 1935 | return pmd;
|
| 1936 | }
|
| 1937 | #endif
|
| 1938 |
|
| 1939 | #ifndef __HAVE_PFNMAP_TRACKING
|
| 1940 | |
| 1941 | * Interfaces that can be used by architecture code to keep track of
|
| 1942 | * memory type of pfn mappings specified by the remap_pfn_range,
|
| 1943 | * vmf_insert_pfn.
|
| 1944 |
|
| 1945 |
|
| 1946 | static inline int pfnmap_setup_cachemode(unsigned long pfn, unsigned long size,
|
| 1947 | pgprot_t *prot)
|
| 1948 | {
|
| 1949 | return 0;
|
| 1950 | }
|
| 1951 |
|
| 1952 | static inline int pfnmap_track(unsigned long pfn, unsigned long size,
|
| 1953 | pgprot_t *prot)
|
| 1954 | {
|
| 1955 | return 0;
|
| 1956 | }
|
| 1957 |
|
| 1958 | static inline void pfnmap_untrack(unsigned long pfn, unsigned long size)
|
| 1959 | {
|
| 1960 | }
|
| 1961 | #else
|
| 1962 | |
| 1963 | * pfnmap_setup_cachemode - setup the cachemode in the pgprot for a pfn range
|
| 1964 | * @pfn: the start of the pfn range
|
| 1965 | * @size: the size of the pfn range in bytes
|
| 1966 | * @prot: the pgprot to modify
|
| 1967 | *
|
| 1968 | * Lookup the cachemode for the pfn range starting at @pfn with the size
|
| 1969 | * @size and store it in @prot, leaving other data in @prot unchanged.
|
| 1970 | *
|
| 1971 | * This allows for a hardware implementation to have fine-grained control of
|
| 1972 | * memory cache behavior at page level granularity. Without a hardware
|
| 1973 | * implementation, this function does nothing.
|
| 1974 | *
|
| 1975 | * Currently there is only one implementation for this - x86 Page Attribute
|
| 1976 | * Table (PAT). See Documentation/arch/x86/pat.rst for more details.
|
| 1977 | *
|
| 1978 | * This function can fail if the pfn range spans pfns that require differing
|
| 1979 | * cachemodes. If the pfn range was previously verified to have a single
|
| 1980 | * cachemode, it is sufficient to query only a single pfn. The assumption is
|
| 1981 | * that this is the case for drivers using the vmf_insert_pfn*() interface.
|
| 1982 | *
|
| 1983 | * Returns 0 on success and -EINVAL on error.
|
| 1984 |
|
| 1985 | int pfnmap_setup_cachemode(unsigned long pfn, unsigned long size,
|
| 1986 | pgprot_t *prot);
|
| 1987 |
|
| 1988 | |
| 1989 | * pfnmap_track - track a pfn range
|
| 1990 | * @pfn: the start of the pfn range
|
| 1991 | * @size: the size of the pfn range in bytes
|
| 1992 | * @prot: the pgprot to track
|
| 1993 | *
|
| 1994 | * Requested the pfn range to be 'tracked' by a hardware implementation and
|
| 1995 | * setup the cachemode in @prot similar to pfnmap_setup_cachemode().
|
| 1996 | *
|
| 1997 | * This allows for fine-grained control of memory cache behaviour at page
|
| 1998 | * level granularity. Tracking memory this way is persisted across VMA splits
|
| 1999 | * (VMA merging does not apply for VM_PFNMAP).
|
| 2000 | *
|
| 2001 | * Currently, there is only one implementation for this - x86 Page Attribute
|
| 2002 | * Table (PAT). See Documentation/arch/x86/pat.rst for more details.
|
| 2003 | *
|
| 2004 | * Returns 0 on success and -EINVAL on error.
|
| 2005 |
|
| 2006 | int pfnmap_track(unsigned long pfn, unsigned long size, pgprot_t *prot);
|
| 2007 |
|
| 2008 | |
| 2009 | * pfnmap_untrack - untrack a pfn range
|
| 2010 | * @pfn: the start of the pfn range
|
| 2011 | * @size: the size of the pfn range in bytes
|
| 2012 | *
|
| 2013 | * Untrack a pfn range previously tracked through pfnmap_track().
|
| 2014 |
|
| 2015 | void pfnmap_untrack(unsigned long pfn, unsigned long size);
|
| 2016 | #endif
|
| 2017 |
|
| 2018 | |
| 2019 | * pfnmap_setup_cachemode_pfn - setup the cachemode in the pgprot for a pfn
|
| 2020 | * @pfn: the pfn
|
| 2021 | * @prot: the pgprot to modify
|
| 2022 | *
|
| 2023 | * Lookup the cachemode for @pfn and store it in @prot, leaving other
|
| 2024 | * data in @prot unchanged.
|
| 2025 | *
|
| 2026 | * See pfnmap_setup_cachemode() for details.
|
| 2027 |
|
| 2028 | static inline void pfnmap_setup_cachemode_pfn(unsigned long pfn, pgprot_t *prot)
|
| 2029 | {
|
| 2030 | pfnmap_setup_cachemode(pfn, PAGE_SIZE, prot);
|
| 2031 | }
|
| 2032 |
|
| 2033 | |
| 2034 | * ZERO_PAGE() is global shared page(s) that is always zero. It is used for
|
| 2035 | * zero-mapped memory areas, CoW etc.
|
| 2036 | *
|
| 2037 | * On architectures that __HAVE_COLOR_ZERO_PAGE there are several such pages
|
| 2038 | * for different ranges in the virtual address space.
|
| 2039 | *
|
| 2040 | * zero_page_pfn identifies the first (or the only) pfn for these pages.
|
| 2041 | *
|
| 2042 | * For architectures that don't __HAVE_COLOR_ZERO_PAGE the zero page lives in
|
| 2043 | * empty_zero_page in BSS.
|
| 2044 |
|
| 2045 | void arch_setup_zero_pages(void);
|
| 2046 |
|
| 2047 | #ifdef __HAVE_COLOR_ZERO_PAGE
|
| 2048 | static inline int is_zero_pfn(unsigned long pfn)
|
| 2049 | {
|
| 2050 | extern unsigned long zero_page_pfn;
|
| 2051 | unsigned long offset_from_zero_pfn = pfn - zero_page_pfn;
|
| 2052 |
|
| 2053 | return offset_from_zero_pfn <= (zero_page_mask >> PAGE_SHIFT);
|
| 2054 | }
|
| 2055 |
|
| 2056 | #define zero_pfn(addr) page_to_pfn(ZERO_PAGE(addr))
|
| 2057 |
|
| 2058 | #else
|
| 2059 | static inline int is_zero_pfn(unsigned long pfn)
|
| 2060 | {
|
| 2061 | extern unsigned long zero_page_pfn;
|
| 2062 |
|
| 2063 | return pfn == zero_page_pfn;
|
| 2064 | }
|
| 2065 |
|
| 2066 | static inline unsigned long zero_pfn(unsigned long addr)
|
| 2067 | {
|
| 2068 | extern unsigned long zero_page_pfn;
|
| 2069 |
|
| 2070 | return zero_page_pfn;
|
| 2071 | }
|
| 2072 |
|
| 2073 | extern const uint8_t empty_zero_page[PAGE_SIZE];
|
| 2074 | extern struct page *__zero_page;
|
| 2075 |
|
| 2076 | static inline struct page *_zero_page(unsigned long addr)
|
| 2077 | {
|
| 2078 | return __zero_page;
|
| 2079 | }
|
| 2080 | #define ZERO_PAGE(vaddr) _zero_page(vaddr)
|
| 2081 |
|
| 2082 | #endif
|
| 2083 |
|
| 2084 | #ifdef CONFIG_MMU
|
| 2085 |
|
| 2086 | #ifndef CONFIG_TRANSPARENT_HUGEPAGE
|
| 2087 | static inline int pmd_trans_huge(pmd_t pmd)
|
| 2088 | {
|
| 2089 | return 0;
|
| 2090 | }
|
| 2091 | #ifndef pmd_write
|
| 2092 | static inline int pmd_write(pmd_t pmd)
|
| 2093 | {
|
| 2094 | BUG();
|
| 2095 | return 0;
|
| 2096 | }
|
| 2097 | #endif
|
| 2098 | #endif
|
| 2099 |
|
| 2100 | #ifndef pud_write
|
| 2101 | static inline int pud_write(pud_t pud)
|
| 2102 | {
|
| 2103 | BUG();
|
| 2104 | return 0;
|
| 2105 | }
|
| 2106 | #endif
|
| 2107 |
|
| 2108 | #if !defined(CONFIG_TRANSPARENT_HUGEPAGE) || \
|
| 2109 | !defined(CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD)
|
| 2110 | static inline int pud_trans_huge(pud_t pud)
|
| 2111 | {
|
| 2112 | return 0;
|
| 2113 | }
|
| 2114 | #endif
|
| 2115 |
|
| 2116 | static inline int pud_trans_unstable(pud_t *pud)
|
| 2117 | {
|
| 2118 | #if defined(CONFIG_TRANSPARENT_HUGEPAGE) && \
|
| 2119 | defined(CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD)
|
| 2120 | pud_t pudval = pudp_get(pud);
|
| 2121 |
|
| 2122 | if (pud_none(pudval) || pud_trans_huge(pudval))
|
| 2123 | return 1;
|
| 2124 | if (unlikely(pud_bad(pudval))) {
|
| 2125 | pud_clear_bad(pud);
|
| 2126 | return 1;
|
| 2127 | }
|
| 2128 | #endif
|
| 2129 | return 0;
|
| 2130 | }
|
| 2131 |
|
| 2132 | #ifndef CONFIG_NUMA_BALANCING
|
| 2133 | |
| 2134 | * In an inaccessible (PROT_NONE) VMA, pte_protnone() may indicate "yes". It is
|
| 2135 | * perfectly valid to indicate "no" in that case, which is why our default
|
| 2136 | * implementation defaults to "always no".
|
| 2137 | *
|
| 2138 | * In an accessible VMA, however, pte_protnone() reliably indicates PROT_NONE
|
| 2139 | * page protection due to NUMA hinting. NUMA hinting faults only apply in
|
| 2140 | * accessible VMAs.
|
| 2141 | *
|
| 2142 | * So, to reliably identify PROT_NONE PTEs that require a NUMA hinting fault,
|
| 2143 | * looking at the VMA accessibility is sufficient.
|
| 2144 |
|
| 2145 | static inline int pte_protnone(pte_t pte)
|
| 2146 | {
|
| 2147 | return 0;
|
| 2148 | }
|
| 2149 |
|
| 2150 | static inline int pmd_protnone(pmd_t pmd)
|
| 2151 | {
|
| 2152 | return 0;
|
| 2153 | }
|
| 2154 | #endif
|
| 2155 |
|
| 2156 | #endif
|
| 2157 |
|
| 2158 | #ifdef CONFIG_HAVE_ARCH_HUGE_VMAP
|
| 2159 |
|
| 2160 | #ifndef __PAGETABLE_P4D_FOLDED
|
| 2161 | int p4d_set_huge(p4d_t *p4d, phys_addr_t addr, pgprot_t prot);
|
| 2162 | void p4d_clear_huge(p4d_t *p4d);
|
| 2163 | #else
|
| 2164 | static inline int p4d_set_huge(p4d_t *p4d, phys_addr_t addr, pgprot_t prot)
|
| 2165 | {
|
| 2166 | return 0;
|
| 2167 | }
|
| 2168 | static inline void p4d_clear_huge(p4d_t *p4d) { }
|
| 2169 | #endif
|
| 2170 |
|
| 2171 | int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot);
|
| 2172 | int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot);
|
| 2173 | int pud_clear_huge(pud_t *pud);
|
| 2174 | int pmd_clear_huge(pmd_t *pmd);
|
| 2175 | int p4d_free_pud_page(p4d_t *p4d, unsigned long addr);
|
| 2176 | int pud_free_pmd_page(pud_t *pud, unsigned long addr);
|
| 2177 | int pmd_free_pte_page(pmd_t *pmd, unsigned long addr);
|
| 2178 | #else
|
| 2179 | static inline int p4d_set_huge(p4d_t *p4d, phys_addr_t addr, pgprot_t prot)
|
| 2180 | {
|
| 2181 | return 0;
|
| 2182 | }
|
| 2183 | static inline int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot)
|
| 2184 | {
|
| 2185 | return 0;
|
| 2186 | }
|
| 2187 | static inline int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot)
|
| 2188 | {
|
| 2189 | return 0;
|
| 2190 | }
|
| 2191 | static inline void p4d_clear_huge(p4d_t *p4d) { }
|
| 2192 | static inline int pud_clear_huge(pud_t *pud)
|
| 2193 | {
|
| 2194 | return 0;
|
| 2195 | }
|
| 2196 | static inline int pmd_clear_huge(pmd_t *pmd)
|
| 2197 | {
|
| 2198 | return 0;
|
| 2199 | }
|
| 2200 | static inline int p4d_free_pud_page(p4d_t *p4d, unsigned long addr)
|
| 2201 | {
|
| 2202 | return 0;
|
| 2203 | }
|
| 2204 | static inline int pud_free_pmd_page(pud_t *pud, unsigned long addr)
|
| 2205 | {
|
| 2206 | return 0;
|
| 2207 | }
|
| 2208 | static inline int pmd_free_pte_page(pmd_t *pmd, unsigned long addr)
|
| 2209 | {
|
| 2210 | return 0;
|
| 2211 | }
|
| 2212 | #endif
|
| 2213 |
|
| 2214 | #ifndef __HAVE_ARCH_FLUSH_PMD_TLB_RANGE
|
| 2215 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE
|
| 2216 | |
| 2217 | * ARCHes with special requirements for evicting THP backing TLB entries can
|
| 2218 | * implement this. Otherwise also, it can help optimize normal TLB flush in
|
| 2219 | * THP regime. Stock flush_tlb_range() typically has optimization to nuke the
|
| 2220 | * entire TLB if flush span is greater than a threshold, which will
|
| 2221 | * likely be true for a single huge page. Thus a single THP flush will
|
| 2222 | * invalidate the entire TLB which is not desirable.
|
| 2223 | * e.g. see arch/arc: flush_pmd_tlb_range
|
| 2224 |
|
| 2225 | #define flush_pmd_tlb_range(vma, addr, end) flush_tlb_range(vma, addr, end)
|
| 2226 | #define flush_pud_tlb_range(vma, addr, end) flush_tlb_range(vma, addr, end)
|
| 2227 | #else
|
| 2228 | #define flush_pmd_tlb_range(vma, addr, end) BUILD_BUG()
|
| 2229 | #define flush_pud_tlb_range(vma, addr, end) BUILD_BUG()
|
| 2230 | #endif
|
| 2231 | #endif
|
| 2232 |
|
| 2233 | struct file;
|
| 2234 | int phys_mem_access_prot_allowed(struct file *file, unsigned long pfn,
|
| 2235 | unsigned long size, pgprot_t *vma_prot);
|
| 2236 |
|
| 2237 | #ifndef CONFIG_X86_ESPFIX64
|
| 2238 | static inline void init_espfix_bsp(void) { }
|
| 2239 | #endif
|
| 2240 |
|
| 2241 | extern void __init pgtable_cache_init(void);
|
| 2242 |
|
| 2243 | #ifndef __HAVE_ARCH_PFN_MODIFY_ALLOWED
|
| 2244 | static inline bool pfn_modify_allowed(unsigned long pfn, pgprot_t prot)
|
| 2245 | {
|
| 2246 | return true;
|
| 2247 | }
|
| 2248 |
|
| 2249 | static inline bool arch_has_pfn_modify_check(void)
|
| 2250 | {
|
| 2251 | return false;
|
| 2252 | }
|
| 2253 | #endif
|
| 2254 |
|
| 2255 | |
| 2256 | * Architecture PAGE_KERNEL_* fallbacks
|
| 2257 | *
|
| 2258 | * Some architectures don't define certain PAGE_KERNEL_* flags. This is either
|
| 2259 | * because they really don't support them, or the port needs to be updated to
|
| 2260 | * reflect the required functionality. Below are a set of relatively safe
|
| 2261 | * fallbacks, as best effort, which we can count on in lieu of the architectures
|
| 2262 | * not defining them on their own yet.
|
| 2263 |
|
| 2264 |
|
| 2265 | #ifndef PAGE_KERNEL_RO
|
| 2266 | # define PAGE_KERNEL_RO PAGE_KERNEL
|
| 2267 | #endif
|
| 2268 |
|
| 2269 | #ifndef PAGE_KERNEL_EXEC
|
| 2270 | # define PAGE_KERNEL_EXEC PAGE_KERNEL
|
| 2271 | #endif
|
| 2272 |
|
| 2273 | |
| 2274 | * Page Table Modification bits for pgtbl_mod_mask.
|
| 2275 | *
|
| 2276 | * These are used by the p?d_alloc_track*() and p*d_populate_kernel()
|
| 2277 | * functions in the generic vmalloc, ioremap and page table update code
|
| 2278 | * to track at which page-table levels entries have been modified.
|
| 2279 | * Based on that the code can better decide when page table changes need
|
| 2280 | * to be synchronized to other page-tables in the system.
|
| 2281 |
|
| 2282 | #define __PGTBL_PGD_MODIFIED 0
|
| 2283 | #define __PGTBL_P4D_MODIFIED 1
|
| 2284 | #define __PGTBL_PUD_MODIFIED 2
|
| 2285 | #define __PGTBL_PMD_MODIFIED 3
|
| 2286 | #define __PGTBL_PTE_MODIFIED 4
|
| 2287 |
|
| 2288 | #define PGTBL_PGD_MODIFIED BIT(__PGTBL_PGD_MODIFIED)
|
| 2289 | #define PGTBL_P4D_MODIFIED BIT(__PGTBL_P4D_MODIFIED)
|
| 2290 | #define PGTBL_PUD_MODIFIED BIT(__PGTBL_PUD_MODIFIED)
|
| 2291 | #define PGTBL_PMD_MODIFIED BIT(__PGTBL_PMD_MODIFIED)
|
| 2292 | #define PGTBL_PTE_MODIFIED BIT(__PGTBL_PTE_MODIFIED)
|
| 2293 |
|
| 2294 |
|
| 2295 | typedef unsigned int pgtbl_mod_mask;
|
| 2296 |
|
| 2297 | enum pgtable_level {
|
| 2298 | PGTABLE_LEVEL_PTE = 0,
|
| 2299 | PGTABLE_LEVEL_PMD,
|
| 2300 | PGTABLE_LEVEL_PUD,
|
| 2301 | PGTABLE_LEVEL_P4D,
|
| 2302 | PGTABLE_LEVEL_PGD,
|
| 2303 | };
|
| 2304 |
|
| 2305 | static inline const char *pgtable_level_to_str(enum pgtable_level level)
|
| 2306 | {
|
| 2307 | switch (level) {
|
| 2308 | case PGTABLE_LEVEL_PTE:
|
| 2309 | return "pte";
|
| 2310 | case PGTABLE_LEVEL_PMD:
|
| 2311 | return "pmd";
|
| 2312 | case PGTABLE_LEVEL_PUD:
|
| 2313 | return "pud";
|
| 2314 | case PGTABLE_LEVEL_P4D:
|
| 2315 | return "p4d";
|
| 2316 | case PGTABLE_LEVEL_PGD:
|
| 2317 | return "pgd";
|
| 2318 | default:
|
| 2319 | return "unknown";
|
| 2320 | }
|
| 2321 | }
|
| 2322 |
|
| 2323 | #endif
|
| 2324 |
|
| 2325 | #if !defined(MAX_POSSIBLE_PHYSMEM_BITS) && !defined(CONFIG_64BIT)
|
| 2326 | #ifdef CONFIG_PHYS_ADDR_T_64BIT
|
| 2327 | |
| 2328 | * ZSMALLOC needs to know the highest PFN on 32-bit architectures
|
| 2329 | * with physical address space extension, but falls back to
|
| 2330 | * BITS_PER_LONG otherwise.
|
| 2331 |
|
| 2332 | #error Missing MAX_POSSIBLE_PHYSMEM_BITS definition
|
| 2333 | #else
|
| 2334 | #define MAX_POSSIBLE_PHYSMEM_BITS 32
|
| 2335 | #endif
|
| 2336 | #endif
|
| 2337 |
|
| 2338 | #ifndef has_transparent_hugepage
|
| 2339 | #define has_transparent_hugepage() IS_BUILTIN(CONFIG_TRANSPARENT_HUGEPAGE)
|
| 2340 | #endif
|
| 2341 |
|
| 2342 | #ifndef has_transparent_pud_hugepage
|
| 2343 | #define has_transparent_pud_hugepage() IS_BUILTIN(CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD)
|
| 2344 | #endif
|
| 2345 | |
| 2346 | * On some architectures it depends on the mm if the p4d/pud or pmd
|
| 2347 | * layer of the page table hierarchy is folded or not.
|
| 2348 |
|
| 2349 | #ifndef mm_p4d_folded
|
| 2350 | #define mm_p4d_folded(mm) __is_defined(__PAGETABLE_P4D_FOLDED)
|
| 2351 | #endif
|
| 2352 |
|
| 2353 | #ifndef mm_pud_folded
|
| 2354 | #define mm_pud_folded(mm) __is_defined(__PAGETABLE_PUD_FOLDED)
|
| 2355 | #endif
|
| 2356 |
|
| 2357 | #ifndef mm_pmd_folded
|
| 2358 | #define mm_pmd_folded(mm) __is_defined(__PAGETABLE_PMD_FOLDED)
|
| 2359 | #endif
|
| 2360 |
|
| 2361 | #ifndef p4d_offset_lockless
|
| 2362 | #define p4d_offset_lockless(pgdp, pgd, address) p4d_offset(&(pgd), address)
|
| 2363 | #endif
|
| 2364 | #ifndef pud_offset_lockless
|
| 2365 | #define pud_offset_lockless(p4dp, p4d, address) pud_offset(&(p4d), address)
|
| 2366 | #endif
|
| 2367 | #ifndef pmd_offset_lockless
|
| 2368 | #define pmd_offset_lockless(pudp, pud, address) pmd_offset(&(pud), address)
|
| 2369 | #endif
|
| 2370 |
|
| 2371 | |
| 2372 | * pXd_leaf() is the API to check whether a pgtable entry is a huge page
|
| 2373 | * mapping. It should work globally across all archs, without any
|
| 2374 | * dependency on CONFIG_* options. For architectures that do not support
|
| 2375 | * huge mappings on specific levels, below fallbacks will be used.
|
| 2376 | *
|
| 2377 | * A leaf pgtable entry should always imply the following:
|
| 2378 | *
|
| 2379 | * - It is a "present" entry. IOW, before using this API, please check it
|
| 2380 | * with pXd_present() first. NOTE: it may not always mean the "present
|
| 2381 | * bit" is set. For example, PROT_NONE entries are always "present".
|
| 2382 | *
|
| 2383 | * - It should _never_ be a swap entry of any type. Above "present" check
|
| 2384 | * should have guarded this, but let's be crystal clear on this.
|
| 2385 | *
|
| 2386 | * - It should contain a huge PFN, which points to a huge page larger than
|
| 2387 | * PAGE_SIZE of the platform. The PFN format isn't important here.
|
| 2388 | *
|
| 2389 | * - It should cover all kinds of huge mappings (i.e. pXd_trans_huge()
|
| 2390 | * or hugetlb mappings).
|
| 2391 |
|
| 2392 | #ifndef pgd_leaf
|
| 2393 | #define pgd_leaf(x) false
|
| 2394 | #endif
|
| 2395 | #ifndef p4d_leaf
|
| 2396 | #define p4d_leaf(x) false
|
| 2397 | #endif
|
| 2398 | #ifndef pud_leaf
|
| 2399 | #define pud_leaf(x) false
|
| 2400 | #endif
|
| 2401 | #ifndef pmd_leaf
|
| 2402 | #define pmd_leaf(x) false
|
| 2403 | #endif
|
| 2404 |
|
| 2405 | #ifndef pgd_leaf_size
|
| 2406 | #define pgd_leaf_size(x) (1ULL << PGDIR_SHIFT)
|
| 2407 | #endif
|
| 2408 | #ifndef p4d_leaf_size
|
| 2409 | #define p4d_leaf_size(x) P4D_SIZE
|
| 2410 | #endif
|
| 2411 | #ifndef pud_leaf_size
|
| 2412 | #define pud_leaf_size(x) PUD_SIZE
|
| 2413 | #endif
|
| 2414 | #ifndef pmd_leaf_size
|
| 2415 | #define pmd_leaf_size(x) PMD_SIZE
|
| 2416 | #endif
|
| 2417 | #ifndef __pte_leaf_size
|
| 2418 | #ifndef pte_leaf_size
|
| 2419 | #define pte_leaf_size(x) PAGE_SIZE
|
| 2420 | #endif
|
| 2421 | #define __pte_leaf_size(x,y) pte_leaf_size(y)
|
| 2422 | #endif
|
| 2423 |
|
| 2424 | |
| 2425 | * We always define pmd_pfn for all archs as it's used in lots of generic
|
| 2426 | * code. Now it happens too for pud_pfn (and can happen for larger
|
| 2427 | * mappings too in the future; we're not there yet). Instead of defining
|
| 2428 | * it for all archs (like pmd_pfn), provide a fallback.
|
| 2429 | *
|
| 2430 | * Note that returning 0 here means any arch that didn't define this can
|
| 2431 | * get severely wrong when it hits a real pud leaf. It's arch's
|
| 2432 | * responsibility to properly define it when a huge pud is possible.
|
| 2433 |
|
| 2434 | #ifndef pud_pfn
|
| 2435 | #define pud_pfn(x) 0
|
| 2436 | #endif
|
| 2437 |
|
| 2438 | |
| 2439 | * Some architectures have MMUs that are configurable or selectable at boot
|
| 2440 | * time. These lead to variable PTRS_PER_x. For statically allocated arrays it
|
| 2441 | * helps to have a static maximum value.
|
| 2442 |
|
| 2443 |
|
| 2444 | #ifndef MAX_PTRS_PER_PTE
|
| 2445 | #define MAX_PTRS_PER_PTE PTRS_PER_PTE
|
| 2446 | #endif
|
| 2447 |
|
| 2448 | #ifndef MAX_PTRS_PER_PMD
|
| 2449 | #define MAX_PTRS_PER_PMD PTRS_PER_PMD
|
| 2450 | #endif
|
| 2451 |
|
| 2452 | #ifndef MAX_PTRS_PER_PUD
|
| 2453 | #define MAX_PTRS_PER_PUD PTRS_PER_PUD
|
| 2454 | #endif
|
| 2455 |
|
| 2456 | #ifndef MAX_PTRS_PER_P4D
|
| 2457 | #define MAX_PTRS_PER_P4D PTRS_PER_P4D
|
| 2458 | #endif
|
| 2459 |
|
| 2460 | #ifndef pte_pgprot
|
| 2461 | #define pte_pgprot(x) ((pgprot_t) {0})
|
| 2462 | #endif
|
| 2463 |
|
| 2464 | #ifndef pmd_pgprot
|
| 2465 | #define pmd_pgprot(x) ((pgprot_t) {0})
|
| 2466 | #endif
|
| 2467 |
|
| 2468 | #ifndef pud_pgprot
|
| 2469 | #define pud_pgprot(x) ((pgprot_t) {0})
|
| 2470 | #endif
|
| 2471 |
|
| 2472 | |
| 2473 | * this is due to the limited x86 page protection hardware. The expected
|
| 2474 | * behavior is in parens:
|
| 2475 | *
|
| 2476 | * map_type prot
|
| 2477 | * PROT_NONE PROT_READ PROT_WRITE PROT_EXEC
|
| 2478 | * MAP_SHARED r: (no) no r: (yes) yes r: (no) yes r: (no) yes
|
| 2479 | * w: (no) no w: (no) no w: (yes) yes w: (no) no
|
| 2480 | * x: (no) no x: (no) yes x: (no) yes x: (yes) yes
|
| 2481 | *
|
| 2482 | * MAP_PRIVATE r: (no) no r: (yes) yes r: (no) yes r: (no) yes
|
| 2483 | * w: (no) no w: (no) no w: (copy) copy w: (no) no
|
| 2484 | * x: (no) no x: (no) yes x: (no) yes x: (yes) yes
|
| 2485 | *
|
| 2486 | * On arm64, PROT_EXEC has the following behaviour for both MAP_SHARED and
|
| 2487 | * MAP_PRIVATE (with Enhanced PAN supported):
|
| 2488 | * r: (no) no
|
| 2489 | * w: (no) no
|
| 2490 | * x: (yes) yes
|
| 2491 |
|
| 2492 | #define DECLARE_VM_GET_PAGE_PROT \
|
| 2493 | pgprot_t vm_get_page_prot(vm_flags_t vm_flags) \
|
| 2494 | { \
|
| 2495 | return protection_map[vm_flags & \
|
| 2496 | (VM_READ | VM_WRITE | VM_EXEC | VM_SHARED)]; \
|
| 2497 | } \
|
| 2498 | EXPORT_SYMBOL(vm_get_page_prot);
|
| 2499 |
|
| 2500 | #endif
|