Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

0eff4589 · Linus Torvalds <[email protected]> · 2016-05-20 20:18:12 -07:00

Pull clk updates from Stephen Boyd:
 "It's the usual big pile of driver updates and additions, but we do
  have a couple core changes in here as well.

  Core:

   - CLK_IS_CRITICAL support has been added.  This should allow drivers
     to properly express that a certain clk should stay on even if their
     prepare/enable count drops to 0 (and in turn the parents of these
     clks should stay enabled).

   - A clk registration API has been added, clk_hw_register(), and an OF
     clk provider API has been added, of_clk_add_hw_provider().  These
     APIs have been put in place to further split clk providers from clk
     consumers, with the goal being to have clk providers never deal
     with struct clk pointers at all.  Conversion of provider drivers is
     on going.  clkdev has also gained support for registering clk_hw
     pointers directly so we can convert drivers that don't use
     devicetree.

  New Drivers:

   - Marvell ap806 and cp110 system controllers (with clks inside!)
   - Hisilicon Hi3519 clock and reset controller
   - Axis ARTPEC-6 clock controllers
   - Oxford Semiconductor OXNAS clock controllers
   - AXS10X I2S PLL
   - Rockchip RK3399 clock and reset controller

  Updates:

   - MMC2 and UART2 clks on Samsung Exynos 3250, ACLK on Samsung Exynos
     542x SoCs, and some more clk ID exporting for bus frequency scaling
   - Proper BCM2835 PCM clk support and various other clks
   - i.MX clk updates for i.MX6SX, i.MX7, and VF610
   - Renesas updates for R-Car H3
   - Tegra210 got updates for DisplayPort and HDMI 2.0
   - Rockchip driver refactorings and fixes due to adding RK3399 support"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (139 commits)
  clk: fix critical clock locking
  clk: qcom: mmcc-8996: Remove clocks that should be controlled by RPM
  clk: ingenic: Allow divider value to be divided
  clk: sunxi: Add display and TCON0 clocks driver
  clk: rockchip: drop old_rate calculation on pll rate changes
  clk: rockchip: simplify GRF handling in pll clocks
  clk: rockchip: lookup General Register Files in rockchip_clk_init
  clk: rockchip: fix the rk3399 sdmmc sample / drv name
  clk: mvebu: new driver for Armada CP110 system controller
  dt-bindings: arm: add DT binding for Marvell CP110 system controller
  clk: mvebu: new driver for Armada AP806 system controller
  clk: hisilicon: add CRG driver for hi3519 soc
  clk: hisilicon: export some hisilicon APIs to modules
  reset: hisilicon: add reset controller driver for hisilicon SOCs
  clk: bcm/kona: Do not use sizeof on pointer type
  clk: qcom: msm8916: Fix crypto clock flags
  clk: nxp: lpc18xx: Initialize clk_init_data::flags to 0
  clk/axs10x: Add I2S PLL clock driver
  clk: imx7d: fix ahb clock mux 1
  clk: fix comment of devm_clk_hw_register()
  ...

Commit: 0eff4589c36edd03d50b835d0768b2c2ef3f20bd
Parents: 087afe8a · ef56b79b

Merge commit. Changes below are compared with the first parent: 087afe8a.

Changes

136 files changed · +7164 −1122

File	Status	Add	Del	Content
Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt	added	+35	−0	View file
Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt	added	+83	−0	View file
Documentation/devicetree/bindings/clock/artpec6.txt	added	+41	−0	View file
Documentation/devicetree/bindings/clock/axs10x-i2s-pll-clock.txt	added	+25	−0	View file
Documentation/devicetree/bindings/clock/hi3519-crg.txt	added	+46	−0	View file
Documentation/devicetree/bindings/clock/imx35-clock.txt	modified	+1	−0	View file
Documentation/devicetree/bindings/clock/oxnas,stdclk.txt	added	+35	−0	View file
Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt	added	+62	−0	View file
Documentation/devicetree/bindings/clock/sunxi.txt	modified	+6	−0	View file
Documentation/driver-model/devres.txt	modified	+1	−0	View file
MAINTAINERS	modified	+1	−1	View file
drivers/clk/Kconfig	modified	+6	−0	View file
drivers/clk/Makefile	modified	+4	−1	View file
drivers/clk/at91/clk-h32mx.c	modified	+1	−1	View file
drivers/clk/axis/Makefile	added	+1	−0	View file
drivers/clk/axis/clk-artpec6.c	added	+242	−0	View file
drivers/clk/axs10x/Makefile	added	+1	−0	View file
drivers/clk/axs10x/i2s_pll_clock.c	added	+228	−0	View file
drivers/clk/bcm/clk-bcm2835.c	modified	+722	−493	View file
drivers/clk/bcm/clk-kona-setup.c	modified	+2	−1	View file
drivers/clk/clk-clps711x.c	modified	+8	−11	View file
drivers/clk/clk-composite.c	modified	+81	−12	View file
drivers/clk/clk-divider.c	modified	+83	−8	View file
drivers/clk/clk-fixed-factor.c	modified	+35	−7	View file
drivers/clk/clk-fixed-rate.c	modified	+36	−8	View file
drivers/clk/clk-fractional-divider.c	modified	+35	−5	View file
drivers/clk/clk-gate.c	modified	+36	−7	View file
drivers/clk/clk-gpio.c	modified	+41	−11	View file
drivers/clk/clk-ls1x.c	modified	+1	−2	View file
drivers/clk/clk-mux.c	modified	+51	−6	View file
drivers/clk/clk-nspire.c	modified	+1	−2	View file
drivers/clk/clk-oxnas.c	added	+195	−0	View file
drivers/clk/clk-palmas.c	modified	+2	−2	View file
drivers/clk/clk-qoriq.c	modified	+3	−2	View file
drivers/clk/clk-rk808.c	modified	+0	−1	View file
drivers/clk/clk-tango4.c	modified	+48	−25	View file
drivers/clk/clk-twl6040.c	modified	+0	−1	View file
drivers/clk/clk-wm831x.c	modified	+0	−1	View file
drivers/clk/clk-xgene.c	modified	+1	−1	View file
drivers/clk/clk.c	modified	+218	−4	View file
drivers/clk/clkdev.c	modified	+56	−19	View file
drivers/clk/hisilicon/Kconfig	modified	+15	−0	View file
drivers/clk/hisilicon/Makefile	modified	+2	−0	View file
drivers/clk/hisilicon/clk-hi3519.c	added	+131	−0	View file
drivers/clk/hisilicon/clk.c	modified	+15	−8	View file
drivers/clk/hisilicon/clk.h	modified	+7	−7	View file
drivers/clk/hisilicon/reset.c	added	+134	−0	View file
drivers/clk/hisilicon/reset.h	added	+36	−0	View file
drivers/clk/imx/clk-gate2.c	modified	+5	−2	View file
drivers/clk/imx/clk-imx35.c	modified	+2	−2	View file
drivers/clk/imx/clk-imx6sx.c	modified	+6	−4	View file
drivers/clk/imx/clk-imx7d.c	modified	+3	−2	View file
drivers/clk/imx/clk-pllv3.c	modified	+8	−1	View file
drivers/clk/imx/clk-vf610.c	modified	+58	−2	View file
drivers/clk/imx/clk.h	modified	+10	−3	View file
drivers/clk/ingenic/cgu.c	modified	+10	−1	View file
drivers/clk/ingenic/cgu.h	modified	+5	−1	View file
drivers/clk/ingenic/jz4740-cgu.c	modified	+12	−12	View file
drivers/clk/ingenic/jz4780-cgu.c	modified	+20	−20	View file
drivers/clk/meson/meson8b-clkc.c	modified	+3	−3	View file
drivers/clk/mmp/clk-mmp2.c	modified	+5	−9	View file
drivers/clk/mmp/clk-of-mmp2.c	modified	+5	−5	View file
drivers/clk/mmp/clk-of-pxa168.c	modified	+4	−4	View file
drivers/clk/mmp/clk-of-pxa1928.c	modified	+6	−6	View file
drivers/clk/mmp/clk-of-pxa910.c	modified	+4	−4	View file
drivers/clk/mmp/clk-pxa168.c	modified	+3	−5	View file
drivers/clk/mmp/clk-pxa910.c	modified	+3	−5	View file
drivers/clk/mvebu/Kconfig	modified	+6	−0	View file
drivers/clk/mvebu/Makefile	modified	+2	−0	View file
drivers/clk/mvebu/ap806-system-controller.c	added	+168	−0	View file
drivers/clk/mvebu/cp110-system-controller.c	added	+406	−0	View file
drivers/clk/nxp/clk-lpc18xx-creg.c	modified	+1	−0	View file
drivers/clk/qcom/gcc-msm8916.c	modified	+2	−0	View file
drivers/clk/qcom/mmcc-msm8996.c	modified	+0	−32	View file
drivers/clk/renesas/clk-mstp.c	modified	+1	−2	View file
drivers/clk/renesas/r8a7795-cpg-mssr.c	modified	+13	−0	View file
drivers/clk/renesas/renesas-cpg-mssr.c	modified	+1	−1	View file
drivers/clk/rockchip/Makefile	modified	+1	−0	View file
drivers/clk/rockchip/clk-cpu.c	modified	+18	−11	View file
drivers/clk/rockchip/clk-mmc-phase.c	modified	+2	−1	View file
drivers/clk/rockchip/clk-pll.c	modified	+291	−45	View file
drivers/clk/rockchip/clk-rk3036.c	modified	+16	−5	View file
drivers/clk/rockchip/clk-rk3188.c	modified	+38	−13	View file
drivers/clk/rockchip/clk-rk3228.c	modified	+16	−5	View file
drivers/clk/rockchip/clk-rk3288.c	modified	+17	−6	View file
drivers/clk/rockchip/clk-rk3368.c	modified	+21	−7	View file
drivers/clk/rockchip/clk-rk3399.c	added	+1573	−0	View file
drivers/clk/rockchip/clk.c	modified	+92	−59	View file
drivers/clk/rockchip/clk.h	modified	+85	−19	View file
drivers/clk/samsung/clk-exynos5420.c	modified	+47	−30	View file
drivers/clk/sirf/clk-atlas6.c	modified	+3	−4	View file
drivers/clk/sirf/clk-prima2.c	modified	+3	−4	View file
drivers/clk/sunxi/Makefile	modified	+3	−0	View file
drivers/clk/sunxi/clk-a10-hosc.c	modified	+1	−2	View file
drivers/clk/sunxi/clk-a10-mod1.c	modified	+1	−1	View file
drivers/clk/sunxi/clk-sun4i-display.c	added	+261	−0	View file
drivers/clk/sunxi/clk-sun4i-pll3.c	added	+98	−0	View file
drivers/clk/sunxi/clk-sun4i-tcon-ch1.c	added	+300	−0	View file
drivers/clk/sunxi/clk-sun9i-mmc.c	modified	+1	−1	View file
drivers/clk/sunxi/clk-sunxi.c	modified	+68	−11	View file
drivers/clk/tegra/Makefile	modified	+1	−0	View file
drivers/clk/tegra/clk-dfll.c	modified	+6	−5	View file
drivers/clk/tegra/clk-dfll.h	modified	+9	−13	View file
drivers/clk/tegra/clk-id.h	modified	+2	−0	View file
drivers/clk/tegra/clk-periph-fixed.c	added	+120	−0	View file
drivers/clk/tegra/clk-periph-gate.c	modified	+1	−1	View file
drivers/clk/tegra/clk-periph.c	modified	+1	−1	View file
drivers/clk/tegra/clk-pll.c	modified	+46	−0	View file
drivers/clk/tegra/clk-tegra-fixed.c	modified	+0	−1	View file
drivers/clk/tegra/clk-tegra-periph.c	modified	+2	−3	View file
drivers/clk/tegra/clk-tegra114.c	modified	+5	−1	View file
drivers/clk/tegra/clk-tegra124-dfll-fcpu.c	modified	+60	−43	View file
drivers/clk/tegra/clk-tegra124.c	modified	+4	−0	View file
drivers/clk/tegra/clk-tegra210.c	modified	+27	−2	View file
drivers/clk/tegra/clk-tegra30.c	modified	+7	−5	View file
drivers/clk/tegra/clk.c	modified	+2	−2	View file
drivers/clk/tegra/clk.h	modified	+25	−2	View file
drivers/clk/tegra/cvb.c	modified	+43	−28	View file
drivers/clk/tegra/cvb.h	modified	+8	−7	View file
drivers/clk/ti/clk-54xx.c	modified	+1	−0	View file
drivers/clk/ti/clk-7xx.c	modified	+1	−0	View file
drivers/clk/ti/clk-dra7-atl.c	modified	+2	−0	View file
drivers/clk/ti/clkt_dflt.c	modified	+1	−1	View file
drivers/clk/ti/clkt_dpll.c	modified	+3	−0	View file
drivers/clk/ti/dpll.c	modified	+5	−0	View file
drivers/clk/zte/clk-zx296702.c	modified	+1	−2	View file
include/dt-bindings/clock/axis,artpec6-clkctrl.h	added	+38	−0	View file
include/dt-bindings/clock/bcm2835.h	modified	+19	−1	View file
include/dt-bindings/clock/exynos5420.h	modified	+23	−1	View file
include/dt-bindings/clock/hi3519-clock.h	added	+40	−0	View file
include/dt-bindings/clock/imx7d-clock.h	modified	+2	−1	View file
include/dt-bindings/clock/tegra210-car.h	modified	+1	−1	View file
include/dt-bindings/clock/vf610-clock.h	modified	+6	−2	View file
include/linux/clk-provider.h	modified	+102	−1	View file
include/linux/clk/ti.h	modified	+2	−0	View file
include/linux/clkdev.h	modified	+6	−1	View file

Only the first 600 diff lines are shown. Download the complete patch.

Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt

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diff --git a/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt b/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt
new file mode 100644
index 0000000..8968371
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt
@@ -0,0 +1,35 @@
+Marvell Armada AP806 System Controller
+======================================
+
+The AP806 is one of the two core HW blocks of the Marvell Armada 7K/8K
+SoCs. It contains a system controller, which provides a number
+registers giving access to numerous features: clocks, pin-muxing and
+many other SoC configuration items. This DT binding allows to describe
+this system controller.
+
+The Device Tree node representing the AP806 system controller provides
+a number of clocks:
+
+ - 0: clock of CPU cluster 0
+ - 1: clock of CPU cluster 1
+ - 2: fixed PLL at 1200 Mhz
+ - 3: MSS clock, derived from the fixed PLL
+
+Required properties:
+
+ - compatible: must be:
+     "marvell,ap806-system-controller", "syscon"
+ - reg: register area of the AP806 system controller
+ - #clock-cells: must be set to 1
+ - clock-output-names: must be defined to:
+    "ap-cpu-cluster-0", "ap-cpu-cluster-1", "ap-fixed", "ap-mss"
+
+Example:
+
+	syscon: system-controller@6f4000 {
+		compatible = "marvell,ap806-system-controller", "syscon";
+		#clock-cells = <1>;
+		clock-output-names = "ap-cpu-cluster-0", "ap-cpu-cluster-1",
+				     "ap-fixed", "ap-mss";
+		reg = <0x6f4000 0x1000>;
+	};

Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt

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diff --git a/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt b/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt
new file mode 100644
index 0000000..30c5469
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt
@@ -0,0 +1,83 @@
+Marvell Armada CP110 System Controller 0
+========================================
+
+The CP110 is one of the two core HW blocks of the Marvell Armada 7K/8K
+SoCs. It contains two sets of system control registers, System
+Controller 0 and System Controller 1. This Device Tree binding allows
+to describe the first system controller, which provides registers to
+configure various aspects of the SoC.
+
+The Device Tree node representing this System Controller 0 provides a
+number of clocks:
+
+ - a set of core clocks
+ - a set of gatable clocks
+
+Those clocks can be referenced by other Device Tree nodes using two
+cells:
+ - The first cell must be 0 or 1. 0 for the core clocks and 1 for the
+   gatable clocks.
+ - The second cell identifies the particular core clock or gatable
+   clocks.
+
+The following clocks are available:
+ - Core clocks
+   - 0 0	APLL
+   - 0 1	PPv2 core
+   - 0 2	EIP
+   - 0 3	Core
+   - 0 4	NAND core
+ - Gatable clocks
+   - 1 0	Audio
+   - 1 1	Comm Unit
+   - 1 2	NAND
+   - 1 3	PPv2
+   - 1 4	SDIO
+   - 1 5	MG Domain
+   - 1 6	MG Core
+   - 1 7	XOR1
+   - 1 8	XOR0
+   - 1 9	GOP DP
+   - 1 11	PCIe x1 0
+   - 1 12	PCIe x1 1
+   - 1 13	PCIe x4
+   - 1 14	PCIe / XOR
+   - 1 15	SATA
+   - 1 16	SATA USB
+   - 1 17	Main
+   - 1 18	SD/MMC
+   - 1 21	Slow IO (SPI, NOR, BootROM, I2C, UART)
+   - 1 22	USB3H0
+   - 1 23	USB3H1
+   - 1 24	USB3 Device
+   - 1 25	EIP150
+   - 1 26	EIP197
+
+Required properties:
+
+ - compatible: must be:
+     "marvell,cp110-system-controller0", "syscon";
+ - reg: register area of the CP110 system controller 0
+ - #clock-cells: must be set to 2
+ - core-clock-output-names must be set to:
+	"cpm-apll", "cpm-ppv2-core", "cpm-eip", "cpm-core", "cpm-nand-core"
+ - gate-clock-output-names must be set to:
+	"cpm-audio", "cpm-communit", "cpm-nand", "cpm-ppv2", "cpm-sdio",
+	"cpm-mg-domain", "cpm-mg-core", "cpm-xor1", "cpm-xor0", "cpm-gop-dp", "none",
+	"cpm-pcie_x10", "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor", "cpm-sata",
+	"cpm-sata-usb", "cpm-main", "cpm-sd-mmc", "none", "none", "cpm-slow-io",
+	"cpm-usb3h0", "cpm-usb3h1", "cpm-usb3dev", "cpm-eip150", "cpm-eip197";
+
+Example:
+
+	cpm_syscon0: system-controller@440000 {
+		compatible = "marvell,cp110-system-controller0", "syscon";
+		reg = <0x440000 0x1000>;
+		#clock-cells = <2>;
+		core-clock-output-names = "cpm-apll", "cpm-ppv2-core", "cpm-eip", "cpm-core", "cpm-nand-core";
+		gate-clock-output-names = "cpm-audio", "cpm-communit", "cpm-nand", "cpm-ppv2", "cpm-sdio",
+			"cpm-mg-domain", "cpm-mg-core", "cpm-xor1", "cpm-xor0", "cpm-gop-dp", "none",
+			"cpm-pcie_x10", "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor", "cpm-sata",
+			"cpm-sata-usb", "cpm-main", "cpm-sd-mmc", "none", "none", "cpm-slow-io",
+			"cpm-usb3h0", "cpm-usb3h1", "cpm-usb3dev", "cpm-eip150", "cpm-eip197";
+	};

Documentation/devicetree/bindings/clock/artpec6.txt

View file

diff --git a/Documentation/devicetree/bindings/clock/artpec6.txt b/Documentation/devicetree/bindings/clock/artpec6.txt
new file mode 100644
index 0000000..dff9cdf
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/artpec6.txt
@@ -0,0 +1,41 @@
+* Clock bindings for Axis ARTPEC-6 chip
+
+The bindings are based on the clock provider binding in
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+External clocks:
+----------------
+
+There are two external inputs to the main clock controller which should be
+provided using the common clock bindings.
+- "sys_refclk": External 50 Mhz oscillator (required)
+- "i2s_refclk": Alternate audio reference clock (optional).
+
+Main clock controller
+---------------------
+
+Required properties:
+- #clock-cells: Should be <1>
+  See dt-bindings/clock/axis,artpec6-clkctrl.h for the list of valid identifiers.
+- compatible: Should be "axis,artpec6-clkctrl"
+- reg: Must contain the base address and length of the system controller
+- clocks:  Must contain a phandle entry for each clock in clock-names
+- clock-names: Must include the external oscillator ("sys_refclk"). Optional
+  ones are the audio reference clock ("i2s_refclk") and the audio fractional
+  dividers ("frac_clk0" and "frac_clk1").
+
+Examples:
+
+ext_clk: ext_clk {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <50000000>;
+};
+
+clkctrl: clkctrl@f8000000 {
+	#clock-cells = <1>;
+	compatible = "axis,artpec6-clkctrl";
+	reg = <0xf8000000 0x48>;
+	clocks = <&ext_clk>;
+	clock-names = "sys_refclk";
+};

Documentation/devicetree/bindings/clock/axs10x-i2s-pll-clock.txt

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diff --git a/Documentation/devicetree/bindings/clock/axs10x-i2s-pll-clock.txt b/Documentation/devicetree/bindings/clock/axs10x-i2s-pll-clock.txt
new file mode 100644
index 0000000..5ffc8df
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/axs10x-i2s-pll-clock.txt
@@ -0,0 +1,25 @@
+Binding for the AXS10X I2S PLL clock
+
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible: shall be "snps,axs10x-i2s-pll-clock"
+- reg : address and length of the I2S PLL register set.
+- clocks: shall be the input parent clock phandle for the PLL.
+- #clock-cells: from common clock binding; Should always be set to 0.
+
+Example:
+	pll_clock: pll_clock {
+		compatible = "fixed-clock";
+		clock-frequency = <27000000>;
+		#clock-cells = <0>;
+	};
+
+	i2s_clock@100a0 {
+		compatible = "snps,axs10x-i2s-pll-clock";
+		reg = <0x100a0 0x10>;
+		clocks = <&pll_clock>;
+		#clock-cells = <0>;
+	};

Documentation/devicetree/bindings/clock/hi3519-crg.txt

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diff --git a/Documentation/devicetree/bindings/clock/hi3519-crg.txt b/Documentation/devicetree/bindings/clock/hi3519-crg.txt
new file mode 100644
index 0000000..acd1f23
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/hi3519-crg.txt
@@ -0,0 +1,46 @@
+* Hisilicon Hi3519 Clock and Reset Generator(CRG)
+
+The Hi3519 CRG module provides clock and reset signals to various
+controllers within the SoC.
+
+This binding uses the following bindings:
+    Documentation/devicetree/bindings/clock/clock-bindings.txt
+    Documentation/devicetree/bindings/reset/reset.txt
+
+Required Properties:
+
+- compatible: should be one of the following.
+  - "hisilicon,hi3519-crg" - controller compatible with Hi3519 SoC.
+
+- reg: physical base address of the controller and length of memory mapped
+  region.
+
+- #clock-cells: should be 1.
+
+Each clock is assigned an identifier and client nodes use this identifier
+to specify the clock which they consume.
+
+All these identifier could be found in <dt-bindings/clock/hi3519-clock.h>.
+
+- #reset-cells: should be 2.
+
+A reset signal can be controlled by writing a bit register in the CRG module.
+The reset specifier consists of two cells. The first cell represents the
+register offset relative to the base address. The second cell represents the
+bit index in the register.
+
+Example: CRG nodes
+CRG: clock-reset-controller@12010000 {
+	compatible = "hisilicon,hi3519-crg";
+	reg = <0x12010000 0x10000>;
+	#clock-cells = <1>;
+	#reset-cells = <2>;
+};
+
+Example: consumer nodes
+i2c0: i2c@12110000 {
+	compatible = "hisilicon,hi3519-i2c";
+	reg = <0x12110000 0x1000>;
+	clocks = <&CRG HI3519_I2C0_RST>;
+	resets = <&CRG 0xe4 0>;
+};

Documentation/devicetree/bindings/clock/imx35-clock.txt

View file

diff --git a/Documentation/devicetree/bindings/clock/imx35-clock.txt b/Documentation/devicetree/bindings/clock/imx35-clock.txt
index a703564..f497832 100644
--- a/Documentation/devicetree/bindings/clock/imx35-clock.txt
+++ b/Documentation/devicetree/bindings/clock/imx35-clock.txt
@@ -94,6 +94,7 @@ clocks and IDs.
 	csi_sel			79
 	iim_gate		80
 	gpu2d_gate		81
+	ckli_gate		82
 
 Examples:
 

Documentation/devicetree/bindings/clock/oxnas,stdclk.txt

View file

diff --git a/Documentation/devicetree/bindings/clock/oxnas,stdclk.txt b/Documentation/devicetree/bindings/clock/oxnas,stdclk.txt
new file mode 100644
index 0000000..208cca6
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/oxnas,stdclk.txt
@@ -0,0 +1,35 @@
+Oxford Semiconductor OXNAS SoC Family Standard Clocks
+================================================
+
+Please also refer to clock-bindings.txt in this directory for common clock
+bindings usage.
+
+Required properties:
+- compatible: Should be "oxsemi,ox810se-stdclk"
+- #clock-cells: 1, see below
+
+Parent node should have the following properties :
+- compatible: Should be "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd"
+
+For OX810SE, the clock indices are :
+ - 0: LEON
+ - 1: DMA_SGDMA
+ - 2: CIPHER
+ - 3: SATA
+ - 4: AUDIO
+ - 5: USBMPH
+ - 6: ETHA
+ - 7: PCIA
+ - 8: NAND
+
+example:
+
+sys: sys-ctrl@000000 {
+	compatible = "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd";
+	reg = <0x000000 0x100000>;
+
+	stdclk: stdclk {
+		compatible = "oxsemi,ox810se-stdclk";
+		#clock-cells = <1>;
+	};
+};

Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt

View file

diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt
new file mode 100644
index 0000000..3888dd3
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt
@@ -0,0 +1,62 @@
+* Rockchip RK3399 Clock and Reset Unit
+
+The RK3399 clock controller generates and supplies clock to various
+controllers within the SoC and also implements a reset controller for SoC
+peripherals.
+
+Required Properties:
+
+- compatible: PMU for CRU should be "rockchip,rk3399-pmucru"
+- compatible: CRU should be "rockchip,rk3399-cru"
+- reg: physical base address of the controller and length of memory mapped
+  region.
+- #clock-cells: should be 1.
+- #reset-cells: should be 1.
+
+Each clock is assigned an identifier and client nodes can use this identifier
+to specify the clock which they consume. All available clocks are defined as
+preprocessor macros in the dt-bindings/clock/rk3399-cru.h headers and can be
+used in device tree sources. Similar macros exist for the reset sources in
+these files.
+
+External clocks:
+
+There are several clocks that are generated outside the SoC. It is expected
+that they are defined using standard clock bindings with following
+clock-output-names:
+ - "xin24m" - crystal input - required,
+ - "xin32k" - rtc clock - optional,
+ - "clkin_gmac" - external GMAC clock - optional,
+ - "clkin_i2s" - external I2S clock - optional,
+ - "pclkin_cif" - external ISP clock - optional,
+ - "clk_usbphy0_480m" - output clock of the pll in the usbphy0
+ - "clk_usbphy1_480m" - output clock of the pll in the usbphy1
+
+Example: Clock controller node:
+
+	pmucru: pmu-clock-controller@ff750000 {
+		compatible = "rockchip,rk3399-pmucru";
+		reg = <0x0 0xff750000 0x0 0x1000>;
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	cru: clock-controller@ff760000 {
+		compatible = "rockchip,rk3399-cru";
+		reg = <0x0 0xff760000 0x0 0x1000>;
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+Example: UART controller node that consumes the clock generated by the clock
+  controller:
+
+	uart0: serial@ff1a0000 {
+		compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
+		reg = <0x0 0xff180000 0x0 0x100>;
+		clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
+		clock-names = "baudclk", "apb_pclk";
+		interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+		reg-shift = <2>;
+		reg-io-width = <4>;
+	};

Documentation/devicetree/bindings/clock/sunxi.txt

View file

diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
index 834436f..8f7619d 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -10,6 +10,7 @@ Required properties:
 	"allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4
 	"allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
 	"allwinner,sun8i-a23-pll1-clk" - for the main PLL clock on A23
+	"allwinner,sun4i-a10-pll3-clk" - for the video PLL clock on A10
 	"allwinner,sun9i-a80-pll4-clk" - for the peripheral PLLs on A80
 	"allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock
 	"allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock
@@ -63,7 +64,9 @@ Required properties:
 	"allwinner,sun8i-a83t-bus-gates-clk" - for the bus gates on A83T
 	"allwinner,sun8i-h3-bus-gates-clk" - for the bus gates on H3
 	"allwinner,sun9i-a80-apbs-gates-clk" - for the APBS gates on A80
+	"allwinner,sun4i-a10-display-clk" - for the display clocks on the A10
 	"allwinner,sun4i-a10-dram-gates-clk" - for the DRAM gates on A10
+	"allwinner,sun5i-a13-dram-gates-clk" - for the DRAM gates on A13
 	"allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13
 	"allwinner,sun4i-a10-mmc-clk" - for the MMC clock
 	"allwinner,sun9i-a80-mmc-clk" - for mmc module clocks on A80
@@ -73,6 +76,8 @@ Required properties:
 	"allwinner,sun8i-a23-mbus-clk" - for the MBUS clock on A23
 	"allwinner,sun7i-a20-out-clk" - for the external output clocks
 	"allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31
+	"allwinner,sun4i-a10-tcon-ch0-clk" - for the TCON channel 0 clock on the A10
+	"allwinner,sun4i-a10-tcon-ch1-clk" - for the TCON channel 1 clock on the A10
 	"allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20
 	"allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13
 	"allwinner,sun6i-a31-usb-clk" - for usb gates + resets on A31
@@ -81,6 +86,7 @@ Required properties:
 	"allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80
 	"allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80
 	"allwinner,sun4i-a10-ve-clk" - for the Video Engine clock
+	"allwinner,sun6i-a31-display-clk" - for the display clocks
 
 Required properties for all clocks:
 - reg : shall be the control register address for the clock.

Documentation/driver-model/devres.txt

View file

diff --git a/Documentation/driver-model/devres.txt b/Documentation/driver-model/devres.txt
index 6c4478c..76a6c0a 100644
--- a/Documentation/driver-model/devres.txt
+++ b/Documentation/driver-model/devres.txt
@@ -236,6 +236,7 @@ certainly invest a bit more effort into libata core layer).
 CLOCK
   devm_clk_get()
   devm_clk_put()
+  devm_clk_hw_register()
 
 DMA
   dmam_alloc_coherent()

MAINTAINERS

View file

diff --git a/MAINTAINERS b/MAINTAINERS
index 2f66ca7..e840831 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -977,7 +977,7 @@ S:	Maintained
 L:	[email protected]
 F:	arch/arm/mach-artpec
 F:	arch/arm/boot/dts/artpec6*
-F:	drivers/clk/clk-artpec6.c
+F:	drivers/clk/axis
 
 ARM/ASPEED MACHINE SUPPORT
 M:	Joel Stanley <[email protected]>

drivers/clk/Kconfig

View file

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 90518cd..53ddba2 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -200,6 +200,12 @@ config COMMON_CLK_PXA
 config COMMON_CLK_PIC32
 	def_bool COMMON_CLK && MACH_PIC32
 
+config COMMON_CLK_OXNAS
+	bool "Clock driver for the OXNAS SoC Family"
+	select MFD_SYSCON
+	---help---
+	  Support for the OXNAS SoC Family clocks.
+
 source "drivers/clk/bcm/Kconfig"
 source "drivers/clk/hisilicon/Kconfig"
 source "drivers/clk/mvebu/Kconfig"

drivers/clk/Makefile

View file

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 18e64bb..dcc5e69 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -33,6 +33,7 @@ obj-$(CONFIG_ARCH_MB86S7X)		+= clk-mb86s7x.o
 obj-$(CONFIG_ARCH_MOXART)		+= clk-moxart.o
 obj-$(CONFIG_ARCH_NOMADIK)		+= clk-nomadik.o
 obj-$(CONFIG_ARCH_NSPIRE)		+= clk-nspire.o
+obj-$(CONFIG_COMMON_CLK_OXNAS)		+= clk-oxnas.o
 obj-$(CONFIG_COMMON_CLK_PALMAS)		+= clk-palmas.o
 obj-$(CONFIG_CLK_QORIQ)			+= clk-qoriq.o
 obj-$(CONFIG_COMMON_CLK_RK808)		+= clk-rk808.o
@@ -51,6 +52,7 @@ obj-$(CONFIG_COMMON_CLK_WM831X)		+= clk-wm831x.o
 obj-$(CONFIG_COMMON_CLK_XGENE)		+= clk-xgene.o
 obj-$(CONFIG_COMMON_CLK_PWM)		+= clk-pwm.o
 obj-$(CONFIG_COMMON_CLK_AT91)		+= at91/
+obj-$(CONFIG_ARCH_ARTPEC)		+= axis/
 obj-y					+= bcm/
 obj-$(CONFIG_ARCH_BERLIN)		+= berlin/
 obj-$(CONFIG_ARCH_HISI)			+= hisilicon/
@@ -62,7 +64,7 @@ obj-$(CONFIG_MACH_PIC32)		+= microchip/
 ifeq ($(CONFIG_COMMON_CLK), y)
 obj-$(CONFIG_ARCH_MMP)			+= mmp/
 endif
-obj-$(CONFIG_PLAT_ORION)		+= mvebu/
+obj-y					+= mvebu/
 obj-$(CONFIG_ARCH_MESON)		+= meson/
 obj-$(CONFIG_ARCH_MXS)			+= mxs/
 obj-$(CONFIG_MACH_PISTACHIO)		+= pistachio/
@@ -85,3 +87,4 @@ obj-$(CONFIG_X86)			+= x86/
 obj-$(CONFIG_ARCH_ZX)			+= zte/
 obj-$(CONFIG_ARCH_ZYNQ)			+= zynq/
 obj-$(CONFIG_H8300)		+= h8300/
+obj-$(CONFIG_ARC_PLAT_AXS10X)		+= axs10x/

drivers/clk/at91/clk-h32mx.c

View file

diff --git a/drivers/clk/at91/clk-h32mx.c b/drivers/clk/at91/clk-h32mx.c
index 819f584..8e20c8a 100644
--- a/drivers/clk/at91/clk-h32mx.c
+++ b/drivers/clk/at91/clk-h32mx.c
@@ -114,7 +114,7 @@ static void __init of_sama5d4_clk_h32mx_setup(struct device_node *np)
 	h32mxclk->regmap = regmap;
 
 	clk = clk_register(NULL, &h32mxclk->hw);
-	if (!clk) {
+	if (IS_ERR(clk)) {
 		kfree(h32mxclk);
 		return;
 	}

drivers/clk/axis/Makefile

View file

diff --git a/drivers/clk/axis/Makefile b/drivers/clk/axis/Makefile
new file mode 100644
index 0000000..628c9d3
--- /dev/null
+++ b/drivers/clk/axis/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_MACH_ARTPEC6)	+= clk-artpec6.o

drivers/clk/axis/clk-artpec6.c

View file

diff --git a/drivers/clk/axis/clk-artpec6.c b/drivers/clk/axis/clk-artpec6.c
new file mode 100644
index 0000000..ffc988b
--- /dev/null
+++ b/drivers/clk/axis/clk-artpec6.c
@@ -0,0 +1,242 @@
+/*
+ * ARTPEC-6 clock initialization
+ *
+ * Copyright 2015-2016 Axis Comunications AB.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <dt-bindings/clock/axis,artpec6-clkctrl.h>
+
+#define NUM_I2S_CLOCKS 2
+
+struct artpec6_clkctrl_drvdata {
+	struct clk *clk_table[ARTPEC6_CLK_NUMCLOCKS];
+	void __iomem *syscon_base;
+	struct clk_onecell_data clk_data;
+	spinlock_t i2scfg_lock;
+};
+
+static struct artpec6_clkctrl_drvdata *clkdata;
+
+static const char *const i2s_clk_names[NUM_I2S_CLOCKS] = {
+	"i2s0",
+	"i2s1",
+};
+
+static const int i2s_clk_indexes[NUM_I2S_CLOCKS] = {
+	ARTPEC6_CLK_I2S0_CLK,
+	ARTPEC6_CLK_I2S1_CLK,
+};
+
+static void of_artpec6_clkctrl_setup(struct device_node *np)
+{
+	int i;
+	const char *sys_refclk_name;
+	u32 pll_mode, pll_m, pll_n;
+	struct clk **clks;
+
+	/* Mandatory parent clock. */
+	i = of_property_match_string(np, "clock-names", "sys_refclk");
+	if (i < 0)
+		return;
+
+	sys_refclk_name = of_clk_get_parent_name(np, i);
+
+	clkdata = kzalloc(sizeof(*clkdata), GFP_KERNEL);
+	if (!clkdata)
+		return;
+
+	clks = clkdata->clk_table;
+
+	for (i = 0; i < ARTPEC6_CLK_NUMCLOCKS; ++i)
+		clks[i] = ERR_PTR(-EPROBE_DEFER);
+
+	clkdata->syscon_base = of_iomap(np, 0);
+	BUG_ON(clkdata->syscon_base == NULL);
+
+	/* Read PLL1 factors configured by boot strap pins. */
+	pll_mode = (readl(clkdata->syscon_base) >> 6) & 3;
+	switch (pll_mode) {
+	case 0:		/* DDR3-2133 mode */
+		pll_m = 4;
+		pll_n = 85;
+		break;
+	case 1:		/* DDR3-1866 mode */
+		pll_m = 6;
+		pll_n = 112;
+		break;
+	case 2:		/* DDR3-1600 mode */