diff --git a/arch/sparc/include/asm/cacheflush.h b/arch/sparc/include/asm/cacheflush.h
index 0491680..f6c4839 100644
--- a/arch/sparc/include/asm/cacheflush.h
+++ b/arch/sparc/include/asm/cacheflush.h
@@ -1,5 +1,9 @@
 #ifndef ___ASM_SPARC_CACHEFLUSH_H
 #define ___ASM_SPARC_CACHEFLUSH_H
+
+/* flush addr - to allow use of self-modifying code */
+#define flushi(addr)	__asm__ __volatile__ ("flush %0" : : "r" (addr) : "memory")
+
 #if defined(__sparc__) && defined(__arch64__)
 #include <asm/cacheflush_64.h>
 #else
diff --git a/arch/sparc/include/asm/cacheflush_64.h b/arch/sparc/include/asm/cacheflush_64.h
index 2efea2f..301736d 100644
--- a/arch/sparc/include/asm/cacheflush_64.h
+++ b/arch/sparc/include/asm/cacheflush_64.h
@@ -8,9 +8,6 @@
 #include <linux/mm.h>
 
 /* Cache flush operations. */
-
-
-#define flushi(addr)	__asm__ __volatile__ ("flush %0" : : "r" (addr) : "memory")
 #define flushw_all()	__asm__ __volatile__("flushw")
 
 extern void __flushw_user(void);
diff --git a/arch/sparc/kernel/setup_32.c b/arch/sparc/kernel/setup_32.c
index d65b5a1..c052313 100644
--- a/arch/sparc/kernel/setup_32.c
+++ b/arch/sparc/kernel/setup_32.c
@@ -227,16 +227,14 @@ static void __init per_cpu_patch(void)
 			prom_halt();
 		}
 		*(unsigned int *) (addr + 0) = insns[0];
+		flushi(addr + 0);
 		*(unsigned int *) (addr + 4) = insns[1];
+		flushi(addr + 4);
 		*(unsigned int *) (addr + 8) = insns[2];
+		flushi(addr + 8);
 
 		p++;
 	}
-#ifdef CONFIG_SMP
-	local_ops->cache_all();
-#else
-	sparc32_cachetlb_ops->cache_all();
-#endif
 }
 
 enum sparc_cpu sparc_cpu_model;
@@ -340,13 +338,11 @@ void __init setup_arch(char **cmdline_p)
 	init_mm.context = (unsigned long) NO_CONTEXT;
 	init_task.thread.kregs = &fake_swapper_regs;
 
-	paging_init();
-
-	/* Now that we have the cache ops hooked up, we can patch
-	 * instructions.
-	 */
+	/* Run-time patch instructions to match the cpu model */
 	per_cpu_patch();
 
+	paging_init();
+
 	smp_setup_cpu_possible_map();
 }