Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

1fbb2dc6 · Linus Torvalds <[email protected]> · 2018-12-25 14:57:37 -08:00

Pull clk updates from Stephen Boyd:
 "This round is dominated by NXP's i.MX clk drivers. We gained support
  for two or three i.MX SoCs in here and that mostly means a lot of
  driver code and data.

  Beyond that platform, there are some new Mediatek, Amlogic, and
  Qualcomm clk drivers added in here, and then we get to the long tail
  of driver updates and non-critical fixes all around, including code
  for vendors such as Renesas, Rockchip, Nvidia, and Allwinner. Overall,
  the driver updates look normal.

  Apart from the usual driver updates we have an update to make
  registering OF based clk providers a little simpler when they're
  devices created as a child of a device backed by a node in DT. Drivers
  don't have to jump through hoops to unregister the provider upon
  driver removal anymore because the API does the right thing and uses
  the parent device DT node.

  Summary:

  Core:
   - Make devm_of_clk_add_hw_provider() use parent dt node if necessary
   - Various SPDX taggings
   - Mark clk_ops const when possible

  New Drivers:
   - NXP i.MX7ULP SoC clock support
   - NXP i.MX8QXP SoC clock support
   - NXP i.MX8MQ SoC clock support
   - NXP QorIQ T1023 SoC support
   - Qualcomm SDM845 audio subsystem clks
   - Qualcomm SDM845 GPU clck controllers
   - Qualcomm QCS404 RPM clk support
   - Mediatek MT7629 SoC clk controllers
   - Allwinner F1c100s SoC clocks
   - Allwinner H6 display engine clocks
   - Amlogic GX video clocks
   - Support for Amlogic meson8b CPU frequency scaling
   - Amlogic Meson8b CPU post-divider clocks

  Updates:
   - Proper suspend/resume on VersaClock5
   - Shrink code some with DEFINE_SHOW_ATTRIBUTE()
   - Register fixes for Rockchip rk3188 and rk3328
   - One new critical clock for Rockchip rk3188 and a fixed clock id
     (double used number)
   - New clock id for Rockchip rk3328
   - Amlogic Meson8/Meson8b video clock support
   - Amlogic got a clk-input helper and used it for the axg-audio clock
     driver
   - Sigma Delta modulation for the Allwinner A33 audio clocks
   - Support for CPEX (timer) clocks on various Renesas R-Car Gen3 and
     RZ/G2 SoCs
   - Support for SDHI HS400 clocks on early revisions of Renesas R-Car
     H3 and M3-W
   - Support for SDHI and USB clocks on Renesas RZ/A2
   - Support for RPC (SPI Multi I/O Bus Controller) clocks on Renesas
     R-Car V3M
   - Qualcomm MSM8998 GCC driver improvements (resets, drop unused clks,
     etc)"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (172 commits)
  clk: imx: imx7ulp: add arm hsrun mode clocks support
  dt-bindings: clock: imx7ulp: add HSRUN mode related clocks
  clk: Use of_node_name_eq for node name comparisons
  clk: vc5: Add suspend/resume support
  clk: qcom: Drop unused 8998 clock
  clk: qcom: Leave mmss noc on for 8998
  clk: tegra: Return the exact clock rate from clk_round_rate
  clk: tegra30: Use Tegra CPU powergate helper function
  soc/tegra: pmc: Drop SMP dependency from CPU APIs
  clk: tegra: Fix maximum audio sync clock for Tegra124/210
  clk: tegra: get rid of duplicate defines
  clk: imx: add imx8qxp lpcg driver
  clk: imx: add lpcg clock support
  clk: imx: add imx8qxp clk driver
  clk: imx: Make the i.MX8MQ CCM clock driver CLK_IMX8MQ dependant
  clk: imx: add scu clock common part
  clk: imx: add configuration option for mmio clks
  dt-bindings: clock: add imx8qxp lpcg clock binding
  dt-bindings: clock: imx8qxp: add SCU clock IDs
  clk: qcom: Add missing msm8998 resets
  ...

Commit: 1fbb2dc6f0ce95e73b9bd7e8e899089f5cebc99a
Parents: 4e4390ad · b677574b

Merge commit. Changes below are compared with the first parent: 4e4390ad.

Changes

190 files changed · +11000 −1352

File	Status	Add	Del	Content
Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt	modified	+8	−29	View file
Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt	modified	+1	−0	View file
Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt	modified	+1	−0	View file
Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt	modified	+1	−0	View file
Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt	modified	+1	−0	View file
Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt	modified	+1	−0	View file
Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt	modified	+1	−0	View file
Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt	modified	+1	−0	View file
Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt	modified	+1	−0	View file
Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt	modified	+5	−8	View file
Documentation/devicetree/bindings/clock/imx6q-clock.txt	modified	+3	−0	View file
Documentation/devicetree/bindings/clock/imx7ulp-clock.txt	added	+104	−0	View file
Documentation/devicetree/bindings/clock/imx8mq-clock.txt	added	+20	−0	View file
Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt	added	+51	−0	View file
Documentation/devicetree/bindings/clock/qcom,gcc.txt	modified	+16	−0	View file
Documentation/devicetree/bindings/clock/qcom,gpucc.txt	added	+22	−0	View file
Documentation/devicetree/bindings/clock/qcom,lpasscc.txt	added	+26	−0	View file
Documentation/devicetree/bindings/clock/qcom,rpmcc.txt	modified	+1	−0	View file
Documentation/devicetree/bindings/clock/qcom,videocc.txt	modified	+1	−2	View file
Documentation/devicetree/bindings/clock/sun8i-de2.txt	modified	+3	−2	View file
Documentation/devicetree/bindings/clock/sunxi-ccu.txt	modified	+1	−0	View file
drivers/clk/Kconfig	modified	+9	−0	View file
drivers/clk/Makefile	modified	+2	−1	View file
drivers/clk/bcm/clk-bcm2835-aux.c	modified	+2	−11	View file
drivers/clk/bcm/clk-bcm2835.c	modified	+2	−12	View file
drivers/clk/clk-axm5516.c	modified	+0	−2	View file
drivers/clk/clk-bd718x7.c	added	+123	−0	View file
drivers/clk/clk-bulk.c	modified	+1	−12	View file
drivers/clk/clk-composite.c	modified	+1	−12	View file
drivers/clk/clk-conf.c	modified	+1	−4	View file
drivers/clk/clk-devres.c	modified	+1	−6	View file
drivers/clk/clk-divider.c	modified	+1	−4	View file
drivers/clk/clk-fixed-factor.c	modified	+1	−6	View file
drivers/clk/clk-fixed-rate.c	modified	+1	−4	View file
drivers/clk/clk-fractional-divider.c	modified	+11	−4	View file
drivers/clk/clk-gate.c	modified	+1	−4	View file
drivers/clk/clk-gpio.c	modified	+1	−4	View file
drivers/clk/clk-hi655x.c	modified	+2	−2	View file
drivers/clk/clk-max77686.c	modified	+1	−1	View file
drivers/clk/clk-multiplier.c	modified	+1	−4	View file
drivers/clk/clk-mux.c	modified	+1	−4	View file
drivers/clk/clk-nomadik.c	modified	+3	−13	View file
drivers/clk/clk-palmas.c	modified	+1	−1	View file
drivers/clk/clk-qoriq.c	modified	+11	−0	View file
drivers/clk/clk-rk808.c	modified	+2	−13	View file
drivers/clk/clk-s2mps11.c	modified	+1	−1	View file
drivers/clk/clk-stm32mp1.c	modified	+1	−1	View file
drivers/clk/clk-twl6040.c	modified	+2	−3	View file
drivers/clk/clk-versaclock5.c	modified	+25	−0	View file
drivers/clk/clk.c	modified	+41	−6	View file
drivers/clk/clk.h	modified	+1	−6	View file
drivers/clk/h8300/clk-h8s2678.c	modified	+1	−1	View file
drivers/clk/hisilicon/clk-hi3620.c	modified	+1	−1	View file
drivers/clk/hisilicon/clk-hisi-phase.c	modified	+1	−1	View file
drivers/clk/hisilicon/clk-hix5hd2.c	modified	+1	−1	View file
drivers/clk/hisilicon/clkgate-separated.c	modified	+1	−1	View file
drivers/clk/imgtec/clk-boston.c	modified	+17	−4	View file
drivers/clk/imx/Kconfig	added	+22	−0	View file
drivers/clk/imx/Makefile	modified	+17	−2	View file
drivers/clk/imx/clk-busy.c	modified	+1	−1	View file
drivers/clk/imx/clk-composite-7ulp.c	added	+87	−0	View file
drivers/clk/imx/clk-composite-8m.c	added	+178	−0	View file
drivers/clk/imx/clk-divider-gate.c	added	+221	−0	View file
drivers/clk/imx/clk-fixup-mux.c	modified	+1	−1	View file
drivers/clk/imx/clk-frac-pll.c	added	+232	−0	View file
drivers/clk/imx/clk-imx6q.c	modified	+81	−12	View file
drivers/clk/imx/clk-imx6sl.c	modified	+6	−0	View file
drivers/clk/imx/clk-imx7d.c	modified	+0	−3	View file
drivers/clk/imx/clk-imx7ulp.c	added	+249	−0	View file
drivers/clk/imx/clk-imx8mq.c	added	+589	−0	View file
drivers/clk/imx/clk-imx8qxp-lpcg.c	added	+216	−0	View file
drivers/clk/imx/clk-imx8qxp-lpcg.h	added	+102	−0	View file
drivers/clk/imx/clk-imx8qxp.c	added	+153	−0	View file
drivers/clk/imx/clk-lpcg-scu.c	added	+116	−0	View file
drivers/clk/imx/clk-pfdv2.c	added	+203	−0	View file
drivers/clk/imx/clk-pllv4.c	added	+184	−0	View file
drivers/clk/imx/clk-sccg-pll.c	added	+256	−0	View file
drivers/clk/imx/clk-scu.c	added	+270	−0	View file
drivers/clk/imx/clk-scu.h	added	+18	−0	View file
drivers/clk/imx/clk.c	modified	+22	−0	View file
drivers/clk/imx/clk.h	modified	+153	−7	View file
drivers/clk/loongson1/clk.c	modified	+5	−3	View file
drivers/clk/mediatek/Kconfig	modified	+23	−0	View file
drivers/clk/mediatek/Makefile	modified	+3	−0	View file
drivers/clk/mediatek/clk-cpumux.c	modified	+4	−4	View file
drivers/clk/mediatek/clk-mt7622.c	modified	+2	−2	View file
drivers/clk/mediatek/clk-mt7629-eth.c	added	+159	−0	View file
drivers/clk/mediatek/clk-mt7629-hif.c	added	+156	−0	View file
drivers/clk/mediatek/clk-mt7629.c	added	+723	−0	View file
drivers/clk/meson/Makefile	modified	+2	−1	View file
drivers/clk/meson/axg-audio.c	modified	+24	−59	View file
drivers/clk/meson/clk-input.c	added	+44	−0	View file
drivers/clk/meson/clk-pll.c	modified	+19	−0	View file
drivers/clk/meson/clk-regmap.c	modified	+5	−0	View file
drivers/clk/meson/clk-regmap.h	modified	+1	−0	View file
drivers/clk/meson/clkc.h	modified	+11	−0	View file
drivers/clk/meson/gxbb.c	modified	+777	−2	View file
drivers/clk/meson/gxbb.h	modified	+24	−2	View file
drivers/clk/meson/meson8b.c	modified	+1259	−204	View file
drivers/clk/meson/meson8b.h	modified	+65	−4	View file
drivers/clk/meson/vid-pll-div.c	added	+91	−0	View file
drivers/clk/pistachio/clk-pll.c	modified	+4	−4	View file
drivers/clk/pxa/clk-pxa.c	modified	+2	−2	View file
drivers/clk/qcom/Kconfig	modified	+26	−35	View file
drivers/clk/qcom/Makefile	modified	+2	−0	View file
drivers/clk/qcom/apcs-msm8916.c	modified	+2	−4	View file
drivers/clk/qcom/clk-smd-rpm.c	modified	+45	−0	View file
drivers/clk/qcom/gcc-msm8916.c	modified	+4	−0	View file
drivers/clk/qcom/gcc-msm8998.c	modified	+207	−64	View file
drivers/clk/qcom/gcc-sdm845.c	modified	+35	−0	View file
drivers/clk/qcom/gdsc.c	modified	+4	−2	View file
drivers/clk/qcom/gpucc-sdm845.c	added	+252	−0	View file
drivers/clk/qcom/lpasscc-sdm845.c	added	+179	−0	View file
drivers/clk/renesas/clk-div6.c	modified	+1	−1	View file
drivers/clk/renesas/clk-mstp.c	modified	+2	−2	View file
drivers/clk/renesas/r7s9210-cpg-mssr.c	modified	+8	−1	View file
drivers/clk/renesas/r8a774a1-cpg-mssr.c	modified	+1	−0	View file
drivers/clk/renesas/r8a7795-cpg-mssr.c	modified	+1	−0	View file
drivers/clk/renesas/r8a7796-cpg-mssr.c	modified	+1	−0	View file
drivers/clk/renesas/r8a77965-cpg-mssr.c	modified	+1	−0	View file
drivers/clk/renesas/r8a77970-cpg-mssr.c	modified	+5	−0	View file
drivers/clk/renesas/r8a77990-cpg-mssr.c	modified	+2	−2	View file
drivers/clk/renesas/r8a77995-cpg-mssr.c	modified	+6	−9	View file
drivers/clk/renesas/r9a06g032-clocks.c	modified	+4	−4	View file
drivers/clk/renesas/rcar-gen3-cpg.c	modified	+34	−23	View file
drivers/clk/renesas/renesas-cpg-mssr.c	modified	+1	−1	View file
drivers/clk/rockchip/clk-rk3188.c	modified	+7	−6	View file
drivers/clk/rockchip/clk-rk3328.c	modified	+2	−2	View file
drivers/clk/samsung/clk-s3c2410-dclk.c	modified	+1	−1	View file
drivers/clk/st/clk-flexgen.c	modified	+1	−1	View file
drivers/clk/st/clkgen-fsyn.c	modified	+2	−2	View file
drivers/clk/st/clkgen-pll.c	modified	+1	−1	View file
drivers/clk/sunxi-ng/Kconfig	modified	+6	−0	View file
drivers/clk/sunxi-ng/Makefile	modified	+1	−0	View file
drivers/clk/sunxi-ng/ccu-sun50i-a64.c	modified	+32	−16	View file
drivers/clk/sunxi-ng/ccu-sun50i-h6.c	modified	+7	−3	View file
drivers/clk/sunxi-ng/ccu-sun8i-a33.c	modified	+27	−16	View file
drivers/clk/sunxi-ng/ccu-sun8i-de2.c	modified	+68	−3	View file
drivers/clk/sunxi-ng/ccu-sun8i-de2.h	modified	+3	−1	View file
drivers/clk/sunxi-ng/ccu-sun8i-h3.c	modified	+2	−2	View file
drivers/clk/sunxi-ng/ccu-sun8i-r40.c	modified	+11	−0	View file
drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c	added	+541	−0	View file
drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h	added	+34	−0	View file
drivers/clk/sunxi-ng/ccu_mp.c	modified	+62	−2	View file
drivers/clk/sunxi-ng/ccu_nm.c	modified	+15	−3	View file
drivers/clk/tegra/clk-audio-sync.c	modified	+1	−2	View file
drivers/clk/tegra/clk-dfll.c	modified	+1	−11	View file
drivers/clk/tegra/clk-pll.c	modified	+4	−3	View file
drivers/clk/tegra/clk-tegra-audio.c	modified	+2	−5	View file
drivers/clk/tegra/clk-tegra-periph.c	modified	+0	−3	View file
drivers/clk/tegra/clk-tegra114.c	modified	+8	−1	View file
drivers/clk/tegra/clk-tegra124.c	modified	+8	−1	View file
drivers/clk/tegra/clk-tegra20.c	modified	+36	−10	View file
drivers/clk/tegra/clk-tegra210.c	modified	+8	−1	View file
drivers/clk/tegra/clk-tegra30.c	modified	+11	−4	View file
drivers/clk/tegra/clk.h	modified	+2	−2	View file
drivers/clk/ti/clkctrl.c	modified	+1	−1	View file
drivers/clk/ti/dpll.c	modified	+1	−1	View file
drivers/clk/ux500/u8500_of_clk.c	modified	+5	−5	View file
drivers/clk/versatile/clk-sp810.c	modified	+1	−1	View file
drivers/soc/tegra/pmc.c	modified	+0	−2	View file
include/dt-bindings/clock/bcm2835-aux.h	modified	+1	−9	View file
include/dt-bindings/clock/bcm2835.h	modified	+1	−9	View file
include/dt-bindings/clock/gxbb-clkc.h	modified	+18	−0	View file
include/dt-bindings/clock/imx6qdl-clock.h	modified	+3	−1	View file
include/dt-bindings/clock/imx7ulp-clock.h	added	+116	−0	View file
include/dt-bindings/clock/imx8mq-clock.h	added	+395	−0	View file
include/dt-bindings/clock/imx8qxp-clock.h	added	+289	−0	View file
include/dt-bindings/clock/meson8b-clkc.h	modified	+4	−0	View file
include/dt-bindings/clock/mt7629-clk.h	added	+203	−0	View file
include/dt-bindings/clock/qcom,gcc-msm8998.h	modified	+94	−0	View file
include/dt-bindings/clock/qcom,gcc-sdm845.h	modified	+2	−0	View file
include/dt-bindings/clock/qcom,gpucc-sdm845.h	added	+24	−0	View file
include/dt-bindings/clock/qcom,lpass-sdm845.h	added	+15	−0	View file
include/dt-bindings/clock/qcom,rpmcc.h	modified	+4	−0	View file
include/dt-bindings/clock/r8a7795-cpg-mssr.h	modified	+1	−1	View file
include/dt-bindings/clock/r8a7796-cpg-mssr.h	modified	+1	−1	View file
include/dt-bindings/clock/r8a77995-cpg-mssr.h	modified	+3	−2	View file
include/dt-bindings/clock/rk3328-cru.h	modified	+2	−1	View file
include/dt-bindings/clock/sun8i-de2.h	modified	+3	−0	View file
include/dt-bindings/clock/suniv-ccu-f1c100s.h	added	+70	−0	View file
include/dt-bindings/firmware/imx/rsrc.h	added	+559	−0	View file
include/dt-bindings/reset/sun8i-de2.h	modified	+1	−0	View file
include/dt-bindings/reset/suniv-ccu-f1c100s.h	added	+38	−0	View file
include/linux/clk-provider.h	modified	+9	−6	View file
include/linux/clk/clk-conf.h	modified	+1	−4	View file
include/linux/firmware/imx/sci.h	modified	+1	−0	View file
include/linux/firmware/imx/svc/pm.h	added	+85	−0	View file
include/linux/firmware/imx/types.h	modified	+0	−552	View file
include/soc/tegra/pmc.h	modified	+0	−2	View file

Only the first 600 diff lines are shown. Download the complete patch.

Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt

View file

diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
index 46d0af1..c20f38e 100644
--- a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
+++ b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
@@ -58,19 +58,11 @@ This binding for the SCU power domain providers uses the generic power
 domain binding[2].
 
 Required properties:
-- compatible:		Should be "fsl,scu-pd".
-- #address-cells:	Should be 1.
-- #size-cells:		Should be 0.
-
-Required properties for power domain sub nodes:
-- #power-domain-cells:	Must be 0.
-
-Optional Properties:
-- reg:			Resource ID of this power domain.
-			No exist means uncontrollable by user.
+- compatible:		Should be "fsl,imx8qxp-scu-pd".
+- #power-domain-cells:	Must be 1. Contains the Resource ID used by
+			SCU commands.
 			See detailed Resource ID list from:
-			include/dt-bindings/power/imx-rsrc.h
-- power-domains:	phandle pointing to the parent power domain.
+			include/dt-bindings/firmware/imx/rsrc.h
 
 Clock bindings based on SCU Message Protocol
 ------------------------------------------------------------
@@ -152,22 +144,9 @@ firmware {
 			...
 		};
 
-		imx8qx-pm {
-			compatible = "fsl,scu-pd";
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			pd_dma: dma-power-domain {
-				#power-domain-cells = <0>;
-
-				pd_dma_lpuart0: dma-lpuart0@57 {
-					reg = <SC_R_UART_0>;
-					#power-domain-cells = <0>;
-					power-domains = <&pd_dma>;
-				};
-				...
-			};
-			...
+		pd: imx8qx-pd {
+			compatible = "fsl,imx8qxp-scu-pd";
+			#power-domain-cells = <1>;
 		};
 	};
 };
@@ -179,5 +158,5 @@ serial@5a060000 {
 	clocks = <&clk IMX8QXP_UART0_CLK>,
 		 <&clk IMX8QXP_UART0_IPG_CLK>;
 	clock-names = "per", "ipg";
-	power-domains = <&pd_dma_lpuart0>;
+	power-domains = <&pd IMX_SC_R_UART_0>;
 };

Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt

View file

diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
index 4e4a3c0..de40754 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
@@ -11,6 +11,7 @@ Required Properties:
 	- "mediatek,mt6797-apmixedsys"
 	- "mediatek,mt7622-apmixedsys"
 	- "mediatek,mt7623-apmixedsys", "mediatek,mt2701-apmixedsys"
+	- "mediatek,mt7629-apmixedsys"
 	- "mediatek,mt8135-apmixedsys"
 	- "mediatek,mt8173-apmixedsys"
 - #clock-cells: Must be 1

Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt

View file

diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
index f17cfe6..6b7e806 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
@@ -9,6 +9,7 @@ Required Properties:
 	- "mediatek,mt2701-ethsys", "syscon"
 	- "mediatek,mt7622-ethsys", "syscon"
 	- "mediatek,mt7623-ethsys", "mediatek,mt2701-ethsys", "syscon"
+	- "mediatek,mt7629-ethsys", "syscon"
 - #clock-cells: Must be 1
 - #reset-cells: Must be 1
 

Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt

View file

diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
index 89f4272..417bd83 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
@@ -12,6 +12,7 @@ Required Properties:
 	- "mediatek,mt6797-infracfg", "syscon"
 	- "mediatek,mt7622-infracfg", "syscon"
 	- "mediatek,mt7623-infracfg", "mediatek,mt2701-infracfg", "syscon"
+	- "mediatek,mt7629-infracfg", "syscon"
 	- "mediatek,mt8135-infracfg", "syscon"
 	- "mediatek,mt8173-infracfg", "syscon"
 - #clock-cells: Must be 1

Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt

View file

diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt
index 7fe5dc6..d179a61 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt
@@ -7,6 +7,7 @@ Required Properties:
 
 - compatible: Should be:
 	- "mediatek,mt7622-pciesys", "syscon"
+	- "mediatek,mt7629-pciesys", "syscon"
 - #clock-cells: Must be 1
 - #reset-cells: Must be 1
 

Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt

View file

diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt
index 6755514..4c7e478 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt
@@ -11,6 +11,7 @@ Required Properties:
 	- "mediatek,mt2712-pericfg", "syscon"
 	- "mediatek,mt7622-pericfg", "syscon"
 	- "mediatek,mt7623-pericfg", "mediatek,mt2701-pericfg", "syscon"
+	- "mediatek,mt7629-pericfg", "syscon"
 	- "mediatek,mt8135-pericfg", "syscon"
 	- "mediatek,mt8173-pericfg", "syscon"
 - #clock-cells: Must be 1

Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt

View file

diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt
index d113b8e..30cb645 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt
@@ -7,6 +7,7 @@ Required Properties:
 
 - compatible: Should be:
 	- "mediatek,mt7622-sgmiisys", "syscon"
+	- "mediatek,mt7629-sgmiisys", "syscon"
 - #clock-cells: Must be 1
 
 The SGMIISYS controller uses the common clk binding from

Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt

View file

diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt
index b8184da..7cb02c9 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt
@@ -7,6 +7,7 @@ Required Properties:
 
 - compatible: Should be:
 	- "mediatek,mt7622-ssusbsys", "syscon"
+	- "mediatek,mt7629-ssusbsys", "syscon"
 - #clock-cells: Must be 1
 - #reset-cells: Must be 1
 

Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt

View file

diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
index d849465..d160c2b 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
@@ -11,6 +11,7 @@ Required Properties:
 	- "mediatek,mt6797-topckgen"
 	- "mediatek,mt7622-topckgen"
 	- "mediatek,mt7623-topckgen", "mediatek,mt2701-topckgen"
+	- "mediatek,mt7629-topckgen"
 	- "mediatek,mt8135-topckgen"
 	- "mediatek,mt8173-topckgen"
 - #clock-cells: Must be 1

Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt

View file

diff --git a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
index b455c5a..4d94091 100644
--- a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
+++ b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
@@ -9,15 +9,13 @@ Required Properties:
 	- "amlogic,meson8-clkc" for Meson8 (S802) SoCs
 	- "amlogic,meson8b-clkc" for Meson8 (S805) SoCs
 	- "amlogic,meson8m2-clkc" for Meson8m2 (S812) SoCs
-- reg: it must be composed by two tuples:
-	0) physical base address of the xtal register and length of memory
-	   mapped region.
-	1) physical base address of the clock controller and length of memory
-	   mapped region.
-
 - #clock-cells: should be 1.
 - #reset-cells: should be 1.
 
+Parent node should have the following properties :
+- compatible: "amlogic,meson-hhi-sysctrl", "simple-mfd", "syscon"
+- reg: base address and size of the HHI system control register space.
+
 Each clock is assigned an identifier and client nodes can use this identifier
 to specify the clock which they consume. All available clocks are defined as
 preprocessor macros in the dt-bindings/clock/meson8b-clkc.h header and can be
@@ -30,9 +28,8 @@ device tree sources).
 
 Example: Clock controller node:
 
-	clkc: clock-controller@c1104000 {
+	clkc: clock-controller {
 		compatible = "amlogic,meson8b-clkc";
-		reg = <0xc1108000 0x4>, <0xc1104000 0x460>;
 		#clock-cells = <1>;
 		#reset-cells = <1>;
 	};

Documentation/devicetree/bindings/clock/imx6q-clock.txt

View file

diff --git a/Documentation/devicetree/bindings/clock/imx6q-clock.txt b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
index e130834..13d36d4 100644
--- a/Documentation/devicetree/bindings/clock/imx6q-clock.txt
+++ b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
@@ -13,6 +13,9 @@ Optional properties:
   management IC (PMIC) triggered via PMIC_STBY_REQ signal.
   Boards that are designed to initiate poweroff on PMIC_ON_REQ signal should
   be using "syscon-poweroff" driver instead.
+- clocks: list of clock specifiers, must contain an entry for each entry
+          in clock-names
+- clock-names: valid names are "osc", "ckil", "ckih1", "anaclk1" and "anaclk2"
 
 The clock consumer should specify the desired clock by having the clock
 ID in its "clocks" phandle cell.  See include/dt-bindings/clock/imx6qdl-clock.h

Documentation/devicetree/bindings/clock/imx7ulp-clock.txt

View file

diff --git a/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt b/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt
new file mode 100644
index 0000000..a4f8cd4
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt
@@ -0,0 +1,104 @@
+* Clock bindings for Freescale i.MX7ULP
+
+i.MX7ULP Clock functions are under joint control of the System
+Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
+modules, and Core Mode Controller (CMC)1 blocks
+
+The clocking scheme provides clear separation between M4 domain
+and A7 domain. Except for a few clock sources shared between two
+domains, such as the System Oscillator clock, the Slow IRC (SIRC),
+and and the Fast IRC clock (FIRCLK), clock sources and clock
+management are separated and contained within each domain.
+
+M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules.
+A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
+
+Note: this binding doc is only for A7 clock domain.
+
+System Clock Generation (SCG) modules:
+---------------------------------------------------------------------
+The System Clock Generation (SCG) is responsible for clock generation
+and distribution across this device. Functions performed by the SCG
+include: clock reference selection, generation of clock used to derive
+processor, system, peripheral bus and external memory interface clocks,
+source selection for peripheral clocks and control of power saving
+clock gating mode.
+
+Required properties:
+
+- compatible:	Should be "fsl,imx7ulp-scg1".
+- reg : 	Should contain registers location and length.
+- #clock-cells:	Should be <1>.
+- clocks:	Should contain the fixed input clocks.
+- clock-names:  Should contain the following clock names:
+		"rosc", "sosc", "sirc", "firc", "upll", "mpll".
+
+Peripheral Clock Control (PCC) modules:
+---------------------------------------------------------------------
+The Peripheral Clock Control (PCC) is responsible for clock selection,
+optional division and clock gating mode for peripherals in their
+respected power domain
+
+Required properties:
+- compatible:	Should be one of:
+		  "fsl,imx7ulp-pcc2",
+		  "fsl,imx7ulp-pcc3".
+- reg : 	Should contain registers location and length.
+- #clock-cells:	Should be <1>.
+- clocks:	Should contain the fixed input clocks.
+- clock-names:  Should contain the following clock names:
+		"nic1_bus_clk", "nic1_clk", "ddr_clk", "apll_pfd2",
+		"apll_pfd1", "apll_pfd0", "upll", "sosc_bus_clk",
+		"mpll", "firc_bus_clk", "rosc", "spll_bus_clk";
+
+The clock consumer should specify the desired clock by having the clock
+ID in its "clocks" phandle cell.
+See include/dt-bindings/clock/imx7ulp-clock.h
+for the full list of i.MX7ULP clock IDs of each module.
+
+Examples:
+
+#include <dt-bindings/clock/imx7ulp-clock.h>
+
+scg1: scg1@403e0000 {
+	compatible = "fsl,imx7ulp-scg1;
+	reg = <0x403e0000 0x10000>;
+	clocks = <&rosc>, <&sosc>, <&sirc>,
+		 <&firc>, <&upll>, <&mpll>;
+	clock-names = "rosc", "sosc", "sirc",
+		      "firc", "upll", "mpll";
+	#clock-cells = <1>;
+};
+
+pcc2: pcc2@403f0000 {
+	compatible = "fsl,imx7ulp-pcc2";
+	reg = <0x403f0000 0x10000>;
+	#clock-cells = <1>;
+	clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
+		 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
+		 <&scg1 IMX7ULP_CLK_DDR_DIV>,
+		 <&scg1 IMX7ULP_CLK_APLL_PFD2>,
+		 <&scg1 IMX7ULP_CLK_APLL_PFD1>,
+		 <&scg1 IMX7ULP_CLK_APLL_PFD0>,
+		 <&scg1 IMX7ULP_CLK_UPLL>,
+		 <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
+		 <&scg1 IMX7ULP_CLK_MIPI_PLL>,
+		 <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
+		 <&scg1 IMX7ULP_CLK_ROSC>,
+		 <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
+	clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
+		      "apll_pfd2", "apll_pfd1", "apll_pfd0",
+		      "upll", "sosc_bus_clk", "mpll",
+		      "firc_bus_clk", "rosc", "spll_bus_clk";
+};
+
+usdhc1: usdhc@40380000 {
+	compatible = "fsl,imx7ulp-usdhc";
+	reg = <0x40380000 0x10000>;
+	interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+	clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
+		 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
+		 <&pcc2 IMX7ULP_CLK_USDHC1>;
+	clock-names ="ipg", "ahb", "per";
+	bus-width = <4>;
+};

Documentation/devicetree/bindings/clock/imx8mq-clock.txt

View file

diff --git a/Documentation/devicetree/bindings/clock/imx8mq-clock.txt b/Documentation/devicetree/bindings/clock/imx8mq-clock.txt
new file mode 100644
index 0000000..52de826
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx8mq-clock.txt
@@ -0,0 +1,20 @@
+* Clock bindings for NXP i.MX8M Quad
+
+Required properties:
+- compatible: Should be "fsl,imx8mq-ccm"
+- reg: Address and length of the register set
+- #clock-cells: Should be <1>
+- clocks: list of clock specifiers, must contain an entry for each required
+          entry in clock-names
+- clock-names: should include the following entries:
+    - "ckil"
+    - "osc_25m"
+    - "osc_27m"
+    - "clk_ext1"
+    - "clk_ext2"
+    - "clk_ext3"
+    - "clk_ext4"
+
+The clock consumer should specify the desired clock by having the clock
+ID in its "clocks" phandle cell.  See include/dt-bindings/clock/imx8mq-clock.h
+for the full list of i.MX8M Quad clock IDs.

Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt

View file

diff --git a/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt b/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt
new file mode 100644
index 0000000..965cfa4
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt
@@ -0,0 +1,51 @@
+* NXP i.MX8QXP LPCG (Low-Power Clock Gating) Clock bindings
+
+The Low-Power Clock Gate (LPCG) modules contain a local programming
+model to control the clock gates for the peripherals. An LPCG module
+is used to locally gate the clocks for the associated peripheral.
+
+Note:
+This level of clock gating is provided after the clocks are generated
+by the SCU resources and clock controls. Thus even if the clock is
+enabled by these control bits, it might still not be running based
+on the base resource.
+
+Required properties:
+- compatible:	Should be one of:
+		  "fsl,imx8qxp-lpcg-adma",
+		  "fsl,imx8qxp-lpcg-conn",
+		  "fsl,imx8qxp-lpcg-dc",
+		  "fsl,imx8qxp-lpcg-dsp",
+		  "fsl,imx8qxp-lpcg-gpu",
+		  "fsl,imx8qxp-lpcg-hsio",
+		  "fsl,imx8qxp-lpcg-img",
+		  "fsl,imx8qxp-lpcg-lsio",
+		  "fsl,imx8qxp-lpcg-vpu"
+- reg:		Address and length of the register set
+- #clock-cells:	Should be <1>
+
+The clock consumer should specify the desired clock by having the clock
+ID in its "clocks" phandle cell.
+See the full list of clock IDs from:
+include/dt-bindings/clock/imx8qxp-clock.h
+
+Examples:
+
+#include <dt-bindings/clock/imx8qxp-clock.h>
+
+conn_lpcg: clock-controller@5b200000 {
+	compatible = "fsl,imx8qxp-lpcg-conn";
+	reg = <0x5b200000 0xb0000>;
+	#clock-cells = <1>;
+};
+
+usdhc1: mmc@5b010000 {
+	compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
+	interrupt-parent = <&gic>;
+	interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
+	reg = <0x5b010000 0x10000>;
+	clocks = <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_IPG_CLK>,
+		 <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_PER_CLK>,
+		 <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_HCLK>;
+	clock-names = "ipg", "per", "ahb";
+};

Documentation/devicetree/bindings/clock/qcom,gcc.txt

View file

diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
index 52d9345..8661c3c 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
@@ -35,6 +35,8 @@ be part of GCC and hence the TSENS properties can also be
 part of the GCC/clock-controller node.
 For more details on the TSENS properties please refer
 Documentation/devicetree/bindings/thermal/qcom-tsens.txt
+- protected-clocks : Protected clock specifier list as per common clock
+ binding.
 
 Example:
 	clock-controller@900000 {
@@ -55,3 +57,17 @@ Example of GCC with TSENS properties:
 		#reset-cells = <1>;
 		#thermal-sensor-cells = <1>;
 	};
+
+Example of GCC with protected-clocks properties:
+	clock-controller@100000 {
+		compatible = "qcom,gcc-sdm845";
+		reg = <0x100000 0x1f0000>;
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+		#power-domain-cells = <1>;
+		protected-clocks = <GCC_QSPI_CORE_CLK>,
+				   <GCC_QSPI_CORE_CLK_SRC>,
+				   <GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
+				   <GCC_LPASS_Q6_AXI_CLK>,
+				   <GCC_LPASS_SWAY_CLK>;
+	};

Documentation/devicetree/bindings/clock/qcom,gpucc.txt

View file

diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.txt b/Documentation/devicetree/bindings/clock/qcom,gpucc.txt
new file mode 100644
index 0000000..4e5215e
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.txt
@@ -0,0 +1,22 @@
+Qualcomm Graphics Clock & Reset Controller Binding
+--------------------------------------------------
+
+Required properties :
+- compatible : shall contain "qcom,sdm845-gpucc"
+- reg : shall contain base register location and length
+- #clock-cells : from common clock binding, shall contain 1
+- #reset-cells : from common reset binding, shall contain 1
+- #power-domain-cells : from generic power domain binding, shall contain 1
+- clocks : shall contain the XO clock
+- clock-names : shall be "xo"
+
+Example:
+	gpucc: clock-controller@5090000 {
+		compatible = "qcom,sdm845-gpucc";
+		reg = <0x5090000 0x9000>;
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+		#power-domain-cells = <1>;
+		clocks = <&rpmhcc RPMH_CXO_CLK>;
+		clock-names = "xo";
+	};

Documentation/devicetree/bindings/clock/qcom,lpasscc.txt

View file

diff --git a/Documentation/devicetree/bindings/clock/qcom,lpasscc.txt b/Documentation/devicetree/bindings/clock/qcom,lpasscc.txt
new file mode 100644
index 0000000..b9e9787
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,lpasscc.txt
@@ -0,0 +1,26 @@
+Qualcomm LPASS Clock Controller Binding
+-----------------------------------------------
+
+Required properties :
+- compatible		: shall contain "qcom,sdm845-lpasscc"
+- #clock-cells		: from common clock binding, shall contain 1.
+- reg			: shall contain base register address and size,
+			  in the order
+			Index-0 maps to LPASS_CC register region
+			Index-1 maps to LPASS_QDSP6SS register region
+
+Optional properties :
+- reg-names	: register names of LPASS domain
+		 "cc", "qdsp6ss".
+
+Example:
+
+The below node has to be defined in the cases where the LPASS peripheral loader
+would bring the subsystem out of reset.
+
+	lpasscc: clock-controller@17014000 {
+		compatible = "qcom,sdm845-lpasscc";
+		reg = <0x17014000 0x1f004>, <0x17300000 0x200>;
+		reg-names = "cc", "qdsp6ss";
+		#clock-cells = <1>;
+	};

Documentation/devicetree/bindings/clock/qcom,rpmcc.txt

View file

diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
index 4491d1c..87b4949 100644
--- a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
@@ -16,6 +16,7 @@ Required properties :
 			"qcom,rpmcc-msm8974", "qcom,rpmcc"
 			"qcom,rpmcc-apq8064", "qcom,rpmcc"
 			"qcom,rpmcc-msm8996", "qcom,rpmcc"
+			"qcom,rpmcc-qcs404", "qcom,rpmcc"
 
 - #clock-cells : shall contain 1
 

Documentation/devicetree/bindings/clock/qcom,videocc.txt

View file

diff --git a/Documentation/devicetree/bindings/clock/qcom,videocc.txt b/Documentation/devicetree/bindings/clock/qcom,videocc.txt
index e7c035a..8a8622c 100644
--- a/Documentation/devicetree/bindings/clock/qcom,videocc.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,videocc.txt
@@ -6,8 +6,6 @@ Required properties :
 - reg : shall contain base register location and length
 - #clock-cells : from common clock binding, shall contain 1.
 - #power-domain-cells : from generic power domain binding, shall contain 1.
-
-Optional properties :
 - #reset-cells : from common reset binding, shall contain 1.
 
 Example:
@@ -16,4 +14,5 @@ Example:
 		reg = <0xab00000 0x10000>;
 		#clock-cells = <1>;
 		#power-domain-cells = <1>;
+		#reset-cells = <1>;
 	};

Documentation/devicetree/bindings/clock/sun8i-de2.txt

View file

diff --git a/Documentation/devicetree/bindings/clock/sun8i-de2.txt b/Documentation/devicetree/bindings/clock/sun8i-de2.txt
index e94582e..41a52c2 100644
--- a/Documentation/devicetree/bindings/clock/sun8i-de2.txt
+++ b/Documentation/devicetree/bindings/clock/sun8i-de2.txt
@@ -1,5 +1,5 @@
-Allwinner Display Engine 2.0 Clock Control Binding
---------------------------------------------------
+Allwinner Display Engine 2.0/3.0 Clock Control Binding
+------------------------------------------------------
 
 Required properties :
 - compatible: must contain one of the following compatibles:
@@ -8,6 +8,7 @@ Required properties :
 		- "allwinner,sun8i-v3s-de2-clk"
 		- "allwinner,sun50i-a64-de2-clk"
 		- "allwinner,sun50i-h5-de2-clk"
+		- "allwinner,sun50i-h6-de3-clk"
 
 - reg: Must contain the registers base address and length
 - clocks: phandle to the clocks feeding the display engine subsystem.

Documentation/devicetree/bindings/clock/sunxi-ccu.txt

View file

diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
index 47d2e90..e3bd88a 100644
--- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
@@ -22,6 +22,7 @@ Required properties :
 		- "allwinner,sun50i-h5-ccu"
 		- "allwinner,sun50i-h6-ccu"
 		- "allwinner,sun50i-h6-r-ccu"
+		- "allwinner,suniv-f1c100s-ccu"
 		- "nextthing,gr8-ccu"
 
 - reg: Must contain the registers base address and length

drivers/clk/Kconfig

View file

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 81cdb4e..e5b2fe8 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -283,10 +283,19 @@ config COMMON_CLK_STM32H7
 	---help---
 	  Support for stm32h7 SoC family clocks
 
+config COMMON_CLK_BD718XX
+	tristate "Clock driver for ROHM BD718x7 PMIC"
+	depends on MFD_ROHM_BD718XX
+	help
+	  This driver supports ROHM BD71837 and ROHM BD71847
+	  PMICs clock gates.
+
 source "drivers/clk/actions/Kconfig"
 source "drivers/clk/bcm/Kconfig"
 source "drivers/clk/hisilicon/Kconfig"
+source "drivers/clk/imx/Kconfig"
 source "drivers/clk/imgtec/Kconfig"
+source "drivers/clk/imx/Kconfig"
 source "drivers/clk/ingenic/Kconfig"
 source "drivers/clk/keystone/Kconfig"
 source "drivers/clk/mediatek/Kconfig"

drivers/clk/Makefile

View file

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 72be7a3..8a9440a 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -21,6 +21,7 @@ endif
 obj-$(CONFIG_MACH_ASM9260)		+= clk-asm9260.o
 obj-$(CONFIG_COMMON_CLK_AXI_CLKGEN)	+= clk-axi-clkgen.o
 obj-$(CONFIG_ARCH_AXXIA)		+= clk-axm5516.o
+obj-$(CONFIG_COMMON_CLK_BD718XX)	+= clk-bd718x7.o
 obj-$(CONFIG_COMMON_CLK_CDCE706)	+= clk-cdce706.o
 obj-$(CONFIG_COMMON_CLK_CDCE925)	+= clk-cdce925.o
 obj-$(CONFIG_ARCH_CLPS711X)		+= clk-clps711x.o
@@ -71,7 +72,7 @@ obj-$(CONFIG_ARCH_DAVINCI)		+= davinci/
 obj-$(CONFIG_H8300)			+= h8300/
 obj-$(CONFIG_ARCH_HISI)			+= hisilicon/
 obj-y					+= imgtec/
-obj-$(CONFIG_ARCH_MXC)			+= imx/
+obj-y					+= imx/
 obj-y					+= ingenic/
 obj-$(CONFIG_ARCH_K3)			+= keystone/
 obj-$(CONFIG_ARCH_KEYSTONE)		+= keystone/