clocksource: vf_pit_timer: use complement for sched_clock reading

224aa3ed · Stefan Agner <[email protected]> · 2014-03-05 23:11:08 +01:00

Vybrids PIT register is monitonic decreasing. However, sched_clock
reading needs to be monitonic increasing. Use bitwise not to get
the complement of the clock register. This fixes the clock going
backward. Also, the clock now starts at 0 since we load the
register with the maximum value at start.

Signed-off-by: Stefan Agner <[email protected]>
Acked-by: Shawn Guo <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Link: http://lkml.kernel.org/r/d25af915993aec1b486be653eb86f748ddef54fe.1394057313.git.stefan@agner.ch
Cc: [email protected]
Signed-off-by: Thomas Gleixner <[email protected]>

Commit: 224aa3ed45c8735ae02bb2ecca002409fa6aa772
Parents: 0414855f

Changes

1 files changed · +1 −1

File	Status	Add	Del	Content
drivers/clocksource/vf_pit_timer.c	modified	+1	−1	View file

drivers/clocksource/vf_pit_timer.c

View file

diff --git a/drivers/clocksource/vf_pit_timer.c b/drivers/clocksource/vf_pit_timer.c
index 02821b0..a918bc4 100644
--- a/drivers/clocksource/vf_pit_timer.c
+++ b/drivers/clocksource/vf_pit_timer.c
@@ -54,7 +54,7 @@ static inline void pit_irq_acknowledge(void)
 
 static u64 pit_read_sched_clock(void)
 {
-	return __raw_readl(clksrc_base + PITCVAL);
+	return ~__raw_readl(clksrc_base + PITCVAL);
 }
 
 static int __init pit_clocksource_init(unsigned long rate)