Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus

287dc4b7 · Linus Torvalds <[email protected]> · 2012-07-30 11:45:52 -07:00

Pull MIPS updates from Ralf Baechle:
 "More hardware support across the field including a bunch of device
  drivers.  The highlight however really are further steps towards
  device tree.

  This has been sitting in -next for ages.  All MIPS _defconfigs have
  been tested to boot or where I don't have hardware available, to at
  least build fine."

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (77 commits)
  MIPS: Loongson 1B: Add defconfig
  MIPS: Loongson 1B: Add board support
  MIPS: Netlogic: early console fix
  MIPS: Netlogic: Fix indentation of smpboot.S
  MIPS: Netlogic: remove cpu_has_dc_aliases define for XLP
  MIPS: Netlogic: Remove unused pcibios_fixups
  MIPS: Netlogic: Add XLP SoC devices in FDT
  MIPS: Netlogic: Add IRQ mappings for more devices
  MIPS: Netlogic: USB support for XLP
  MIPS: Netlogic: XLP PCIe controller support.
  MIPS: Netlogic: Platform changes for XLR/XLS I2C
  MIPS: Netlogic: Platform NAND/NOR flash support
  MIPS: Netlogic: Platform changes for XLS USB
  MIPS: Netlogic: Remove NETLOGIC_ prefix
  MIPS: Netlogic: SMP wakeup code update
  MIPS: Netlogic: Update comments in smpboot.S
  MIPS: BCM63XX: Add 96328avng reference board
  MIPS: Expose PCIe drivers for MIPS
  MIPS: BCM63XX: Add PCIe Support for BCM6328
  MIPS: BCM63XX: Move the PCI initialization into its own function
  ...

Commit: 287dc4b7642df15fa6b9f286c812e79138acd698
Parents: 720d8507 · 68d88485

Merge commit. Changes below are compared with the first parent: 720d8507.

Changes

165 files changed · +8102 −2217

File	Status	Add	Del	Content
Documentation/devicetree/bindings/ata/cavium-compact-flash.txt	added	+30	−0	View file
Documentation/devicetree/bindings/gpio/cavium-octeon-gpio.txt	added	+49	−0	View file
Documentation/devicetree/bindings/i2c/cavium-i2c.txt	added	+34	−0	View file
Documentation/devicetree/bindings/mips/cavium/bootbus.txt	added	+126	−0	View file
Documentation/devicetree/bindings/mips/cavium/ciu.txt	added	+26	−0	View file
Documentation/devicetree/bindings/mips/cavium/ciu2.txt	added	+27	−0	View file
Documentation/devicetree/bindings/mips/cavium/dma-engine.txt	added	+21	−0	View file
Documentation/devicetree/bindings/mips/cavium/uctl.txt	added	+46	−0	View file
Documentation/devicetree/bindings/net/cavium-mdio.txt	added	+27	−0	View file
Documentation/devicetree/bindings/net/cavium-mix.txt	added	+39	−0	View file
Documentation/devicetree/bindings/net/cavium-pip.txt	added	+98	−0	View file
Documentation/devicetree/bindings/serial/cavium-uart.txt	added	+19	−0	View file
arch/mips/Kbuild.platforms	modified	+1	−0	View file
arch/mips/Kconfig	modified	+37	−1	View file
arch/mips/alchemy/board-mtx1.c	modified	+2	−2	View file
arch/mips/alchemy/common/platform.c	modified	+4	−6	View file
arch/mips/alchemy/devboards/Makefile	modified	+1	−1	View file
arch/mips/alchemy/devboards/bcsr.c	modified	+1	−4	View file
arch/mips/alchemy/devboards/pb1100.c	modified	+2	−2	View file
arch/mips/alchemy/devboards/pb1500.c	modified	+2	−2	View file
arch/mips/alchemy/devboards/platform.c	modified	+30	−0	View file
arch/mips/alchemy/devboards/prom.c	deleted	+0	−69	View before deletion
arch/mips/bcm63xx/Kconfig	modified	+4	−0	View file
arch/mips/bcm63xx/Makefile	modified	+2	−1	View file
arch/mips/bcm63xx/boards/board_bcm963xx.c	modified	+58	−49	View file
arch/mips/bcm63xx/clk.c	modified	+21	−5	View file
arch/mips/bcm63xx/cpu.c	modified	+55	−8	View file
arch/mips/bcm63xx/dev-dsp.c	modified	+1	−1	View file
arch/mips/bcm63xx/dev-flash.c	added	+123	−0	View file
arch/mips/bcm63xx/dev-rng.c	added	+40	−0	View file
arch/mips/bcm63xx/dev-spi.c	added	+119	−0	View file
arch/mips/bcm63xx/dev-wdt.c	modified	+1	−1	View file
arch/mips/bcm63xx/irq.c	modified	+21	−0	View file
arch/mips/bcm63xx/prom.c	modified	+3	−1	View file
arch/mips/bcm63xx/setup.c	modified	+10	−3	View file
arch/mips/boot/compressed/Makefile	modified	+4	−0	View file
arch/mips/boot/compressed/uart-16550.c	modified	+5	−0	View file
arch/mips/cavium-octeon/.gitignore	added	+2	−0	View file
arch/mips/cavium-octeon/Makefile	modified	+16	−0	View file
arch/mips/cavium-octeon/executive/cvmx-fpa.c	deleted	+0	−183	View before deletion
arch/mips/cavium-octeon/executive/cvmx-helper-fpa.c	deleted	+0	−243	View before deletion
arch/mips/cavium-octeon/octeon-irq.c	modified	+314	−85	View file
arch/mips/cavium-octeon/octeon-memcpy.S	modified	+12	−4	View file
arch/mips/cavium-octeon/octeon-platform.c	modified	+522	−177	View file
arch/mips/cavium-octeon/octeon_3xxx.dts	added	+571	−0	View file
arch/mips/cavium-octeon/octeon_68xx.dts	added	+625	−0	View file
arch/mips/cavium-octeon/serial.c	modified	+53	−81	View file
arch/mips/cavium-octeon/setup.c	modified	+45	−0	View file
arch/mips/configs/ls1b_defconfig	added	+109	−0	View file
arch/mips/configs/nlm_xlr_defconfig	modified	+4	−0	View file
arch/mips/dec/prom/memory.c	modified	+1	−1	View file
arch/mips/include/asm/cpu.h	modified	+2	−1	View file
arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h	modified	+140	−10	View file
arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h	added	+12	−0	View file
arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h	added	+89	−0	View file
arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h	modified	+2	−0	View file
arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h	modified	+8	−0	View file
arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h	modified	+268	−18	View file
arch/mips/include/asm/mach-bcm63xx/ioremap.h	modified	+1	−0	View file
arch/mips/include/asm/mach-cavium-octeon/irq.h	modified	+5	−40	View file
arch/mips/include/asm/mach-jz4740/jz4740_nand.h	modified	+4	−0	View file
arch/mips/include/asm/mach-loongson/loongson.h	modified	+2	−1	View file
arch/mips/include/asm/mach-loongson1/irq.h	added	+73	−0	View file
arch/mips/include/asm/mach-loongson1/loongson1.h	added	+44	−0	View file
arch/mips/include/asm/mach-loongson1/platform.h	added	+23	−0	View file
arch/mips/include/asm/mach-loongson1/prom.h	added	+24	−0	View file
arch/mips/include/asm/mach-loongson1/regs-clk.h	added	+33	−0	View file
arch/mips/include/asm/mach-loongson1/regs-wdt.h	added	+22	−0	View file
arch/mips/include/asm/mach-loongson1/war.h	added	+25	−0	View file
arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h	modified	+0	−1	View file
arch/mips/include/asm/mach-tx49xx/mangle-port.h	modified	+1	−1	View file
arch/mips/include/asm/mipsmtregs.h	modified	+13	−0	View file
arch/mips/include/asm/module.h	modified	+2	−0	View file
arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h	modified	+3	−1	View file
arch/mips/include/asm/netlogic/xlp-hal/iomap.h	modified	+4	−1	View file
arch/mips/include/asm/netlogic/xlp-hal/pcibus.h	added	+76	−0	View file
arch/mips/include/asm/netlogic/xlp-hal/pic.h	modified	+4	−0	View file
arch/mips/include/asm/netlogic/xlp-hal/usb.h	added	+64	−0	View file
arch/mips/include/asm/netlogic/xlp-hal/xlp.h	modified	+15	−2	View file
arch/mips/include/asm/netlogic/xlr/bridge.h	added	+104	−0	View file
arch/mips/include/asm/netlogic/xlr/flash.h	added	+55	−0	View file
arch/mips/include/asm/netlogic/xlr/gpio.h	modified	+30	−29	View file
arch/mips/include/asm/octeon/cvmx-helper-fpa.h	deleted	+0	−64	View before deletion
arch/mips/include/asm/octeon/cvmx-helper.h	modified	+0	−2	View file
arch/mips/include/asm/octeon/octeon.h	modified	+0	−5	View file
arch/mips/include/asm/prom.h	modified	+0	−3	View file
arch/mips/include/asm/smtc.h	modified	+6	−0	View file
arch/mips/include/asm/uaccess.h	modified	+3	−3	View file
arch/mips/include/asm/uasm.h	modified	+51	−49	View file
arch/mips/jz4740/board-qi_lb60.c	modified	+1	−0	View file
arch/mips/jz4740/platform.c	modified	+19	−1	View file
arch/mips/jz4740/reset.c	modified	+44	−5	View file
arch/mips/kernel/cpu-probe.c	modified	+156	−143	View file
arch/mips/kernel/perf_event_mipsxx.c	modified	+5	−0	View file
arch/mips/kernel/prom.c	modified	+0	−29	View file
arch/mips/kernel/smp.c	modified	+3	−1	View file
arch/mips/kernel/smtc.c	modified	+68	−8	View file
arch/mips/kernel/traps.c	modified	+1	−0	View file
arch/mips/lib/Makefile	modified	+1	−1	View file
arch/mips/lib/memcpy-inatomic.S	deleted	+0	−451	View before deletion
arch/mips/lib/memcpy.S	modified	+11	−0	View file
arch/mips/loongson1/Kconfig	added	+21	−0	View file
arch/mips/loongson1/Makefile	added	+11	−0	View file
arch/mips/loongson1/Platform	added	+7	−0	View file
arch/mips/loongson1/common/Makefile	added	+5	−0	View file
arch/mips/loongson1/common/clock.c	added	+165	−0	View file
arch/mips/loongson1/common/irq.c	added	+147	−0	View file
arch/mips/loongson1/common/platform.c	added	+124	−0	View file
arch/mips/loongson1/common/prom.c	added	+87	−0	View file
arch/mips/loongson1/common/reset.c	added	+45	−0	View file
arch/mips/loongson1/common/setup.c	added	+29	−0	View file
arch/mips/loongson1/ls1b/Makefile	added	+5	−0	View file
arch/mips/loongson1/ls1b/board.c	added	+33	−0	View file
arch/mips/mm/uasm.c	modified	+30	−32	View file
arch/mips/netlogic/common/earlycons.c	modified	+1	−1	View file
arch/mips/netlogic/common/smpboot.S	modified	+102	−55	View file
arch/mips/netlogic/xlp/Makefile	modified	+2	−0	View file
arch/mips/netlogic/xlp/nlm_hal.c	modified	+52	−0	View file
arch/mips/netlogic/xlp/of.c	added	+34	−0	View file
arch/mips/netlogic/xlp/platform.c	modified	+1	−1	View file
arch/mips/netlogic/xlp/setup.c	modified	+16	−0	View file
arch/mips/netlogic/xlp/usb-init.c	added	+124	−0	View file
arch/mips/netlogic/xlr/Makefile	modified	+1	−1	View file
arch/mips/netlogic/xlr/platform-flash.c	added	+220	−0	View file
arch/mips/netlogic/xlr/platform.c	modified	+140	−0	View file
arch/mips/netlogic/xlr/setup.c	modified	+1	−1	View file
arch/mips/oprofile/common.c	modified	+1	−0	View file
arch/mips/oprofile/op_model_mipsxx.c	modified	+4	−6	View file
arch/mips/pci/Makefile	modified	+1	−0	View file
arch/mips/pci/fixup-cobalt.c	modified	+4	−4	View file
arch/mips/pci/fixup-malta.c	modified	+14	−0	View file
arch/mips/pci/fixup-rc32434.c	modified	+1	−1	View file
arch/mips/pci/ops-bcm63xx.c	modified	+62	−1	View file
arch/mips/pci/pci-bcm63xx.c	modified	+127	−6	View file
arch/mips/pci/pci-bcm63xx.h	modified	+5	−0	View file
arch/mips/pci/pci-xlp.c	added	+248	−0	View file
arch/mips/pci/pci-xlr.c	modified	+0	−4	View file
arch/mips/pnx833x/stb22x/board.c	modified	+2	−2	View file
arch/mips/txx9/generic/pci.c	modified	+3	−3	View file
arch/mips/txx9/generic/setup.c	modified	+5	−7	View file
arch/mips/txx9/generic/setup_tx4939.c	modified	+1	−1	View file
arch/mips/txx9/rbtx4939/setup.c	modified	+5	−6	View file
drivers/char/hw_random/Kconfig	modified	+14	−0	View file
drivers/char/hw_random/Makefile	modified	+1	−0	View file
drivers/char/hw_random/bcm63xx-rng.c	added	+175	−0	View file
drivers/i2c/busses/i2c-octeon.c	modified	+49	−43	View file
drivers/mtd/nand/jz4740_nand.c	modified	+192	−36	View file
drivers/net/ethernet/octeon/octeon_mgmt.c	modified	+207	−105	View file
drivers/net/phy/mdio-octeon.c	modified	+58	−34	View file
drivers/spi/Kconfig	modified	+9	−0	View file
drivers/spi/Makefile	modified	+1	−0	View file
drivers/spi/spi-falcon.c	added	+469	−0	View file
drivers/staging/octeon/ethernet-mdio.c	modified	+15	−13	View file
drivers/staging/octeon/ethernet.c	modified	+99	−54	View file
drivers/staging/octeon/octeon-ethernet.h	modified	+3	−0	View file
include/linux/libfdt.h	added	+8	−0	View file
include/linux/libfdt_env.h	added	+13	−0	View file
lib/Kconfig	modified	+6	−0	View file
lib/Makefile	modified	+5	−0	View file
lib/fdt.c	added	+2	−0	View file
lib/fdt_ro.c	added	+2	−0	View file
lib/fdt_rw.c	added	+2	−0	View file
lib/fdt_strerror.c	added	+2	−0	View file
lib/fdt_sw.c	added	+2	−0	View file
lib/fdt_wip.c	added	+2	−0	View file

Only the first 600 diff lines are shown. Download the complete patch.

Documentation/devicetree/bindings/ata/cavium-compact-flash.txt

View file

diff --git a/Documentation/devicetree/bindings/ata/cavium-compact-flash.txt b/Documentation/devicetree/bindings/ata/cavium-compact-flash.txt
new file mode 100644
index 0000000..93986a5
--- /dev/null
+++ b/Documentation/devicetree/bindings/ata/cavium-compact-flash.txt
@@ -0,0 +1,30 @@
+* Compact Flash
+
+The Cavium Compact Flash device is connected to the Octeon Boot Bus,
+and is thus a child of the Boot Bus device.  It can read and write
+industry standard compact flash devices.
+
+Properties:
+- compatible: "cavium,ebt3000-compact-flash";
+
+  Compatibility with many Cavium evaluation boards.
+
+- reg: The base address of the the CF chip select banks.  Depending on
+  the device configuration, there may be one or two banks.
+
+- cavium,bus-width: The width of the connection to the CF devices.  Valid
+  values are 8 and 16.
+
+- cavium,true-ide: Optional, if present the CF connection is in True IDE mode.
+
+- cavium,dma-engine-handle: Optional, a phandle for the DMA Engine connected
+  to this device.
+
+Example:
+	compact-flash@5,0 {
+		compatible = "cavium,ebt3000-compact-flash";
+		reg = <5 0 0x10000>, <6 0 0x10000>;
+		cavium,bus-width = <16>;
+		cavium,true-ide;
+		cavium,dma-engine-handle = <&dma0>;
+	};

Documentation/devicetree/bindings/gpio/cavium-octeon-gpio.txt

View file

diff --git a/Documentation/devicetree/bindings/gpio/cavium-octeon-gpio.txt b/Documentation/devicetree/bindings/gpio/cavium-octeon-gpio.txt
new file mode 100644
index 0000000..9d6dcd3
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/cavium-octeon-gpio.txt
@@ -0,0 +1,49 @@
+* General Purpose Input Output (GPIO) bus.
+
+Properties:
+- compatible: "cavium,octeon-3860-gpio"
+
+  Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs.
+
+- reg: The base address of the GPIO unit's register bank.
+
+- gpio-controller: This is a GPIO controller.
+
+- #gpio-cells: Must be <2>.  The first cell is the GPIO pin.
+
+- interrupt-controller: The GPIO controller is also an interrupt
+  controller, many of its pins may be configured as an interrupt
+  source.
+
+- #interrupt-cells: Must be <2>.  The first cell is the GPIO pin
+   connected to the interrupt source.  The second cell is the interrupt
+   triggering protocol and may have one of four values:
+   1 - edge triggered on the rising edge.
+   2 - edge triggered on the falling edge
+   4 - level triggered active high.
+   8 - level triggered active low.
+
+- interrupts: Interrupt routing for each pin.
+
+Example:
+
+	gpio-controller@1070000000800 {
+		#gpio-cells = <2>;
+		compatible = "cavium,octeon-3860-gpio";
+		reg = <0x10700 0x00000800 0x0 0x100>;
+		gpio-controller;
+		/* Interrupts are specified by two parts:
+		 * 1) GPIO pin number (0..15)
+		 * 2) Triggering (1 - edge rising
+		 *		  2 - edge falling
+		 *		  4 - level active high
+		 *		  8 - level active low)
+		 */
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		/* The GPIO pin connect to 16 consecutive CUI bits */
+		interrupts = <0 16>, <0 17>, <0 18>, <0 19>,
+			     <0 20>, <0 21>, <0 22>, <0 23>,
+			     <0 24>, <0 25>, <0 26>, <0 27>,
+			     <0 28>, <0 29>, <0 30>, <0 31>;
+	};

Documentation/devicetree/bindings/i2c/cavium-i2c.txt

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diff --git a/Documentation/devicetree/bindings/i2c/cavium-i2c.txt b/Documentation/devicetree/bindings/i2c/cavium-i2c.txt
new file mode 100644
index 0000000..dced82e
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/cavium-i2c.txt
@@ -0,0 +1,34 @@
+* Two Wire Serial Interface (TWSI) / I2C
+
+- compatible: "cavium,octeon-3860-twsi"
+
+  Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs.
+
+- reg: The base address of the TWSI/I2C bus controller register bank.
+
+- #address-cells: Must be <1>.
+
+- #size-cells: Must be <0>.  I2C addresses have no size component.
+
+- interrupts: A single interrupt specifier.
+
+- clock-frequency: The I2C bus clock rate in Hz.
+
+Example:
+	twsi0: i2c@1180000001000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "cavium,octeon-3860-twsi";
+		reg = <0x11800 0x00001000 0x0 0x200>;
+		interrupts = <0 45>;
+		clock-frequency = <100000>;
+
+		rtc@68 {
+			compatible = "dallas,ds1337";
+			reg = <0x68>;
+		};
+		tmp@4c {
+			compatible = "ti,tmp421";
+			reg = <0x4c>;
+		};
+	};

Documentation/devicetree/bindings/mips/cavium/bootbus.txt

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diff --git a/Documentation/devicetree/bindings/mips/cavium/bootbus.txt b/Documentation/devicetree/bindings/mips/cavium/bootbus.txt
new file mode 100644
index 0000000..6581478
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/cavium/bootbus.txt
@@ -0,0 +1,126 @@
+* Boot Bus
+
+The Octeon Boot Bus is a configurable parallel bus with 8 chip
+selects.  Each chip select is independently configurable.
+
+Properties:
+- compatible: "cavium,octeon-3860-bootbus"
+
+  Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs.
+
+- reg: The base address of the Boot Bus' register bank.
+
+- #address-cells: Must be <2>.  The first cell is the chip select
+   within the bootbus.  The second cell is the offset from the chip select.
+
+- #size-cells: Must be <1>.
+
+- ranges: There must be one one triplet of (child-bus-address,
+  parent-bus-address, length) for each active chip select.  If the
+  length element for any triplet is zero, the chip select is disabled,
+  making it inactive.
+
+The configuration parameters for each chip select are stored in child
+nodes.
+
+Configuration Properties:
+- compatible:  "cavium,octeon-3860-bootbus-config"
+
+- cavium,cs-index: A single cell indicating the chip select that
+  corresponds to this configuration.
+
+- cavium,t-adr: A cell specifying the ADR timing (in nS).
+
+- cavium,t-ce: A cell specifying the CE timing (in nS).
+
+- cavium,t-oe: A cell specifying the OE timing (in nS).
+
+- cavium,t-we: A cell specifying the WE timing (in nS).
+
+- cavium,t-rd-hld: A cell specifying the RD_HLD timing (in nS).
+
+- cavium,t-wr-hld: A cell specifying the WR_HLD timing (in nS).
+
+- cavium,t-pause: A cell specifying the PAUSE timing (in nS).
+
+- cavium,t-wait: A cell specifying the WAIT timing (in nS).
+
+- cavium,t-page: A cell specifying the PAGE timing (in nS).
+
+- cavium,t-rd-dly: A cell specifying the RD_DLY timing (in nS).
+
+- cavium,pages: A cell specifying the PAGES parameter (0 = 8 bytes, 1
+  = 2 bytes, 2 = 4 bytes, 3 = 8 bytes).
+
+- cavium,wait-mode: Optional.  If present, wait mode (WAITM) is selected.
+
+- cavium,page-mode: Optional.  If present, page mode (PAGEM) is selected.
+
+- cavium,bus-width: A cell specifying the WIDTH parameter (in bits) of
+  the bus for this chip select.
+
+- cavium,ale-mode: Optional.  If present, ALE mode is selected.
+
+- cavium,sam-mode: Optional.  If present, SAM mode is selected.
+
+- cavium,or-mode: Optional.  If present, OR mode is selected.
+
+Example:
+	bootbus: bootbus@1180000000000 {
+		compatible = "cavium,octeon-3860-bootbus";
+		reg = <0x11800 0x00000000 0x0 0x200>;
+		/* The chip select number and offset */
+		#address-cells = <2>;
+		/* The size of the chip select region */
+		#size-cells = <1>;
+		ranges = <0 0  0x0 0x1f400000  0xc00000>,
+			 <1 0  0x10000 0x30000000  0>,
+			 <2 0  0x10000 0x40000000  0>,
+			 <3 0  0x10000 0x50000000  0>,
+			 <4 0  0x0 0x1d020000  0x10000>,
+			 <5 0  0x0 0x1d040000  0x10000>,
+			 <6 0  0x0 0x1d050000  0x10000>,
+			 <7 0  0x10000 0x90000000  0>;
+
+			cavium,cs-config@0 {
+			compatible = "cavium,octeon-3860-bootbus-config";
+			cavium,cs-index = <0>;
+			cavium,t-adr  = <20>;
+			cavium,t-ce   = <60>;
+			cavium,t-oe   = <60>;
+			cavium,t-we   = <45>;
+			cavium,t-rd-hld = <35>;
+			cavium,t-wr-hld = <45>;
+			cavium,t-pause  = <0>;
+			cavium,t-wait   = <0>;
+			cavium,t-page   = <35>;
+			cavium,t-rd-dly = <0>;
+
+			cavium,pages     = <0>;
+			cavium,bus-width = <8>;
+		};
+		.
+		.
+		.
+		cavium,cs-config@6 {
+			compatible = "cavium,octeon-3860-bootbus-config";
+			cavium,cs-index = <6>;
+			cavium,t-adr  = <5>;
+			cavium,t-ce   = <300>;
+			cavium,t-oe   = <270>;
+			cavium,t-we   = <150>;
+			cavium,t-rd-hld = <100>;
+			cavium,t-wr-hld = <70>;
+			cavium,t-pause  = <0>;
+			cavium,t-wait   = <0>;
+			cavium,t-page   = <320>;
+			cavium,t-rd-dly = <0>;
+
+			cavium,pages     = <0>;
+			cavium,wait-mode;
+			cavium,bus-width = <16>;
+		};
+		.
+		.
+		.
+	};

Documentation/devicetree/bindings/mips/cavium/ciu.txt

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diff --git a/Documentation/devicetree/bindings/mips/cavium/ciu.txt b/Documentation/devicetree/bindings/mips/cavium/ciu.txt
new file mode 100644
index 0000000..2c2d074
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/cavium/ciu.txt
@@ -0,0 +1,26 @@
+* Central Interrupt Unit
+
+Properties:
+- compatible: "cavium,octeon-3860-ciu"
+
+  Compatibility with all cn3XXX, cn5XXX and cn63XX SOCs.
+
+- interrupt-controller:  This is an interrupt controller.
+
+- reg: The base address of the CIU's register bank.
+
+- #interrupt-cells: Must be <2>.  The first cell is the bank within
+   the CIU and may have a value of 0 or 1.  The second cell is the bit
+   within the bank and may have a value between 0 and 63.
+
+Example:
+	interrupt-controller@1070000000000 {
+		compatible = "cavium,octeon-3860-ciu";
+		interrupt-controller;
+		/* Interrupts are specified by two parts:
+		 * 1) Controller register (0 or 1)
+		 * 2) Bit within the register (0..63)
+		 */
+		#interrupt-cells = <2>;
+		reg = <0x10700 0x00000000 0x0 0x7000>;
+	};

Documentation/devicetree/bindings/mips/cavium/ciu2.txt

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diff --git a/Documentation/devicetree/bindings/mips/cavium/ciu2.txt b/Documentation/devicetree/bindings/mips/cavium/ciu2.txt
new file mode 100644
index 0000000..0ec7ba8
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/cavium/ciu2.txt
@@ -0,0 +1,27 @@
+* Central Interrupt Unit
+
+Properties:
+- compatible: "cavium,octeon-6880-ciu2"
+
+  Compatibility with 68XX SOCs.
+
+- interrupt-controller:  This is an interrupt controller.
+
+- reg: The base address of the CIU's register bank.
+
+- #interrupt-cells: Must be <2>.  The first cell is the bank within
+  the CIU and may have a value between 0 and 63.  The second cell is
+  the bit within the bank and may also have a value between 0 and 63.
+
+Example:
+	interrupt-controller@1070100000000 {
+		compatible = "cavium,octeon-6880-ciu2";
+		interrupt-controller;
+		/* Interrupts are specified by two parts:
+		 * 1) Controller register (0..63)
+		 * 2) Bit within the register (0..63)
+		 */
+		#address-cells = <0>;
+		#interrupt-cells = <2>;
+		reg = <0x10701 0x00000000 0x0 0x4000000>;
+	};

Documentation/devicetree/bindings/mips/cavium/dma-engine.txt

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diff --git a/Documentation/devicetree/bindings/mips/cavium/dma-engine.txt b/Documentation/devicetree/bindings/mips/cavium/dma-engine.txt
new file mode 100644
index 0000000..cb4291e
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/cavium/dma-engine.txt
@@ -0,0 +1,21 @@
+* DMA Engine.
+
+The Octeon DMA Engine transfers between the Boot Bus and main memory.
+The DMA Engine will be refered to by phandle by any device that is
+connected to it.
+
+Properties:
+- compatible: "cavium,octeon-5750-bootbus-dma"
+
+  Compatibility with all cn52XX, cn56XX and cn6XXX SOCs.
+
+- reg: The base address of the DMA Engine's register bank.
+
+- interrupts: A single interrupt specifier.
+
+Example:
+	dma0: dma-engine@1180000000100 {
+		compatible = "cavium,octeon-5750-bootbus-dma";
+		reg = <0x11800 0x00000100 0x0 0x8>;
+		interrupts = <0 63>;
+	};

Documentation/devicetree/bindings/mips/cavium/uctl.txt

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diff --git a/Documentation/devicetree/bindings/mips/cavium/uctl.txt b/Documentation/devicetree/bindings/mips/cavium/uctl.txt
new file mode 100644
index 0000000..aa66b9b
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/cavium/uctl.txt
@@ -0,0 +1,46 @@
+* UCTL USB controller glue
+
+Properties:
+- compatible: "cavium,octeon-6335-uctl"
+
+  Compatibility with all cn6XXX SOCs.
+
+- reg: The base address of the UCTL register bank.
+
+- #address-cells: Must be <2>.
+
+- #size-cells: Must be <2>.
+
+- ranges: Empty to signify direct mapping of the children.
+
+- refclk-frequency: A single cell containing the reference clock
+  frequency in Hz.
+
+- refclk-type: A string describing the reference clock connection
+  either "crystal" or "external".
+
+Example:
+	uctl@118006f000000 {
+		compatible = "cavium,octeon-6335-uctl";
+		reg = <0x11800 0x6f000000 0x0 0x100>;
+		ranges; /* Direct mapping */
+		#address-cells = <2>;
+		#size-cells = <2>;
+		/* 12MHz, 24MHz and 48MHz allowed */
+		refclk-frequency = <24000000>;
+		/* Either "crystal" or "external" */
+		refclk-type = "crystal";
+
+		ehci@16f0000000000 {
+			compatible = "cavium,octeon-6335-ehci","usb-ehci";
+			reg = <0x16f00 0x00000000 0x0 0x100>;
+			interrupts = <0 56>;
+			big-endian-regs;
+		};
+		ohci@16f0000000400 {
+			compatible = "cavium,octeon-6335-ohci","usb-ohci";
+			reg = <0x16f00 0x00000400 0x0 0x100>;
+			interrupts = <0 56>;
+			big-endian-regs;
+		};
+	};

Documentation/devicetree/bindings/net/cavium-mdio.txt

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diff --git a/Documentation/devicetree/bindings/net/cavium-mdio.txt b/Documentation/devicetree/bindings/net/cavium-mdio.txt
new file mode 100644
index 0000000..04cb749
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/cavium-mdio.txt
@@ -0,0 +1,27 @@
+* System Management Interface (SMI) / MDIO
+
+Properties:
+- compatible: "cavium,octeon-3860-mdio"
+
+  Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs.
+
+- reg: The base address of the MDIO bus controller register bank.
+
+- #address-cells: Must be <1>.
+
+- #size-cells: Must be <0>.  MDIO addresses have no size component.
+
+Typically an MDIO bus might have several children.
+
+Example:
+	mdio@1180000001800 {
+		compatible = "cavium,octeon-3860-mdio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x11800 0x00001800 0x0 0x40>;
+
+		ethernet-phy@0 {
+			...
+			reg = <0>;
+		};
+	};

Documentation/devicetree/bindings/net/cavium-mix.txt

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diff --git a/Documentation/devicetree/bindings/net/cavium-mix.txt b/Documentation/devicetree/bindings/net/cavium-mix.txt
new file mode 100644
index 0000000..5da628d
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/cavium-mix.txt
@@ -0,0 +1,39 @@
+* MIX Ethernet controller.
+
+Properties:
+- compatible: "cavium,octeon-5750-mix"
+
+  Compatibility with all cn5XXX and cn6XXX SOCs populated with MIX
+  devices.
+
+- reg: The base addresses of four separate register banks.  The first
+  bank contains the MIX registers.  The second bank the corresponding
+  AGL registers.  The third bank are the AGL registers shared by all
+  MIX devices present.  The fourth bank is the AGL_PRT_CTL shared by
+  all MIX devices present.
+
+- cell-index: A single cell specifying which portion of the shared
+  register banks corresponds to this MIX device.
+
+- interrupts: Two interrupt specifiers.  The first is the MIX
+  interrupt routing and the second the routing for the AGL interrupts.
+
+- mac-address: Optional, the MAC address to assign to the device.
+
+- local-mac-address: Optional, the MAC address to assign to the device
+  if mac-address is not specified.
+
+- phy-handle: Optional, a phandle for the PHY device connected to this device.
+
+Example:
+	ethernet@1070000100800 {
+		compatible = "cavium,octeon-5750-mix";
+		reg = <0x10700 0x00100800 0x0 0x100>, /* MIX */
+		      <0x11800 0xE0000800 0x0 0x300>, /* AGL */
+		      <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED  */
+		      <0x11800 0xE0002008 0x0 0x8>;   /* AGL_PRT_CTL */
+		cell-index = <1>;
+		interrupts = <1 18>, < 1 46>;
+		local-mac-address = [ 00 0f b7 10 63 54 ];
+		phy-handle = <&phy1>;
+	};

Documentation/devicetree/bindings/net/cavium-pip.txt

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diff --git a/Documentation/devicetree/bindings/net/cavium-pip.txt b/Documentation/devicetree/bindings/net/cavium-pip.txt
new file mode 100644
index 0000000..d4c53ba
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/cavium-pip.txt
@@ -0,0 +1,98 @@
+* PIP Ethernet nexus.
+
+The PIP Ethernet nexus can control several data packet input/output
+devices.  The devices have a two level grouping scheme.  There may be
+several interfaces, and each interface may have several ports.  These
+ports might be an individual Ethernet PHY.
+
+
+Properties for the PIP nexus:
+- compatible: "cavium,octeon-3860-pip"
+
+  Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs.
+
+- reg: The base address of the PIP's register bank.
+
+- #address-cells: Must be <1>.
+
+- #size-cells: Must be <0>.
+
+Properties for PIP interfaces which is a child the PIP nexus:
+- compatible: "cavium,octeon-3860-pip-interface"
+
+  Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs.
+
+- reg: The interface number.
+
+- #address-cells: Must be <1>.
+
+- #size-cells: Must be <0>.
+
+Properties for PIP port which is a child the PIP interface:
+- compatible: "cavium,octeon-3860-pip-port"
+
+  Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs.
+
+- reg: The port number within the interface group.
+
+- mac-address: Optional, the MAC address to assign to the device.
+
+- local-mac-address: Optional, the MAC address to assign to the device
+  if mac-address is not specified.
+
+- phy-handle: Optional, a phandle for the PHY device connected to this device.
+
+Example:
+
+	pip@11800a0000000 {
+		compatible = "cavium,octeon-3860-pip";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x11800 0xa0000000 0x0 0x2000>;
+
+		interface@0 {
+			compatible = "cavium,octeon-3860-pip-interface";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0>; /* interface */
+
+			ethernet@0 {
+				compatible = "cavium,octeon-3860-pip-port";
+				reg = <0x0>; /* Port */
+				local-mac-address = [ 00 0f b7 10 63 60 ];
+				phy-handle = <&phy2>;
+			};
+			ethernet@1 {
+				compatible = "cavium,octeon-3860-pip-port";
+				reg = <0x1>; /* Port */
+				local-mac-address = [ 00 0f b7 10 63 61 ];
+				phy-handle = <&phy3>;
+			};
+			ethernet@2 {
+				compatible = "cavium,octeon-3860-pip-port";
+				reg = <0x2>; /* Port */
+				local-mac-address = [ 00 0f b7 10 63 62 ];
+				phy-handle = <&phy4>;
+			};
+			ethernet@3 {
+				compatible = "cavium,octeon-3860-pip-port";
+				reg = <0x3>; /* Port */
+				local-mac-address = [ 00 0f b7 10 63 63 ];
+				phy-handle = <&phy5>;
+			};
+		};
+
+		interface@1 {
+			compatible = "cavium,octeon-3860-pip-interface";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>; /* interface */
+
+			ethernet@0 {
+				compatible = "cavium,octeon-3860-pip-port";
+				reg = <0x0>; /* Port */
+				local-mac-address = [ 00 0f b7 10 63 64 ];
+				phy-handle = <&phy6>;
+			};
+		};
+	};

Documentation/devicetree/bindings/serial/cavium-uart.txt

View file

diff --git a/Documentation/devicetree/bindings/serial/cavium-uart.txt b/Documentation/devicetree/bindings/serial/cavium-uart.txt
new file mode 100644
index 0000000..87a6c37
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/cavium-uart.txt
@@ -0,0 +1,19 @@
+* Universal Asynchronous Receiver/Transmitter (UART)
+
+- compatible: "cavium,octeon-3860-uart"
+
+  Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs.

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