Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

455e73a0 · Linus Torvalds <[email protected]> · 2022-01-12 17:02:27 -08:00

Pull clk updates from Stephen Boyd:
 "We have a couple patches in the framework core this time around but
  they're mostly minor cleanups and some debugfs stuff. The real work
  that's in here is the typical pile of clk driver updates and new SoC
  support.

  Per usual (or maybe just recent trends), Qualcomm gains a handful of
  SoC drivers additions and has the largest diffstat. After that there
  are quite a few updates to the Allwinner (sunxi) drivers to support
  modular drivers and Renesas is heavily updated to add more support for
  various clks.

  Overall it looks pretty normal.

  New Drivers:
   - Add MDMA and BDMA clks to Ingenic JZ4760 and JZ4770
   - MediaTek mt7986 SoC basic support
   - Clock and reset driver for Toshiba Visconti SoCs
   - Initial clock driver for the Exynos7885 SoC (Samsung Galaxy A8)
   - Allwinner D1 clks
   - Lan966x Generic Clock Controller driver and associated DT bindings
   - Qualcomm SDX65, SM8450, and MSM8976 GCC clks
   - Qualcomm SDX65 and SM8450 RPMh clks

  Updates:
   - Set suppress_bind_attrs to true for i.MX8ULP driver
   - Switch from do_div to div64_ul for throughout all i.MX drivers
   - Fix imx8mn_clko1_sels for i.MX8MN
   - Remove unused IPG_AUDIO_ROOT from i.MX8MP
   - Switch parent for audio_root_clk to audio ahb in i.MX8MP driver
   - Removal of all remaining uses of __clk_lookup() in
     drivers/clk/samsung
   - Refactoring of the CPU clocks registration to use common interface
   - An update of the Exynos850 driver (support for more clock domains)
     required by the E850-96 development board
   - Prep for runtime PM and generic power domains on Tegra
   - Support modular Allwinner clk drivers via platform bus
   - Lan966x clock driver extended to support clock gating
   - Add serial (SCI1), watchdog (WDT), timer (OSTM), SPI (RSPI), and
     thermal (TSU) clocks and resets on Renesas RZ/G2L
   - Rework SDHI clock handling in the Renesas R-Car Gen3 and RZ/G2
     clock drivers, and in the Renesas SDHI driver
   - Make the Cortex-A55 (I) clock on Renesas RZ/G2L programmable
   - Document support for the new Renesas R-Car S4-8 (R8A779F0) SoC
   - Add support for the new Renesas R-Car S4-8 (R8A779F0) SoC
   - Add GPU clock and resets on Renesas RZ/G2L
   - Add clk-provider.h to various Qualcomm clk drivers
   - devm version of clk_hw_register_gate()
   - kerneldoc fixes in a couple drivers"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (131 commits)
  clk: visconti: Remove pointless NULL check in visconti_pll_add_lookup()
  clk: mediatek: add mt7986 clock support
  clk: mediatek: add mt7986 clock IDs
  dt-bindings: clock: mediatek: document clk bindings for mediatek mt7986 SoC
  clk: mediatek: clk-gate: Use regmap_{set/clear}_bits helpers
  clk: mediatek: clk-gate: Shrink by adding clockgating bit check helper
  clk: x86: Fix clk_gate_flags for RV_CLK_GATE
  clk: x86: Use dynamic con_id string during clk registration
  ACPI: APD: Add a fmw property clk-name
  drivers: acpi: acpi_apd: Remove unused device property "is-rv"
  x86: clk: clk-fch: Add support for newer family of AMD's SOC
  clk: ingenic: Add MDMA and BDMA clocks
  dt-bindings: clk/ingenic: Add MDMA and BDMA clocks
  clk: bm1880: remove kfrees on static allocations
  clk: Drop unused COMMON_CLK_STM32MP157_SCMI config
  clk: st: clkgen-mux: search reg within node or parent
  clk: st: clkgen-fsyn: search reg within node or parent
  clk: Enable/Disable runtime PM for clk_summary
  MAINTAINERS: Add entries for Toshiba Visconti PLL and clock controller
  clk: visconti: Add support common clock driver and reset driver
  ...

Commit: 455e73a07f6e288b0061dfcf4fcf54fa9fe06458
Parents: d9b5941b · 4afd2a93

Merge commit. Changes below are compared with the first parent: d9b5941b.

Changes

198 files changed · +18551 −1240

File	Status	Add	Del	Content
Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt	modified	+1	−0	View file
Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt	modified	+1	−0	View file
Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt	modified	+1	−0	View file
Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt	modified	+2	−0	View file
Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt	modified	+1	−0	View file
Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml	modified	+4	−0	View file
Documentation/devicetree/bindings/clock/microchip,lan966x-gck.yaml	added	+60	−0	View file
Documentation/devicetree/bindings/clock/qcom,gcc-msm8976.yaml	added	+97	−0	View file
Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml	modified	+2	−0	View file
Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml	modified	+1	−0	View file
Documentation/devicetree/bindings/clock/samsung,exynos7885-clock.yaml	added	+166	−0	View file
Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml	modified	+38	−0	View file
Documentation/devicetree/bindings/clock/toshiba,tmpv770x-pipllct.yaml	added	+57	−0	View file
Documentation/devicetree/bindings/clock/toshiba,tmpv770x-pismu.yaml	added	+52	−0	View file
MAINTAINERS	modified	+12	−0	View file
drivers/acpi/acpi_apd.c	modified	+9	−2	View file
drivers/clk/Kconfig	modified	+16	−10	View file
drivers/clk/Makefile	modified	+4	−1	View file
drivers/clk/clk-bm1880.c	modified	+2	−18	View file
drivers/clk/clk-gate.c	modified	+35	−0	View file
drivers/clk/clk-gemini.c	modified	+1	−1	View file
drivers/clk/clk-lan966x.c	added	+293	−0	View file
drivers/clk/clk-stm32f4.c	modified	+0	−4	View file
drivers/clk/clk-stm32mp1.c	modified	+0	−2	View file
drivers/clk/clk-tps68470.c	added	+261	−0	View file
drivers/clk/clk.c	modified	+69	−11	View file
drivers/clk/imx/clk-imx8mn.c	modified	+3	−3	View file
drivers/clk/imx/clk-imx8mp.c	modified	+1	−1	View file
drivers/clk/imx/clk-imx8ulp.c	modified	+1	−0	View file
drivers/clk/imx/clk-pllv1.c	modified	+8	−9	View file
drivers/clk/imx/clk-pllv3.c	modified	+3	−3	View file
drivers/clk/ingenic/jz4760-cgu.c	modified	+10	−0	View file
drivers/clk/ingenic/jz4770-cgu.c	modified	+5	−0	View file
drivers/clk/mediatek/Kconfig	modified	+17	−0	View file
drivers/clk/mediatek/Makefile	modified	+4	−0	View file
drivers/clk/mediatek/clk-gate.c	modified	+9	−15	View file
drivers/clk/mediatek/clk-mt7986-apmixed.c	added	+100	−0	View file
drivers/clk/mediatek/clk-mt7986-eth.c	added	+132	−0	View file
drivers/clk/mediatek/clk-mt7986-infracfg.c	added	+224	−0	View file
drivers/clk/mediatek/clk-mt7986-topckgen.c	added	+342	−0	View file
drivers/clk/meson/gxbb.c	modified	+41	−3	View file
drivers/clk/qcom/Kconfig	modified	+24	−0	View file
drivers/clk/qcom/Makefile	modified	+3	−0	View file
drivers/clk/qcom/clk-alpha-pll.c	modified	+160	−6	View file
drivers/clk/qcom/clk-alpha-pll.h	modified	+3	−0	View file
drivers/clk/qcom/clk-rpmh.c	modified	+52	−0	View file
drivers/clk/qcom/clk-smd-rpm.c	modified	+4	−27	View file
drivers/clk/qcom/gcc-msm8976.c	added	+4155	−0	View file
drivers/clk/qcom/gcc-msm8994.c	modified	+1	−0	View file
drivers/clk/qcom/gcc-sc7280.c	modified	+1	−1	View file
drivers/clk/qcom/gcc-sdx65.c	added	+1611	−0	View file
drivers/clk/qcom/gcc-sm6350.c	modified	+1	−0	View file
drivers/clk/qcom/gcc-sm8350.c	modified	+1	−0	View file
drivers/clk/qcom/gcc-sm8450.c	added	+3304	−0	View file
drivers/clk/qcom/lpasscc-sc7280.c	modified	+1	−0	View file
drivers/clk/qcom/lpasscc-sdm845.c	modified	+1	−0	View file
drivers/clk/qcom/mmcc-apq8084.c	modified	+1	−0	View file
drivers/clk/qcom/q6sstop-qcs404.c	modified	+1	−0	View file
drivers/clk/qcom/turingcc-qcs404.c	modified	+1	−0	View file
drivers/clk/renesas/Kconfig	modified	+11	−2	View file
drivers/clk/renesas/Makefile	modified	+2	−0	View file
drivers/clk/renesas/r8a774a1-cpg-mssr.c	modified	+8	−4	View file
drivers/clk/renesas/r8a774b1-cpg-mssr.c	modified	+8	−4	View file
drivers/clk/renesas/r8a774c0-cpg-mssr.c	modified	+6	−3	View file
drivers/clk/renesas/r8a774e1-cpg-mssr.c	modified	+8	−4	View file
drivers/clk/renesas/r8a7795-cpg-mssr.c	modified	+8	−4	View file
drivers/clk/renesas/r8a7796-cpg-mssr.c	modified	+8	−4	View file
drivers/clk/renesas/r8a77965-cpg-mssr.c	modified	+8	−4	View file
drivers/clk/renesas/r8a77980-cpg-mssr.c	modified	+2	−1	View file
drivers/clk/renesas/r8a77990-cpg-mssr.c	modified	+6	−3	View file
drivers/clk/renesas/r8a77995-cpg-mssr.c	modified	+2	−1	View file
drivers/clk/renesas/r8a779a0-cpg-mssr.c	modified	+26	−317	View file
drivers/clk/renesas/r8a779f0-cpg-mssr.c	added	+183	−0	View file
drivers/clk/renesas/r9a07g044-cpg.c	modified	+72	−9	View file
drivers/clk/renesas/rcar-cpg-lib.c	modified	+27	−184	View file
drivers/clk/renesas/rcar-cpg-lib.h	modified	+5	−2	View file
drivers/clk/renesas/rcar-gen3-cpg.c	modified	+9	−15	View file
drivers/clk/renesas/rcar-gen3-cpg.h	modified	+4	−0	View file
drivers/clk/renesas/rcar-gen4-cpg.c	added	+305	−0	View file
drivers/clk/renesas/rcar-gen4-cpg.h	added	+76	−0	View file
drivers/clk/renesas/renesas-cpg-mssr.c	modified	+43	−17	View file
drivers/clk/renesas/renesas-cpg-mssr.h	modified	+2	−1	View file
drivers/clk/renesas/rzg2l-cpg.c	modified	+15	−3	View file
drivers/clk/renesas/rzg2l-cpg.h	modified	+9	−0	View file
drivers/clk/samsung/Makefile	modified	+2	−0	View file
drivers/clk/samsung/clk-cpu.c	modified	+1	−1	View file
drivers/clk/samsung/clk-cpu.h	modified	+0	−7	View file
drivers/clk/samsung/clk-exynos-arm64.c	added	+94	−0	View file
drivers/clk/samsung/clk-exynos-arm64.h	added	+20	−0	View file
drivers/clk/samsung/clk-exynos3250.c	modified	+27	−27	View file
drivers/clk/samsung/clk-exynos4.c	modified	+24	−17	View file
drivers/clk/samsung/clk-exynos5250.c	modified	+12	−9	View file
drivers/clk/samsung/clk-exynos5420.c	modified	+19	−10	View file
drivers/clk/samsung/clk-exynos7885.c	added	+597	−0	View file
drivers/clk/samsung/clk-exynos850.c	modified	+295	−71	View file
drivers/clk/samsung/clk-pll.c	modified	+1	−0	View file
drivers/clk/samsung/clk-pll.h	modified	+1	−0	View file
drivers/clk/samsung/clk-s3c2410.c	modified	+4	−2	View file
drivers/clk/samsung/clk-s3c64xx.c	modified	+6	−2	View file
drivers/clk/samsung/clk-s5pv210.c	modified	+6	−2	View file
drivers/clk/samsung/clk.c	modified	+0	−14	View file
drivers/clk/samsung/clk.h	modified	+17	−19	View file
drivers/clk/socfpga/clk-agilex.c	modified	+1	−3	View file
drivers/clk/socfpga/clk-gate.c	modified	+2	−2	View file
drivers/clk/socfpga/clk-pll-s10.c	modified	+1	−1	View file
drivers/clk/socfpga/clk-s10.c	modified	+1	−3	View file
drivers/clk/st/clkgen-fsyn.c	modified	+11	−2	View file
drivers/clk/st/clkgen-mux.c	modified	+9	−2	View file
drivers/clk/sunxi-ng/Kconfig	modified	+30	−19	View file
drivers/clk/sunxi-ng/Makefile	modified	+65	−36	View file
drivers/clk/sunxi-ng/ccu-sun20i-d1-r.c	added	+140	−0	View file
drivers/clk/sunxi-ng/ccu-sun20i-d1-r.h	added	+17	−0	View file
drivers/clk/sunxi-ng/ccu-sun20i-d1.c	added	+1390	−0	View file
drivers/clk/sunxi-ng/ccu-sun20i-d1.h	added	+15	−0	View file
drivers/clk/sunxi-ng/ccu-sun4i-a10.c	modified	+36	−22	View file
drivers/clk/sunxi-ng/ccu-sun50i-a100-r.c	modified	+3	−1	View file
drivers/clk/sunxi-ng/ccu-sun50i-a100.c	modified	+3	−1	View file
drivers/clk/sunxi-ng/ccu-sun50i-a64.c	modified	+5	−2	View file
drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c	modified	+35	−21	View file
drivers/clk/sunxi-ng/ccu-sun50i-h6.c	modified	+5	−2	View file
drivers/clk/sunxi-ng/ccu-sun50i-h616.c	modified	+23	−10	View file
drivers/clk/sunxi-ng/ccu-sun6i-a31.c	modified	+30	−10	View file
drivers/clk/sunxi-ng/ccu-sun8i-a23.c	modified	+25	−10	View file
drivers/clk/sunxi-ng/ccu-sun8i-a33.c	modified	+30	−10	View file
drivers/clk/sunxi-ng/ccu-sun8i-a83t.c	modified	+5	−2	View file
drivers/clk/sunxi-ng/ccu-sun8i-de2.c	modified	+6	−3	View file
drivers/clk/sunxi-ng/ccu-sun8i-h3.c	modified	+41	−21	View file
drivers/clk/sunxi-ng/ccu-sun8i-r.c	modified	+38	−27	View file
drivers/clk/sunxi-ng/ccu-sun8i-r40.c	modified	+5	−1	View file
drivers/clk/sunxi-ng/ccu-sun8i-v3s.c	modified	+35	−22	View file
drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c	modified	+5	−2	View file
drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c	modified	+5	−2	View file
drivers/clk/sunxi-ng/ccu-sun9i-a80.c	modified	+5	−2	View file
drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c	modified	+30	−10	View file
drivers/clk/sunxi-ng/ccu_common.c	modified	+6	−0	View file
drivers/clk/sunxi-ng/ccu_div.c	modified	+1	−0	View file
drivers/clk/sunxi-ng/ccu_div.h	modified	+78	−0	View file
drivers/clk/sunxi-ng/ccu_frac.c	modified	+6	−0	View file
drivers/clk/sunxi-ng/ccu_gate.c	modified	+4	−0	View file
drivers/clk/sunxi-ng/ccu_gate.h	modified	+31	−1	View file
drivers/clk/sunxi-ng/ccu_mp.c	modified	+2	−0	View file
drivers/clk/sunxi-ng/ccu_mp.h	modified	+49	−0	View file
drivers/clk/sunxi-ng/ccu_mult.c	modified	+1	−0	View file
drivers/clk/sunxi-ng/ccu_mux.c	modified	+6	−0	View file
drivers/clk/sunxi-ng/ccu_mux.h	modified	+33	−0	View file
drivers/clk/sunxi-ng/ccu_nk.c	modified	+1	−0	View file
drivers/clk/sunxi-ng/ccu_nkm.c	modified	+1	−0	View file
drivers/clk/sunxi-ng/ccu_nkmp.c	modified	+1	−0	View file
drivers/clk/sunxi-ng/ccu_nm.c	modified	+1	−0	View file
drivers/clk/sunxi-ng/ccu_phase.c	modified	+1	−0	View file
drivers/clk/sunxi-ng/ccu_reset.c	modified	+1	−0	View file
drivers/clk/sunxi-ng/ccu_sdm.c	modified	+6	−0	View file
drivers/clk/tegra/Makefile	modified	+1	−0	View file
drivers/clk/tegra/clk-device.c	added	+199	−0	View file
drivers/clk/tegra/clk-pll.c	modified	+1	−1	View file
drivers/clk/tegra/clk-super.c	modified	+1	−1	View file
drivers/clk/tegra/clk-tegra114.c	modified	+1	−1	View file
drivers/clk/tegra/clk-tegra20.c	modified	+59	−18	View file
drivers/clk/tegra/clk-tegra30.c	modified	+85	−31	View file
drivers/clk/tegra/clk.c	modified	+72	−3	View file
drivers/clk/tegra/clk.h	modified	+2	−0	View file
drivers/clk/ti/adpll.c	modified	+1	−1	View file
drivers/clk/visconti/Kconfig	added	+9	−0	View file
drivers/clk/visconti/Makefile	added	+5	−0	View file
drivers/clk/visconti/clkc-tmpv770x.c	added	+291	−0	View file
drivers/clk/visconti/clkc.c	added	+206	−0	View file
drivers/clk/visconti/clkc.h	added	+76	−0	View file
drivers/clk/visconti/pll-tmpv770x.c	added	+85	−0	View file
drivers/clk/visconti/pll.c	added	+340	−0	View file
drivers/clk/visconti/pll.h	added	+62	−0	View file
drivers/clk/visconti/reset.c	added	+107	−0	View file
drivers/clk/visconti/reset.h	added	+36	−0	View file
drivers/clk/x86/clk-fch.c	modified	+34	−14	View file
drivers/clk/zynq/pll.c	modified	+6	−6	View file
drivers/mmc/host/Kconfig	modified	+1	−0	View file
drivers/mmc/host/renesas_sdhi.h	modified	+4	−0	View file
drivers/mmc/host/renesas_sdhi_core.c	modified	+32	−13	View file
drivers/mmc/host/renesas_sdhi_internal_dmac.c	modified	+21	−0	View file
include/dt-bindings/clock/exynos4.h	modified	+3	−1	View file
include/dt-bindings/clock/exynos5250.h	modified	+3	−1	View file
include/dt-bindings/clock/exynos7885.h	added	+115	−0	View file
include/dt-bindings/clock/exynos850.h	modified	+52	−2	View file
include/dt-bindings/clock/imx8mp-clock.h	modified	+0	−1	View file
include/dt-bindings/clock/ingenic,jz4760-cgu.h	modified	+2	−0	View file
include/dt-bindings/clock/ingenic,jz4770-cgu.h	modified	+1	−0	View file
include/dt-bindings/clock/microchip,lan966x.h	added	+34	−0	View file
include/dt-bindings/clock/mt7986-clk.h	added	+169	−0	View file
include/dt-bindings/clock/qcom,gcc-msm8976.h	added	+240	−0	View file
include/dt-bindings/clock/sun20i-d1-ccu.h	added	+156	−0	View file
include/dt-bindings/clock/sun20i-d1-r-ccu.h	added	+19	−0	View file
include/dt-bindings/clock/toshiba,tmpv770x.h	added	+181	−0	View file
include/dt-bindings/reset/sun20i-d1-ccu.h	added	+77	−0	View file
include/dt-bindings/reset/sun20i-d1-r-ccu.h	added	+16	−0	View file
include/dt-bindings/reset/toshiba,tmpv770x.h	added	+41	−0	View file
include/linux/clk-provider.h	modified	+23	−0	View file
include/linux/clk/sunxi-ng.h	modified	+0	−15	View file
include/linux/mfd/tps68470.h	modified	+11	−0	View file
include/linux/platform_data/clk-fch.h	modified	+1	−1	View file

Only the first 600 diff lines are shown. Download the complete patch.

Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt

View file

diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
index ea827e8..3fa7558 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
@@ -14,6 +14,7 @@ Required Properties:
 	- "mediatek,mt7622-apmixedsys"
 	- "mediatek,mt7623-apmixedsys", "mediatek,mt2701-apmixedsys"
 	- "mediatek,mt7629-apmixedsys"
+	- "mediatek,mt7986-apmixedsys"
 	- "mediatek,mt8135-apmixedsys"
 	- "mediatek,mt8167-apmixedsys", "syscon"
 	- "mediatek,mt8173-apmixedsys"

Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt

View file

diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
index 6b7e806..0502db7 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
@@ -10,6 +10,7 @@ Required Properties:
 	- "mediatek,mt7622-ethsys", "syscon"
 	- "mediatek,mt7623-ethsys", "mediatek,mt2701-ethsys", "syscon"
 	- "mediatek,mt7629-ethsys", "syscon"
+	- "mediatek,mt7986-ethsys", "syscon"
 - #clock-cells: Must be 1
 - #reset-cells: Must be 1
 

Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt

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diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
index eb3523c..f66bd72 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
@@ -15,6 +15,7 @@ Required Properties:
 	- "mediatek,mt7622-infracfg", "syscon"
 	- "mediatek,mt7623-infracfg", "mediatek,mt2701-infracfg", "syscon"
 	- "mediatek,mt7629-infracfg", "syscon"
+	- "mediatek,mt7986-infracfg", "syscon"
 	- "mediatek,mt8135-infracfg", "syscon"
 	- "mediatek,mt8167-infracfg", "syscon"
 	- "mediatek,mt8173-infracfg", "syscon"

Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt

View file

diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt
index 30cb645..29ca7a1 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt
@@ -8,6 +8,8 @@ Required Properties:
 - compatible: Should be:
 	- "mediatek,mt7622-sgmiisys", "syscon"
 	- "mediatek,mt7629-sgmiisys", "syscon"
+	- "mediatek,mt7986-sgmiisys_0", "syscon"
+	- "mediatek,mt7986-sgmiisys_1", "syscon"
 - #clock-cells: Must be 1
 
 The SGMIISYS controller uses the common clk binding from

Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt

View file

diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
index 5ce7578..b82422b 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
@@ -14,6 +14,7 @@ Required Properties:
 	- "mediatek,mt7622-topckgen"
 	- "mediatek,mt7623-topckgen", "mediatek,mt2701-topckgen"
 	- "mediatek,mt7629-topckgen"
+	- "mediatek,mt7986-topckgen", "syscon"
 	- "mediatek,mt8135-topckgen"
 	- "mediatek,mt8167-topckgen", "syscon"
 	- "mediatek,mt8173-topckgen"

Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml

View file

diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml
index c4b7243..15ed64d 100644
--- a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml
+++ b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml
@@ -34,6 +34,8 @@ properties:
       - allwinner,sun8i-v3-ccu
       - allwinner,sun8i-v3s-ccu
       - allwinner,sun9i-a80-ccu
+      - allwinner,sun20i-d1-ccu
+      - allwinner,sun20i-d1-r-ccu
       - allwinner,sun50i-a64-ccu
       - allwinner,sun50i-a64-r-ccu
       - allwinner,sun50i-a100-ccu
@@ -79,6 +81,7 @@ if:
       enum:
         - allwinner,sun8i-a83t-r-ccu
         - allwinner,sun8i-h3-r-ccu
+        - allwinner,sun20i-d1-r-ccu
         - allwinner,sun50i-a64-r-ccu
         - allwinner,sun50i-a100-r-ccu
         - allwinner,sun50i-h6-r-ccu
@@ -99,6 +102,7 @@ else:
     properties:
       compatible:
         enum:
+          - allwinner,sun20i-d1-ccu
           - allwinner,sun50i-a100-ccu
           - allwinner,sun50i-h6-ccu
           - allwinner,sun50i-h616-ccu

Documentation/devicetree/bindings/clock/microchip,lan966x-gck.yaml

View file

diff --git a/Documentation/devicetree/bindings/clock/microchip,lan966x-gck.yaml b/Documentation/devicetree/bindings/clock/microchip,lan966x-gck.yaml
new file mode 100644
index 0000000..df2bec1
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/microchip,lan966x-gck.yaml
@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/microchip,lan966x-gck.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip LAN966X Generic Clock Controller
+
+maintainers:
+  - Kavyasree Kotagiri <[email protected]>
+
+description: |
+  The LAN966X Generic clock controller contains 3 PLLs - cpu_clk,
+  ddr_clk and sys_clk. This clock controller generates and supplies
+  clock to various peripherals within the SoC.
+
+properties:
+  compatible:
+    const: microchip,lan966x-gck
+
+  reg:
+    minItems: 1
+    items:
+      - description: Generic clock registers
+      - description: Optional gate clock registers
+
+  clocks:
+    items:
+      - description: CPU clock source
+      - description: DDR clock source
+      - description: System clock source
+
+  clock-names:
+    items:
+      - const: cpu
+      - const: ddr
+      - const: sys
+
+  '#clock-cells':
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    clks: clock-controller@e00c00a8 {
+        compatible = "microchip,lan966x-gck";
+        #clock-cells = <1>;
+        clocks = <&cpu_clk>, <&ddr_clk>, <&sys_clk>;
+        clock-names = "cpu", "ddr", "sys";
+        reg = <0xe00c00a8 0x38>;
+    };
+...

Documentation/devicetree/bindings/clock/qcom,gcc-msm8976.yaml

View file

diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8976.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8976.yaml
new file mode 100644
index 0000000..f3430b1
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8976.yaml
@@ -0,0 +1,97 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8976.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Global Clock & Reset Controller Binding for MSM8976
+
+maintainers:
+  - Stephen Boyd <[email protected]>
+  - Taniya Das <[email protected]>
+
+description: |
+  Qualcomm global clock control module which supports the clocks, resets and
+  power domains on MSM8976.
+
+  See also:
+  - dt-bindings/clock/qcom,gcc-msm8976.h
+
+properties:
+  compatible:
+    enum:
+      - qcom,gcc-msm8976
+      - qcom,gcc-msm8976-v1.1
+
+  clocks:
+    items:
+      - description: XO source
+      - description: Always-on XO source
+      - description: Pixel clock from DSI PHY0
+      - description: Byte clock from DSI PHY0
+      - description: Pixel clock from DSI PHY1
+      - description: Byte clock from DSI PHY1
+
+  clock-names:
+    items:
+      - const: xo
+      - const: xo_a
+      - const: dsi0pll
+      - const: dsi0pllbyte
+      - const: dsi1pll
+      - const: dsi1pllbyte
+
+  vdd_gfx-supply:
+    description:
+      Phandle to voltage regulator providing power to the GX domain.
+
+  '#clock-cells':
+    const: 1
+
+  '#reset-cells':
+    const: 1
+
+  '#power-domain-cells':
+    const: 1
+
+  reg:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - vdd_gfx-supply
+  - '#clock-cells'
+  - '#reset-cells'
+  - '#power-domain-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    clock-controller@1800000 {
+      compatible = "qcom,gcc-msm8976";
+      #clock-cells = <1>;
+      #reset-cells = <1>;
+      #power-domain-cells = <1>;
+      reg = <0x1800000 0x80000>;
+
+      clocks = <&xo_board>,
+               <&xo_board>,
+               <&dsi0_phy 1>,
+               <&dsi0_phy 0>,
+               <&dsi1_phy 1>,
+               <&dsi1_phy 0>;
+
+      clock-names = "xo",
+                    "xo_a",
+                    "dsi0pll",
+                    "dsi0pllbyte",
+                    "dsi1pll",
+                    "dsi1pllbyte";
+
+      vdd_gfx-supply = <&pm8004_s5>;
+    };
+...

Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml

View file

diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml
index 7221297..8406dde 100644
--- a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml
@@ -22,10 +22,12 @@ properties:
       - qcom,sc8180x-rpmh-clk
       - qcom,sdm845-rpmh-clk
       - qcom,sdx55-rpmh-clk
+      - qcom,sdx65-rpmh-clk
       - qcom,sm6350-rpmh-clk
       - qcom,sm8150-rpmh-clk
       - qcom,sm8250-rpmh-clk
       - qcom,sm8350-rpmh-clk
+      - qcom,sm8450-rpmh-clk
 
   clocks:
     maxItems: 1

Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml

View file

diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
index 9b414fb..e0b8621 100644
--- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
+++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
@@ -48,6 +48,7 @@ properties:
       - renesas,r8a77990-cpg-mssr # R-Car E3
       - renesas,r8a77995-cpg-mssr # R-Car D3
       - renesas,r8a779a0-cpg-mssr # R-Car V3U
+      - renesas,r8a779f0-cpg-mssr # R-Car S4-8
 
   reg:
     maxItems: 1

Documentation/devicetree/bindings/clock/samsung,exynos7885-clock.yaml

View file

diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos7885-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos7885-clock.yaml
new file mode 100644
index 0000000..7e5a9ca
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/samsung,exynos7885-clock.yaml
@@ -0,0 +1,166 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/samsung,exynos7885-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung Exynos7885 SoC clock controller
+
+maintainers:
+  - Dávid Virág <[email protected]>
+  - Chanwoo Choi <[email protected]>
+  - Krzysztof Kozlowski <[email protected]>
+  - Sylwester Nawrocki <[email protected]>
+  - Tomasz Figa <[email protected]>
+
+description: |
+  Exynos7885 clock controller is comprised of several CMU units, generating
+  clocks for different domains. Those CMU units are modeled as separate device
+  tree nodes, and might depend on each other. The root clock in that root tree
+  is an external clock: OSCCLK (26 MHz). This external clock must be defined
+  as a fixed-rate clock in dts.
+
+  CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
+  dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP.
+
+  Each clock is assigned an identifier and client nodes can use this identifier
+  to specify the clock which they consume. All clocks available for usage
+  in clock consumer nodes are defined as preprocessor macros in
+  'dt-bindings/clock/exynos7885.h' header.
+
+properties:
+  compatible:
+    enum:
+      - samsung,exynos7885-cmu-top
+      - samsung,exynos7885-cmu-core
+      - samsung,exynos7885-cmu-peri
+
+  clocks:
+    minItems: 1
+    maxItems: 10
+
+  clock-names:
+    minItems: 1
+    maxItems: 10
+
+  "#clock-cells":
+    const: 1
+
+  reg:
+    maxItems: 1
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos7885-cmu-top
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (26 MHz)
+
+        clock-names:
+          items:
+            - const: oscclk
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos7885-cmu-core
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (26 MHz)
+            - description: CMU_CORE bus clock (from CMU_TOP)
+            - description: CCI clock (from CMU_TOP)
+            - description: G3D clock (from CMU_TOP)
+
+        clock-names:
+          items:
+            - const: oscclk
+            - const: dout_core_bus
+            - const: dout_core_cci
+            - const: dout_core_g3d
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos7885-cmu-peri
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (26 MHz)
+            - description: CMU_PERI bus clock (from CMU_TOP)
+            - description: SPI0 clock (from CMU_TOP)
+            - description: SPI1 clock (from CMU_TOP)
+            - description: UART0 clock (from CMU_TOP)
+            - description: UART1 clock (from CMU_TOP)
+            - description: UART2 clock (from CMU_TOP)
+            - description: USI0 clock (from CMU_TOP)
+            - description: USI1 clock (from CMU_TOP)
+            - description: USI2 clock (from CMU_TOP)
+
+        clock-names:
+          items:
+            - const: oscclk
+            - const: dout_peri_bus
+            - const: dout_peri_spi0
+            - const: dout_peri_spi1
+            - const: dout_peri_uart0
+            - const: dout_peri_uart1
+            - const: dout_peri_uart2
+            - const: dout_peri_usi0
+            - const: dout_peri_usi1
+            - const: dout_peri_usi2
+
+required:
+  - compatible
+  - "#clock-cells"
+  - clocks
+  - clock-names
+  - reg
+
+additionalProperties: false
+
+examples:
+  # Clock controller node for CMU_PERI
+  - |
+    #include <dt-bindings/clock/exynos7885.h>
+
+    cmu_peri: clock-controller@10010000 {
+        compatible = "samsung,exynos7885-cmu-peri";
+        reg = <0x10010000 0x8000>;
+        #clock-cells = <1>;
+
+        clocks = <&oscclk>,
+                 <&cmu_top CLK_DOUT_PERI_BUS>,
+                 <&cmu_top CLK_DOUT_PERI_SPI0>,
+                 <&cmu_top CLK_DOUT_PERI_SPI1>,
+                 <&cmu_top CLK_DOUT_PERI_UART0>,
+                 <&cmu_top CLK_DOUT_PERI_UART1>,
+                 <&cmu_top CLK_DOUT_PERI_UART2>,
+                 <&cmu_top CLK_DOUT_PERI_USI0>,
+                 <&cmu_top CLK_DOUT_PERI_USI1>,
+                 <&cmu_top CLK_DOUT_PERI_USI2>;
+        clock-names = "oscclk",
+                      "dout_peri_bus",
+                      "dout_peri_spi0",
+                      "dout_peri_spi1",
+                      "dout_peri_uart0",
+                      "dout_peri_uart1",
+                      "dout_peri_uart2",
+                      "dout_peri_usi0",
+                      "dout_peri_usi1",
+                      "dout_peri_usi2";
+    };
+
+...

Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml

View file

diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
index 7f8c91a..80ba608 100644
--- a/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
@@ -32,6 +32,8 @@ properties:
   compatible:
     enum:
       - samsung,exynos850-cmu-top
+      - samsung,exynos850-cmu-apm
+      - samsung,exynos850-cmu-cmgp
       - samsung,exynos850-cmu-core
       - samsung,exynos850-cmu-dpu
       - samsung,exynos850-cmu-hsi
@@ -72,6 +74,42 @@ allOf:
       properties:
         compatible:
           contains:
+            const: samsung,exynos850-cmu-apm
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (26 MHz)
+            - description: CMU_APM bus clock (from CMU_TOP)
+
+        clock-names:
+          items:
+            - const: oscclk
+            - const: dout_clkcmu_apm_bus
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos850-cmu-cmgp
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (26 MHz)
+            - description: CMU_CMGP bus clock (from CMU_APM)
+
+        clock-names:
+          items:
+            - const: oscclk
+            - const: gout_clkcmu_cmgp_bus
+
+  - if:
+      properties:
+        compatible:
+          contains:
             const: samsung,exynos850-cmu-core
 
     then:

Documentation/devicetree/bindings/clock/toshiba,tmpv770x-pipllct.yaml

View file

diff --git a/Documentation/devicetree/bindings/clock/toshiba,tmpv770x-pipllct.yaml b/Documentation/devicetree/bindings/clock/toshiba,tmpv770x-pipllct.yaml
new file mode 100644
index 0000000..7b7300c
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/toshiba,tmpv770x-pipllct.yaml
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/toshiba,tmpv770x-pipllct.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Toshiba Visconti5 TMPV770X PLL Controller Device Tree Bindings
+
+maintainers:
+  - Nobuhiro Iwamatsu <[email protected]>
+
+description:
+  Toshia Visconti5 PLL controller which supports the PLLs on TMPV770X.
+
+properties:
+  compatible:
+    const: toshiba,tmpv7708-pipllct
+
+  reg:
+    maxItems: 1
+
+  '#clock-cells':
+    const: 1
+
+  clocks:
+    description: External reference clock (OSC2)
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - "#clock-cells"
+  - clocks
+
+additionalProperties: false
+
+examples:
+  - |
+
+    osc2_clk: osc2-clk {
+      compatible = "fixed-clock";
+      clock-frequency = <20000000>;
+      #clock-cells = <0>;
+    };
+
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        pipllct: clock-controller@24220000 {
+            compatible = "toshiba,tmpv7708-pipllct";
+            reg = <0 0x24220000 0 0x820>;
+            #clock-cells = <1>;
+            clocks = <&osc2_clk>;
+        };
+    };
+...

Documentation/devicetree/bindings/clock/toshiba,tmpv770x-pismu.yaml

View file

diff --git a/Documentation/devicetree/bindings/clock/toshiba,tmpv770x-pismu.yaml b/Documentation/devicetree/bindings/clock/toshiba,tmpv770x-pismu.yaml
new file mode 100644
index 0000000..ed79f16
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/toshiba,tmpv770x-pismu.yaml
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/toshiba,tmpv770x-pismu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Toshiba Visconti5 TMPV770x SMU controller Device Tree Bindings
+
+maintainers:
+  - Nobuhiro Iwamatsu <[email protected]>
+
+description:
+  Toshia Visconti5 SMU (System Management Unit) which supports the clock
+  and resets on TMPV770x.
+