Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

4ee64205 · Linus Torvalds <[email protected]> · 2026-04-21 08:33:26 -07:00

Pull clk updates from Stephen Boyd:
 "We've finally gotten rid of the struct clk_ops::round_rate() code
  after months of effort from Brian Masney. Now the only option is to
  use determine_rate(), which is good because that takes a struct
  argument instead of just a couple unsigned longs, allowing us to
  easily modify the way we determine and set rates in the clk tree.

  Beyond that core framework change we've got the typical pile of new
  SoC clk driver additions, fixes for clk data and/or adding missing
  clks because the consumer driver using those clks wasn't ready, etc.
  The usual suspects are all here: Qualcomm, Samsung, Mediatek, and
  Rockchip along with some newcomers making RISC-V SoCs like ESWIN's
  eic700 and Tenstorrent's Atlantis. The clk driver side of this looks
  pretty normal.

  Core:
   - Remove the round_rate() clk op (yay!)

  New Drivers:
   - ESWIN eic700 SoC clk support
   - Econet EN751221 SoC clock/reset support
   - Global TCSR, RPMh, and display clock controller support for the
     Qualcomm Eliza platform
   - TCSR, the multiple global, and the RPMh clock controller support
     for the Qualcomm Nord platform
   - GPU clock controller support for Qualcomm SM8750
   - Video and GPU clock controller support for Qualcomm Glymur
   - Global clock controller support for Qualcomm IPQ5210
   - Axis ARTPEC-9: Add new PLL clocks and new drivers for eight clock
     controllers on the SoC
   - ExynosAutov920: Add G3D (GPU) clock controller
   - Clock driver for the Rockchip RV1103B SoC
   - Initial support for the Renesas RZ/G3L (R9A08G046) SoC
   - Clock and reset controllers (e.g. PRCM) in the Tenstorrent Atlantis SoC"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (132 commits)
  clk: visconti: pll: initialize clk_init_data to zero
  clk: fsl-sai: Add MCLK generation support
  clk: fsl-sai: Extract clock setup into fsl_sai_clk_register()
  dt-bindings: clock: fsl-sai: Document clock-cells = <1> support
  clk: fsl-sai: Add i.MX8M support with 8 byte register offset
  clk: fsl-sai: Sort the headers
  dt-bindings: clock: fsl-sai: Document i.MX8M support
  clk: qcom: gcc: Add multiple global clock controller driver for Nord SoC
  clk: qcom: rpmh: Add support for Nord rpmh clocks
  clk: qcom: Add TCSR clock driver for Nord SoC
  dt-bindings: clock: qcom: Add Nord Global Clock Controller
  dt-bindings: clock: qcom-rpmhcc: Add support for Nord SoCs
  dt-bindings: clock: qcom: Document the Nord SoC TCSR Clock Controller
  clk: qcom: gcc-x1e80100: Keep GCC USB QTB clock always ON
  clk: qcom: Constify list of critical CBCR registers
  clk: qcom: Constify qcom_cc_driver_data
  clk: qcom: videocc-glymur: Constify qcom_cc_desc
  clk: qcom: Add a driver for SM8750 GPU clocks
  dt-bindings: clock: qcom: Add SM8750 GPU clocks
  clk: qcom: ipq-cmn-pll: Add IPQ8074 SoC support
  ...

Commit: 4ee64205ffaa587e8114d84a67ac721399ccb369
Parents: a85d6ff9 · 6b701fde

Merge commit. Changes below are compared with the first parent: a85d6ff9.

Changes

179 files changed · +24821 −3464

File	Status	Add	Del	Content
Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml	modified	+5	−1	View file
Documentation/devicetree/bindings/clock/baikal,bt1-ccu-div.yaml	deleted	+0	−196	View before deletion
Documentation/devicetree/bindings/clock/baikal,bt1-ccu-pll.yaml	deleted	+0	−131	View before deletion
Documentation/devicetree/bindings/clock/eswin,eic7700-clock.yaml	added	+46	−0	View file
Documentation/devicetree/bindings/clock/fsl,sai-clock.yaml	modified	+36	−7	View file
Documentation/devicetree/bindings/clock/imx6q-clock.yaml	modified	+4	−0	View file
Documentation/devicetree/bindings/clock/imx6ul-clock.yaml	modified	+4	−0	View file
Documentation/devicetree/bindings/clock/qcom,eliza-dispcc.yaml	added	+96	−0	View file
Documentation/devicetree/bindings/clock/qcom,glymur-dispcc.yaml	modified	+2	−2	View file
Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml	modified	+2	−0	View file
Documentation/devicetree/bindings/clock/qcom,kaanapali-gxclkctl.yaml	modified	+2	−0	View file
Documentation/devicetree/bindings/clock/qcom,milos-gcc.yaml	modified	+7	−0	View file
Documentation/devicetree/bindings/clock/qcom,nord-gcc.yaml	added	+58	−0	View file
Documentation/devicetree/bindings/clock/qcom,nord-negcc.yaml	added	+60	−0	View file
Documentation/devicetree/bindings/clock/qcom,nord-nwgcc.yaml	added	+55	−0	View file
Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml	modified	+1	−0	View file
Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml	modified	+26	−1	View file
Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml	modified	+3	−0	View file
Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml	modified	+2	−0	View file
Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml	modified	+21	−0	View file
Documentation/devicetree/bindings/clock/tenstorrent,atlantis-prcm-rcpu.yaml	added	+54	−0	View file
Documentation/devicetree/bindings/mfd/syscon.yaml	modified	+2	−0	View file
Documentation/driver-api/clk.rst	modified	+1	−8	View file
MAINTAINERS	modified	+14	−0	View file
drivers/clk/Kconfig	modified	+6	−5	View file
drivers/clk/Makefile	modified	+2	−1	View file
drivers/clk/baikal-t1/Kconfig	deleted	+0	−52	View before deletion
drivers/clk/baikal-t1/Makefile	deleted	+0	−4	View before deletion
drivers/clk/baikal-t1/ccu-div.c	deleted	+0	−653	View before deletion
drivers/clk/baikal-t1/ccu-div.h	deleted	+0	−121	View before deletion
drivers/clk/baikal-t1/ccu-pll.c	deleted	+0	−560	View before deletion
drivers/clk/baikal-t1/ccu-pll.h	deleted	+0	−72	View before deletion
drivers/clk/baikal-t1/ccu-rst.c	deleted	+0	−217	View before deletion
drivers/clk/baikal-t1/ccu-rst.h	deleted	+0	−67	View before deletion
drivers/clk/baikal-t1/clk-ccu-div.c	deleted	+0	−520	View before deletion
drivers/clk/baikal-t1/clk-ccu-pll.c	deleted	+0	−277	View before deletion
drivers/clk/bcm/clk-raspberrypi.c	modified	+34	−4	View file
drivers/clk/clk-composite.c	modified	+5	−33	View file
drivers/clk/clk-divider.c	modified	+0	−44	View file
drivers/clk/clk-en7523.c	modified	+218	−5	View file
drivers/clk/clk-fsl-sai.c	modified	+118	−30	View file
drivers/clk/clk-qoriq.c	modified	+9	−8	View file
drivers/clk/clk-xgene.c	modified	+2	−0	View file
drivers/clk/clk.c	modified	+17	−29	View file
drivers/clk/clk_test.c	modified	+8	−8	View file
drivers/clk/eswin/Kconfig	added	+15	−0	View file
drivers/clk/eswin/Makefile	added	+8	−0	View file
drivers/clk/eswin/clk-eic7700.c	added	+1376	−0	View file
drivers/clk/eswin/clk.c	added	+586	−0	View file
drivers/clk/eswin/common.h	added	+340	−0	View file
drivers/clk/imx/clk-fracn-gppll.c	modified	+2	−0	View file
drivers/clk/imx/clk-imx6q.c	modified	+11	−1	View file
drivers/clk/imx/clk-imx8-acm.c	modified	+2	−1	View file
drivers/clk/imx/clk-imx8mq.c	modified	+2	−2	View file
drivers/clk/imx/clk-pll14xx.c	modified	+3	−3	View file
drivers/clk/imx/clk-vf610.c	modified	+12	−0	View file
drivers/clk/microchip/clk-mpfs-ccc.c	modified	+5	−1	View file
drivers/clk/mvebu/armada-37xx-periph.c	modified	+9	−7	View file
drivers/clk/qcom/Kconfig	modified	+86	−8	View file
drivers/clk/qcom/Makefile	modified	+9	−0	View file
drivers/clk/qcom/apss-ipq5424.c	modified	+1	−1	View file
drivers/clk/qcom/cambistmclkcc-kaanapali.c	modified	+2	−4	View file
drivers/clk/qcom/cambistmclkcc-sm8750.c	modified	+2	−2	View file
drivers/clk/qcom/camcc-kaanapali.c	modified	+2	−4	View file
drivers/clk/qcom/camcc-milos.c	modified	+2	−2	View file
drivers/clk/qcom/camcc-qcs615.c	modified	+1	−1	View file
drivers/clk/qcom/camcc-sc8180x.c	modified	+32	−35	View file
drivers/clk/qcom/camcc-sm8450.c	modified	+2	−2	View file
drivers/clk/qcom/camcc-sm8550.c	modified	+2	−2	View file
drivers/clk/qcom/camcc-sm8650.c	modified	+2	−2	View file
drivers/clk/qcom/camcc-sm8750.c	modified	+2	−2	View file
drivers/clk/qcom/camcc-x1e80100.c	modified	+2	−2	View file
drivers/clk/qcom/clk-rcg2.c	modified	+2	−0	View file
drivers/clk/qcom/clk-rpmh.c	modified	+46	−0	View file
drivers/clk/qcom/common.h	modified	+2	−2	View file
drivers/clk/qcom/dispcc-eliza.c	added	+2121	−0	View file
drivers/clk/qcom/dispcc-glymur.c	modified	+4	−8	View file
drivers/clk/qcom/dispcc-kaanapali.c	modified	+2	−6	View file
drivers/clk/qcom/dispcc-milos.c	modified	+3	−6	View file
drivers/clk/qcom/dispcc-qcs615.c	modified	+2	−2	View file
drivers/clk/qcom/dispcc-sc7180.c	modified	+8	−0	View file
drivers/clk/qcom/dispcc-sc8280xp.c	modified	+0	−4	View file
drivers/clk/qcom/dispcc-sm4450.c	modified	+0	−1	View file
drivers/clk/qcom/dispcc-sm6115.c	modified	+7	−0	View file
drivers/clk/qcom/dispcc-sm6125.c	modified	+7	−0	View file
drivers/clk/qcom/dispcc-sm8250.c	modified	+3	−3	View file
drivers/clk/qcom/dispcc-sm8450.c	modified	+1	−1	View file
drivers/clk/qcom/dispcc0-sa8775p.c	modified	+0	−2	View file
drivers/clk/qcom/dispcc1-sa8775p.c	modified	+0	−2	View file
drivers/clk/qcom/gcc-eliza.c	added	+3105	−0	View file
drivers/clk/qcom/gcc-glymur.c	modified	+4	−4	View file
drivers/clk/qcom/gcc-ipq5210.c	added	+2661	−0	View file
drivers/clk/qcom/gcc-ipq6018.c	modified	+1	−1	View file
drivers/clk/qcom/gcc-kaanapali.c	modified	+2	−3	View file
drivers/clk/qcom/gcc-milos.c	modified	+2	−2	View file
drivers/clk/qcom/gcc-nord.c	added	+1902	−0	View file
drivers/clk/qcom/gcc-sc8180x.c	modified	+89	−37	View file
drivers/clk/qcom/gcc-x1e80100.c	modified	+1	−0	View file
drivers/clk/qcom/gdsc.c	modified	+11	−1	View file
drivers/clk/qcom/gpucc-glymur.c	added	+618	−0	View file
drivers/clk/qcom/gpucc-kaanapali.c	modified	+2	−3	View file
drivers/clk/qcom/gpucc-milos.c	modified	+2	−2	View file
drivers/clk/qcom/gpucc-qcs615.c	modified	+2	−2	View file
drivers/clk/qcom/gpucc-sm8750.c	added	+473	−0	View file
drivers/clk/qcom/gxclkctl-kaanapali.c	modified	+2	−1	View file
drivers/clk/qcom/ipq-cmn-pll.c	modified	+16	−0	View file
drivers/clk/qcom/negcc-nord.c	added	+1987	−0	View file
drivers/clk/qcom/nwgcc-nord.c	added	+688	−0	View file
drivers/clk/qcom/segcc-nord.c	added	+1609	−0	View file
drivers/clk/qcom/tcsrcc-eliza.c	added	+179	−0	View file
drivers/clk/qcom/tcsrcc-glymur.c	modified	+1	−2	View file
drivers/clk/qcom/tcsrcc-kaanapali.c	modified	+0	−1	View file
drivers/clk/qcom/tcsrcc-nord.c	added	+337	−0	View file
drivers/clk/qcom/tcsrcc-sm8750.c	modified	+1	−1	View file
drivers/clk/qcom/videocc-glymur.c	added	+532	−0	View file
drivers/clk/qcom/videocc-kaanapali.c	modified	+2	−2	View file
drivers/clk/qcom/videocc-milos.c	modified	+2	−2	View file
drivers/clk/qcom/videocc-qcs615.c	modified	+2	−2	View file
drivers/clk/qcom/videocc-sm8450.c	modified	+2	−2	View file
drivers/clk/qcom/videocc-sm8550.c	modified	+2	−2	View file
drivers/clk/qcom/videocc-sm8750.c	modified	+2	−3	View file
drivers/clk/renesas/Kconfig	modified	+6	−1	View file
drivers/clk/renesas/Makefile	modified	+1	−0	View file
drivers/clk/renesas/r9a06g032-clocks.c	modified	+3	−2	View file
drivers/clk/renesas/r9a07g043-cpg.c	modified	+9	−0	View file
drivers/clk/renesas/r9a07g044-cpg.c	modified	+13	−0	View file
drivers/clk/renesas/r9a08g045-cpg.c	modified	+9	−0	View file
drivers/clk/renesas/r9a08g046-cpg.c	added	+153	−0	View file
drivers/clk/renesas/r9a09g047-cpg.c	modified	+29	−0	View file
drivers/clk/renesas/r9a09g056-cpg.c	modified	+27	−33	View file
drivers/clk/renesas/r9a09g057-cpg.c	modified	+25	−35	View file
drivers/clk/renesas/renesas-cpg-mssr.c	modified	+2	−2	View file
drivers/clk/renesas/rzg2l-cpg.c	modified	+78	−13	View file
drivers/clk/renesas/rzg2l-cpg.h	modified	+8	−0	View file
drivers/clk/rockchip/Kconfig	modified	+7	−0	View file
drivers/clk/rockchip/Makefile	modified	+1	−0	View file
drivers/clk/rockchip/clk-rk3568.c	modified	+6	−0	View file
drivers/clk/rockchip/clk-rv1103b.c	added	+658	−0	View file
drivers/clk/rockchip/clk.h	modified	+49	−0	View file
drivers/clk/samsung/Makefile	modified	+1	−0	View file
drivers/clk/samsung/clk-artpec9.c	added	+1224	−0	View file
drivers/clk/samsung/clk-exynos850.c	modified	+6	−1	View file
drivers/clk/samsung/clk-exynosautov920.c	modified	+52	−0	View file
drivers/clk/samsung/clk-gs101.c	modified	+26	−26	View file
drivers/clk/samsung/clk-pll.c	modified	+177	−8	View file
drivers/clk/samsung/clk-pll.h	modified	+17	−0	View file
drivers/clk/samsung/clk.c	modified	+2	−2	View file
drivers/clk/spacemit/ccu_mix.c	modified	+1	−1	View file
drivers/clk/sunxi-ng/ccu-sun55i-a523-r.c	modified	+16	−1	View file
drivers/clk/tenstorrent/Kconfig	added	+14	−0	View file
drivers/clk/tenstorrent/Makefile	added	+3	−0	View file
drivers/clk/tenstorrent/atlantis-prcm.c	added	+870	−0	View file
drivers/clk/visconti/pll.c	modified	+1	−1	View file
drivers/reset/Kconfig	modified	+11	−0	View file
drivers/reset/Makefile	modified	+1	−0	View file
drivers/reset/reset-tenstorrent-atlantis.c	added	+173	−0	View file
include/dt-bindings/clock/bt1-ccu.h	deleted	+0	−48	View before deletion
include/dt-bindings/clock/econet,en751221-scu.h	added	+12	−0	View file
include/dt-bindings/clock/eswin,eic7700-clock.h	added	+285	−0	View file
include/dt-bindings/clock/exynos850.h	modified	+1	−0	View file
include/dt-bindings/clock/qcom,dispcc-sc7180.h	modified	+6	−1	View file
include/dt-bindings/clock/qcom,eliza-dispcc.h	added	+118	−0	View file
include/dt-bindings/clock/qcom,gcc-sc8180x.h	modified	+5	−0	View file
include/dt-bindings/clock/qcom,glymur-gcc.h	modified	+1	−0	View file
include/dt-bindings/clock/qcom,glymur-gpucc.h	added	+51	−0	View file
include/dt-bindings/clock/qcom,glymur-videocc.h	added	+45	−0	View file
include/dt-bindings/clock/qcom,ipq6018-cmn-pll.h	added	+15	−0	View file
include/dt-bindings/clock/qcom,ipq8074-cmn-pll.h	added	+15	−0	View file
include/dt-bindings/clock/qcom,nord-gcc.h	added	+147	−0	View file
include/dt-bindings/clock/qcom,nord-negcc.h	added	+124	−0	View file
include/dt-bindings/clock/qcom,nord-nwgcc.h	added	+69	−0	View file
include/dt-bindings/clock/qcom,nord-segcc.h	added	+98	−0	View file
include/dt-bindings/clock/qcom,nord-tcsrcc.h	added	+26	−0	View file
include/dt-bindings/clock/qcom,sm8750-gpucc.h	added	+50	−0	View file
include/dt-bindings/clock/samsung,exynosautov920.h	modified	+6	−0	View file
include/dt-bindings/clock/tenstorrent,atlantis-prcm-rcpu.h	added	+103	−0	View file
include/dt-bindings/clock/vf610-clock.h	modified	+5	−1	View file
include/dt-bindings/reset/econet,en751221-scu.h	added	+49	−0	View file
include/linux/clk-provider.h	modified	+26	−40	View file

Only the first 600 diff lines are shown. Download the complete patch.

Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml

View file

diff --git a/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml b/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml
index a847136..eb24a56 100644
--- a/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml
+++ b/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml
@@ -32,6 +32,7 @@ properties:
       - enum:
           - airoha,en7523-scu
           - airoha,en7581-scu
+          - econet,en751221-scu
 
   reg:
     items:
@@ -67,7 +68,9 @@ allOf:
   - if:
       properties:
         compatible:
-          const: airoha,en7581-scu
+          enum:
+            - airoha,en7581-scu
+            - econet,en751221-scu
     then:
       properties:
         reg:
@@ -98,3 +101,4 @@ examples:
               #reset-cells = <1>;
       };
     };
+

Documentation/devicetree/bindings/clock/baikal,bt1-ccu-div.yaml

View before deletion

diff --git a/Documentation/devicetree/bindings/clock/baikal,bt1-ccu-div.yaml b/Documentation/devicetree/bindings/clock/baikal,bt1-ccu-div.yaml
deleted file mode 100644
index 30252c9..0000000
--- a/Documentation/devicetree/bindings/clock/baikal,bt1-ccu-div.yaml
+++ /dev/null
@@ -1,196 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-div.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Baikal-T1 Clock Control Unit Dividers
-
-maintainers:
-  - Serge Semin <[email protected]>
-
-description: |
-  Clocks Control Unit is the core of Baikal-T1 SoC System Controller
-  responsible for the chip subsystems clocking and resetting. The CCU is
-  connected with an external fixed rate oscillator, which signal is transformed
-  into clocks of various frequencies and then propagated to either individual
-  IP-blocks or to groups of blocks (clock domains). The transformation is done
-  by means of an embedded into CCU PLLs and gateable/non-gateable dividers. The
-  later ones are described in this binding. Each clock domain can be also
-  individually reset by using the domain clocks divider configuration
-  registers. Baikal-T1 CCU is logically divided into the next components:
-  1) External oscillator (normally XTAL's 25 MHz crystal oscillator, but
-     in general can provide any frequency supported by the CCU PLLs).
-  2) PLLs clocks generators (PLLs).
-  3) AXI-bus clock dividers (AXI) - described in this binding file.
-  4) System devices reference clock dividers (SYS) - described in this binding
-     file.
-  which are connected with each other as shown on the next figure:
-
-          +---------------+
-          | Baikal-T1 CCU |
-          |   +----+------|- MIPS P5600 cores
-          | +-|PLLs|------|- DDR controller
-          | | +----+      |
-  +----+  | |  |  |       |
-  |XTAL|--|-+  |  | +---+-|
-  +----+  | |  |  +-|AXI|-|- AXI-bus
-          | |  |    +---+-|
-          | |  |          |
-          | |  +----+---+-|- APB-bus
-          | +-------|SYS|-|- Low-speed Devices
-          |         +---+-|- High-speed Devices
-          +---------------+
-
-  Each sub-block is represented as a separate DT node and has an individual
-  driver to be bound with.
-
-  In order to create signals of wide range frequencies the external oscillator
-  output is primarily connected to a set of CCU PLLs. Some of PLLs CLKOUT are
-  then passed over CCU dividers to create signals required for the target clock
-  domain (like AXI-bus or System Device consumers). The dividers have the
-  following structure:
-
-          +--------------+
-  CLKIN --|->+----+ 1|\  |
-  SETCLK--|--|/DIV|->| | |
-  CLKDIV--|--|    |  | |-|->CLKLOUT
-  LOCK----|--+----+  | | |
-          |          |/  |
-          |           |  |
-  EN------|-----------+  |
-  RST-----|--------------|->RSTOUT
-          +--------------+
-
-  where CLKIN is the reference clock coming either from CCU PLLs or from an
-  external clock oscillator, SETCLK - a command to update the output clock in
-  accordance with a set divider, CLKDIV - clocks divider, LOCK - a signal of
-  the output clock stabilization, EN - enable/disable the divider block,
-  RST/RSTOUT - reset clocks domain signal. Depending on the consumer IP-core
-  peculiarities the dividers may lack of some functionality depicted on the
-  figure above (like EN, CLKDIV/LOCK/SETCLK). In this case the corresponding
-  clock provider just doesn't expose either switching functions, or the rate
-  configuration, or both of them.
-
-  The clock dividers, which output clock is then consumed by the SoC individual
-  devices, are united into a single clocks provider called System Devices CCU.
-  Similarly the dividers with output clocks utilized as AXI-bus reference clocks
-  are called AXI-bus CCU. Both of them use the common clock bindings with no
-  custom properties. The list of exported clocks and reset signals can be found
-  in the files: 'include/dt-bindings/clock/bt1-ccu.h' and
-  'include/dt-bindings/reset/bt1-ccu.h'. Since System Devices and AXI-bus CCU
-  are a part of the Baikal-T1 SoC System Controller their DT nodes are supposed
-  to be a children of later one.
-
-if:
-  properties:
-    compatible:
-      contains:
-        const: baikal,bt1-ccu-axi
-
-then:
-  properties:
-    clocks:
-      items:
-        - description: CCU SATA PLL output clock
-        - description: CCU PCIe PLL output clock
-        - description: CCU Ethernet PLL output clock
-
-    clock-names:
-      items:
-        - const: sata_clk
-        - const: pcie_clk
-        - const: eth_clk
-
-else:
-  properties:
-    clocks:
-      items:
-        - description: External reference clock
-        - description: CCU SATA PLL output clock
-        - description: CCU PCIe PLL output clock
-        - description: CCU Ethernet PLL output clock
-
-    clock-names:
-      items:
-        - const: ref_clk
-        - const: sata_clk
-        - const: pcie_clk
-        - const: eth_clk
-
-properties:
-  compatible:
-    enum:
-      - baikal,bt1-ccu-axi
-      - baikal,bt1-ccu-sys
-
-  reg:
-    maxItems: 1
-
-  "#clock-cells":
-    const: 1
-
-  "#reset-cells":
-    const: 1
-
-  clocks:
-    minItems: 3
-    maxItems: 4
-
-  clock-names:
-    minItems: 3
-    maxItems: 4
-
-additionalProperties: false
-
-required:
-  - compatible
-  - "#clock-cells"
-  - clocks
-  - clock-names
-
-examples:
-  # AXI-bus Clock Control Unit node:
-  - |
-    #include <dt-bindings/clock/bt1-ccu.h>
-
-    clock-controller@1f04d030 {
-      compatible = "baikal,bt1-ccu-axi";
-      reg = <0x1f04d030 0x030>;
-      #clock-cells = <1>;
-      #reset-cells = <1>;
-
-      clocks = <&ccu_pll CCU_SATA_PLL>,
-               <&ccu_pll CCU_PCIE_PLL>,
-               <&ccu_pll CCU_ETH_PLL>;
-      clock-names = "sata_clk", "pcie_clk", "eth_clk";
-    };
-  # System Devices Clock Control Unit node:
-  - |
-    #include <dt-bindings/clock/bt1-ccu.h>
-
-    clock-controller@1f04d060 {
-      compatible = "baikal,bt1-ccu-sys";
-      reg = <0x1f04d060 0x0a0>;
-      #clock-cells = <1>;
-      #reset-cells = <1>;
-
-      clocks = <&clk25m>,
-               <&ccu_pll CCU_SATA_PLL>,
-               <&ccu_pll CCU_PCIE_PLL>,
-               <&ccu_pll CCU_ETH_PLL>;
-      clock-names = "ref_clk", "sata_clk", "pcie_clk",
-                    "eth_clk";
-    };
-  # Required Clock Control Unit PLL node:
-  - |
-    ccu_pll: clock-controller@1f04d000 {
-      compatible = "baikal,bt1-ccu-pll";
-      reg = <0x1f04d000 0x028>;
-      #clock-cells = <1>;
-
-      clocks = <&clk25m>;
-      clock-names = "ref_clk";
-    };
-...

Documentation/devicetree/bindings/clock/baikal,bt1-ccu-pll.yaml

View before deletion

diff --git a/Documentation/devicetree/bindings/clock/baikal,bt1-ccu-pll.yaml b/Documentation/devicetree/bindings/clock/baikal,bt1-ccu-pll.yaml
deleted file mode 100644
index 7f8d982..0000000
--- a/Documentation/devicetree/bindings/clock/baikal,bt1-ccu-pll.yaml
+++ /dev/null
@@ -1,131 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-pll.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Baikal-T1 Clock Control Unit PLL
-
-maintainers:
-  - Serge Semin <[email protected]>
-
-description: |
-  Clocks Control Unit is the core of Baikal-T1 SoC System Controller
-  responsible for the chip subsystems clocking and resetting. The CCU is
-  connected with an external fixed rate oscillator, which signal is transformed
-  into clocks of various frequencies and then propagated to either individual
-  IP-blocks or to groups of blocks (clock domains). The transformation is done
-  by means of PLLs and gateable/non-gateable dividers embedded into the CCU.
-  It's logically divided into the next components:
-  1) External oscillator (normally XTAL's 25 MHz crystal oscillator, but
-     in general can provide any frequency supported by the CCU PLLs).
-  2) PLLs clocks generators (PLLs) - described in this binding file.
-  3) AXI-bus clock dividers (AXI).
-  4) System devices reference clock dividers (SYS).
-  which are connected with each other as shown on the next figure:
-
-          +---------------+
-          | Baikal-T1 CCU |
-          |   +----+------|- MIPS P5600 cores
-          | +-|PLLs|------|- DDR controller
-          | | +----+      |
-  +----+  | |  |  |       |
-  |XTAL|--|-+  |  | +---+-|
-  +----+  | |  |  +-|AXI|-|- AXI-bus
-          | |  |    +---+-|
-          | |  |          |
-          | |  +----+---+-|- APB-bus
-          | +-------|SYS|-|- Low-speed Devices
-          |         +---+-|- High-speed Devices
-          +---------------+
-
-  Each CCU sub-block is represented as a separate dts-node and has an
-  individual driver to be bound with.
-
-  In order to create signals of wide range frequencies the external oscillator
-  output is primarily connected to a set of CCU PLLs. There are five PLLs
-  to create a clock for the MIPS P5600 cores, the embedded DDR controller,
-  SATA, Ethernet and PCIe domains. The last three domains though named by the
-  biggest system interfaces in fact include nearly all of the rest SoC
-  peripherals. Each of the PLLs is based on True Circuits TSMC CLN28HPM core
-  with an interface wrapper (so called safe PLL' clocks switcher) to simplify
-  the PLL configuration procedure. The PLLs work as depicted on the next
-  diagram:
-
-      +--------------------------+
-      |                          |
-      +-->+---+    +---+   +---+ |  +---+   0|\
-  CLKF--->|/NF|--->|PFD|...|VCO|-+->|/OD|--->| |
-          +---+ +->+---+   +---+ /->+---+    | |--->CLKOUT
-  CLKOD---------C----------------+          1| |
-       +--------C--------------------------->|/
-       |        |                             ^
-  Rclk-+->+---+ |                             |
-  CLKR--->|/NR|-+                             |
-          +---+                               |
-  BYPASS--------------------------------------+
-  BWADJ--->
-
-  where Rclk is the reference clock coming  from XTAL, NR - reference clock
-  divider, NF - PLL clock multiplier, OD - VCO output clock divider, CLKOUT -
-  output clock, BWADJ is the PLL bandwidth adjustment parameter. At this moment
-  the binding supports the PLL dividers configuration in accordance with a
-  requested rate, while bypassing and bandwidth adjustment settings can be
-  added in future if it gets to be necessary.
-
-  The PLLs CLKOUT is then either directly connected with the corresponding
-  clocks consumer (like P5600 cores or DDR controller) or passed over a CCU
-  divider to create a signal required for the clock domain.
-
-  The CCU PLL dts-node uses the common clock bindings with no custom
-  parameters. The list of exported clocks can be found in
-  'include/dt-bindings/clock/bt1-ccu.h'. Since CCU PLL is a part of the
-  Baikal-T1 SoC System Controller its DT node is supposed to be a child of
-  later one.
-
-properties:
-  compatible:
-    const: baikal,bt1-ccu-pll
-
-  reg:
-    maxItems: 1
-
-  "#clock-cells":
-    const: 1
-
-  clocks:
-    description: External reference clock
-    maxItems: 1
-
-  clock-names:
-    const: ref_clk
-
-additionalProperties: false
-
-required:
-  - compatible
-  - "#clock-cells"
-  - clocks
-  - clock-names
-
-examples:
-  # Clock Control Unit PLL node:
-  - |
-    clock-controller@1f04d000 {
-      compatible = "baikal,bt1-ccu-pll";
-      reg = <0x1f04d000 0x028>;
-      #clock-cells = <1>;
-
-      clocks = <&clk25m>;
-      clock-names = "ref_clk";
-    };
-  # Required external oscillator:
-  - |
-    clk25m: clock-oscillator-25m {
-      compatible = "fixed-clock";
-      #clock-cells = <0>;
-      clock-frequency = <25000000>;
-      clock-output-names = "clk25m";
-    };
-...

Documentation/devicetree/bindings/clock/eswin,eic7700-clock.yaml

View file

diff --git a/Documentation/devicetree/bindings/clock/eswin,eic7700-clock.yaml b/Documentation/devicetree/bindings/clock/eswin,eic7700-clock.yaml
new file mode 100644
index 0000000..3125ae5
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/eswin,eic7700-clock.yaml
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/eswin,eic7700-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Eswin EIC7700 SoC clock controller
+
+maintainers:
+  - Yifeng Huang <[email protected]>
+  - Xuyang Dong <[email protected]>
+
+description:
+  The clock controller generates and supplies clock to all the modules
+  for eic7700 SoC.
+
+properties:
+  compatible:
+    const: eswin,eic7700-clock
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: External 24MHz oscillator clock
+
+  '#clock-cells':
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    clock-controller@51828000 {
+        compatible = "eswin,eic7700-clock";
+        reg = <0x51828000 0x300>;
+        clocks = <&xtal24m>;
+        #clock-cells = <1>;
+    };

Documentation/devicetree/bindings/clock/fsl,sai-clock.yaml

View file

diff --git a/Documentation/devicetree/bindings/clock/fsl,sai-clock.yaml b/Documentation/devicetree/bindings/clock/fsl,sai-clock.yaml
index 3bca9d1..041a63f 100644
--- a/Documentation/devicetree/bindings/clock/fsl,sai-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/fsl,sai-clock.yaml
@@ -10,10 +10,10 @@ maintainers:
   - Michael Walle <[email protected]>
 
 description: |
-  It is possible to use the BCLK pin of a SAI module as a generic clock
-  output. Some SoC are very constrained in their pin multiplexer
-  configuration. Eg. pins can only be changed groups. For example, on the
-  LS1028A SoC you can only enable SAIs in pairs. If you use only one SAI,
+  It is possible to use the BCLK or MCLK pin of a SAI module as a generic
+  clock output. Some SoC are very constrained in their pin multiplexer
+  configuration. E.g. pins can only be changed in groups. For example, on
+  the LS1028A SoC you can only enable SAIs in pairs. If you use only one SAI,
   the second pins are wasted. Using this binding it is possible to use the
   clock of the second SAI as a MCLK clock for an audio codec, for example.
 
@@ -21,16 +21,45 @@ description: |
 
 properties:
   compatible:
-    const: fsl,vf610-sai-clock
+    oneOf:
+      - items:
+          - enum:
+              - fsl,imx8mm-sai-clock
+              - fsl,imx8mn-sai-clock
+              - fsl,imx8mp-sai-clock
+          - const: fsl,imx8mq-sai-clock
+      - items:
+          - enum:
+              - fsl,imx8mq-sai-clock
+              - fsl,vf610-sai-clock
 
   reg:
     maxItems: 1
 
   clocks:
-    maxItems: 1
+    minItems: 1
+    maxItems: 2
+
+  clock-names:
+    minItems: 1
+    items:
+      - const: bus
+      - const: mclk1
 
   '#clock-cells':
-    const: 0
+    maximum: 1
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: fsl,vf610-sai-clock
+    then:
+      properties:
+        clocks:
+          maxItems: 1
+        clock-names: false
 
 required:
   - compatible

Documentation/devicetree/bindings/clock/imx6q-clock.yaml

View file

diff --git a/Documentation/devicetree/bindings/clock/imx6q-clock.yaml b/Documentation/devicetree/bindings/clock/imx6q-clock.yaml
index cd3c04c..0e6febe 100644
--- a/Documentation/devicetree/bindings/clock/imx6q-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/imx6q-clock.yaml
@@ -29,20 +29,24 @@ properties:
     const: 1
 
   clocks:
+    minItems: 5
     items:
       - description: 24m osc
       - description: 32k osc
       - description: ckih1 clock input
       - description: anaclk1 clock input
       - description: anaclk2 clock input
+      - description: clock input from enet ref pad
 
   clock-names:
+    minItems: 5
     items:
       - const: osc
       - const: ckil
       - const: ckih1
       - const: anaclk1
       - const: anaclk2
+      - const: enet_ref_pad
 
   fsl,pmic-stby-poweroff:
     $ref: /schemas/types.yaml#/definitions/flag

Documentation/devicetree/bindings/clock/imx6ul-clock.yaml

View file

diff --git a/Documentation/devicetree/bindings/clock/imx6ul-clock.yaml b/Documentation/devicetree/bindings/clock/imx6ul-clock.yaml
index d57e18a..0350027 100644
--- a/Documentation/devicetree/bindings/clock/imx6ul-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/imx6ul-clock.yaml
@@ -29,18 +29,22 @@ properties:
     const: 1
 
   clocks:
+    minItems: 4
     items:
       - description: 32k osc
       - description: 24m osc
       - description: ipp_di0 clock input
       - description: ipp_di1 clock input
+      - description: clock input from enet1 ref pad
 
   clock-names:
+    minItems: 4
     items:
       - const: ckil
       - const: osc
       - const: ipp_di0
       - const: ipp_di1
+      - const: enet1_ref_pad
 
 required:
   - compatible

Documentation/devicetree/bindings/clock/qcom,eliza-dispcc.yaml

View file

diff --git a/Documentation/devicetree/bindings/clock/qcom,eliza-dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,eliza-dispcc.yaml
new file mode 100644
index 0000000..0935ec1
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,eliza-dispcc.yaml
@@ -0,0 +1,96 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,eliza-dispcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Display Clock & Reset Controller for Qualcomm Eliza SoC
+
+maintainers:
+  - Bjorn Andersson <[email protected]>
+  - Konrad Dybcio <[email protected]>
+  - Krzysztof Kozlowski <[email protected]>
+
+description: |
+  Display clock control module provides the clocks, resets and power
+  domains on Qualcomm Eliza SoC platform.
+
+  See also:
+  - include/dt-bindings/clock/qcom,eliza-dispcc.h
+
+properties:
+  compatible:
+    enum:
+      - qcom,eliza-dispcc
+
+  clocks:
+    items:
+      - description: Board XO source
+      - description: Board Always On XO source
+      - description: Display's AHB clock
+      - description: sleep clock
+      - description: Byte clock from DSI PHY0
+      - description: Pixel clock from DSI PHY0
+      - description: Byte clock from DSI PHY1
+      - description: Pixel clock from DSI PHY1
+      - description: Link clock from DP PHY0
+      - description: VCO DIV clock from DP PHY0
+      - description: Link clock from DP PHY1
+      - description: VCO DIV clock from DP PHY1
+      - description: Link clock from DP PHY2
+      - description: VCO DIV clock from DP PHY2
+      - description: Link clock from DP PHY3
+      - description: VCO DIV clock from DP PHY3
+      - description: HDMI link clock from HDMI PHY
+
+  power-domains:
+    maxItems: 1
+
+  required-opps:
+    maxItems: 1
+