projects/linux·commit 570f7e33

Merge tag 'pci-v7.3-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci

570f7e33 · Linus Torvalds <[email protected]> · 2026-08-23 12:44:10 -07:00

Pull PCI updates from Bjorn Helgaas:
 "Resource management:

   - Add hotplug reservation only once (not at each level of the
     hierarchy) so bridge windows don't grow more than necessary (Ilpo
     Järvinen)

  Driver binding:

   - Rework device matching so device ID lifetime only needs to cover
     the probe path since dynamic IDs can be removed at any time (Gary
     Guo)

  Error handling:

   - Update mappings of AER errors to agent & layer and log them for
     each individual error when multiple errors detected (Lukas Wunner)

   - Log Error Source only once, not twice in separate messages (Lukas
     Wunner)

   - Emit TLP Log only for unmasked errors (Lukas Wunner)

   - Support Advisory Non-Fatal Errors (Lukas Wunner)

   - Allow DPC on all Downstream Ports, not just Root Ports, when OS
     controls AER (Darshit Shah)

  ASPM:

   - Program the same ASPM Control values for every function of
     multi-function devices, as recommended by the PCIe spec (Krishna
     Chaitanya Chundru)

   - Avoid L0s for Realtek RTS525A, where it causes an AER interrupt
     storm (Max Lee)

   - Avoid ASPM L0s, L1, and L1 PM Substates based on 'aspm-no-l0s',
     'aspm-no-l1' [1], and 'aspm-no-l1ss' DT properties (Krishna
     Chaitanya Chundru)

  Power management:

   - Allow D3 for native hotplug-capable Root Ports on non-x86 platforms
     (we avoid D3 for these ports on x86 because some old platforms
     didn't validate it) (Manivannan Sadhasivam)

   - Allow portdrv to claim Ports even if they don't support services
     (AER, PME, DPC, hotplug, etc) so it can do power management (Brian
     Norris)

  Power control:

   - Add support for PCIe WAKE# interrupt when described via DT (Krishna
     Chaitanya Chundru)

   - For the TC9563 PCIe switch:

       - Take a reference on the I2C adapter to avoid uninterruptible
         hang when unloading an I2C module while in-use (Johan Hovold)

       - Update DT binding and driver to restrict Tx Amplitude, DFE and
         N_FTS to USP, DSP1 and DSP2 (Manivannan Sadhasivam)

       - Power off only external-facing ports (DSP1, DSP2), leaving USP
         and DSP3 (aka VDSP) powered up (Manivannan Sadhasivam)

       - Move integrated MAC Endpoint out of the list of internal ports
         and configure it separately (Manivannan Sadhasivam)

  Virtualization:

   - Add ACS quirk for Pericom PI7C9X2G608 switches (Tim Harvey)

   - Fix a long-standing bug in the Intel PCH Root Port MPC ACS quirk
     that didn't update the intended INTEL_MPC_REG_IRBNCE bit because it
     used a 16-bit config write when a 32-bit write was intended
     (Mohamad Raizudeen)

  Procfs:

   - Avoid spurious runtime PM wakeup on config space accesses that are
     outside config space and fail before reaching PCI (Krzysztof
     Wilczyński)

   - Warn on user-space writes to kernel-exclusive config space regions,
     as we already do for sysfs (Krzysztof Wilczyński)

   - Check credentials of opener, not reader, for config space reads, as
     we already do for sysfs (Krzysztof Wilczyński)

  Sysfs:

   - In pci_write_legacy_io(), avoid out-of-bounds reads from the user
     buffer and fix incorrect ioport write data (1-byte writes on
     little-endian powerpc, 2- and 4-byte writes on big-endian powerpc)
     (Krzysztof Wilczyński)

   - In pci_read_legacy_io(), fix incorrect ioport read data for 2- and
     4-byte reads on big-endian powerpc (Krzysztof Wilczyński)

   - Fix I/O port accessor argument order in Alpha pci_legacy_write()
     (Krzysztof Wilczyński)

   - Avoid spurious runtime PM wakeup on config space accesses that are
     outside config space and fail before reaching PCI (Krzysztof
     Wilczyński)

   - Return -EINVAL, not -ENODEV, for mmap of I/O BAR that fails because
     the arch doesn't support it, as we do for procfs (Krzysztof
     Wilczyński)

   - Check for LOCKDOWN_PCI_ACCESS for legacy_io and legacy_mem, as we
     do for other config space accessors (Krzysztof Wilczyński)

  Peer-to-peer DMA:

   - Add Nvidia Vera Rubin to list of platforms that support P2PDMA
     (Leon Romanovsky)

  Endpoint framework:

   - Check doorbell SUCCESS bit in pci_endpoint_test to avoid treating
     some failures as successes (Niklas Cassel)

   - Fail doorbell test when the trigger IRQ is missed (Niklas Cassel)

  New native PCIe controller drivers:

   - Add DT binding and driver for NVIDIA Tegra264 (Thierry Reding)

  Native PCIe controllers:

   - Use common wait time definitions for PCIe link monitoring instead
     of defining driver-private duplicates (Thierry Reding)

  Generic host bridge driver:

   - Fix NULL pointer dereference that caused enumeration failures on
     32-bit CAM systems (Steffen Persvold)

  Amlogic Meson PCIe controller driver:

   - Correct the PERST# GPIO state so it remains asserted until power
     and REFCLK become stable to fix enumeration failure (Ronald
     Claveau)

  ASPEED PCIe controller driver:

   - Switch to irq_domain_create_linear() so we can obsolete
     irq_domain_add_linear() (Jiri Slaby)

  Cadence PCIe controller driver:

   - Add MODULE_DEVICE_TABLE to generate module aliases for OF-based
     module autoloading (Pengpeng Hou)

   - Add debugfs 'ltssm_status' file for LGA- and HPA-based Cadence
     controllers (Hans Zhang)

   - Support up to x4 (not x2) lanes for J200 (Takuma Fujiwara)

   - Fix host/endpoint dependencies for cadence-plat driver to fix link
     error when cadence-plat is built-in but the host or endpoint driver
     is modular (Aksh Garg)

  Freescale i.MX6 PCIe controller driver:

   - Add imx6 intr/aer/pme interrupt lines for i.MX95 (Richard Zhu)

   - Remove PERST# checking from pci_host_common_parse_port() so callers
     can decide whether to fall back to legacy DT binding with PERST# in
     the host bridge (Sherry Sun)

   - Fix build issues when PCI_PWRCTRL_GENERIC or PCI_HOST_COMMON is a
     module (Arnd Bergmann)

   - Create pwrctrl devices only once by doing it from imx_pcie_probe()
     instead of imx_pcie_host_init(), which is used during both probe
     and resume (Sherry Sun)

   - Use 'dw_pcie_rp->skip_pwrctrl_off' to avoid powering off devices
     during suspend to preserve wakeup capability (Sherry Sun)

   - Add runtime PM support for i.MX95 to allow dynamic power management
     when the link is idle (Richard Zhu)

  Intel VMD host bridge driver:

   - Support device ID 0x28C1 and assume that BIOS has already
     enumerated the hierarchy below VMD and stored bus range info for OS
     to use (Nirmal Patel)

   - Add support for VMCONFIG BUS_RESTRICT_CFG=3, which makes it
     possible to enumerate downstream devices on Intel Arrow Lake-HX
     systems and probably others (Ali Alaei)

   - Pay attention to _OSC negotiation for VMD hierarchy only when
     running on bare metal, not when running in a VM (Nirmal Patel)

   - Add Nova Lake (NVL) and Dunlow (DNL) Device IDs (Szymon Durawa)

  MediaTek PCIe controller driver:

   - Add support for PCIe controller in EcoNet EN7528 and EN751221 SoCs
     (Caleb James DeLisle)

  MediaTek PCIe Gen3 controller driver:

   - Add mediatek-gen3 'memory-region' for restricted DMA buffer
     (Chen-Yu Tsai)

  NVIDIA Tegra264 PCIe controller driver:

   - Distinguish Tegra264 C0 PCIe controller for internal GPU from C1-C5
     controllers so the unit address matches the first 'reg' entry
     (Thierry Reding)

   - Add Tegra264 Root Port stanzas to prepare for generic WAKE#
     handling (Thierry Reding)

  Qualcomm PCIe controller driver:

   - Add IPQ9650 compatible with global interrupt (Kathiravan
     Thirumoorthy)

   - Add IPQ5210 compatible with IPQ9574 fallback (Varadarajan
     Narayanan)

   - Add DT binding and driver support for Hawi SoC (Matthew Leung)

   - Skip PERST# GPIOs provided by downstream PCIe devices, which should
     be handled by drivers of those devices (Manivannan Sadhasivam)

   - Stop advertising Attention Button Present (no Qcom SoCs support
     Attention Buttons) so pciehp can use Presence Detect Changed events
     (Qiang Yu)

  Renesas R-Car PCIe controller driver:

   - Add rcar-gen4-pci-host optional 'msi-parent' for GIT ITS (Marek
     Vasut)

   - When MSI is enabled but iMSI-RX is not used, configure AXIINTC to
     allow GIT ITS to handle MSI (Marek Vasut)

   - Refactor GIC600 implementation to make it easier to add platforms
     that only support 32-bit addressing (Marek Vasut)

   - Add Renesas R-Car Gen4 S4/V4H/V4M to the list of GIC600
     integrations that only support 32-bit addressing (Marek Vasut)

  Renesas RZ/G3S PCIe controller driver:

   - Add DT binding and driver support for RZ/V2H(P) SoC, which contains
     two PCIe controllers, configured either as a single x4 link or two
     independent x2 link controllers (Lad Prabhakar)

  SpacemiT K1 PCIe controller driver:

   - Add missing MODULE_DEVICE_TABLE() to generate module alias info for
     OF-based module autoloading (Pengpeng Hou)

  StarFive PCIe controller driver:

   - Fix resource leaks on error paths in host_init() (Ali Tariq)

   - Fix runtime PM handling and teardown ordering to avoid register
     access while power or clocks are disabled (Ali Tariq)

   - Check for runtime PM resume failure to avoid register access while
     power or clocks are disabled (Ali Tariq)

  Synopsys DesignWare PCIe controller driver:

   - Add LECARC PMU IDs to the DWC RAS/DES VSEC list so it can take
     advantage of the existing debugfs support for silicon debug, error
     injection, and event counters (Brett Zhou)

   - Factor pcie_valid_speed() and pci_bus_speed2lnkctl2() out of bwctrl
     so they can be shared by the DWC core (Hans Zhang)

   - Flush MSI writes from endpoint before unmapping the iATU, as we
     already do for MSI-X writes (Niklas Cassel)

   - Unmap MSI iATU window before mapping MSI-X window, to avoid a
     subsequent MSI write using a disabled aperture and losing the
     interrupt (Niklas Cassel)

   - Change endpoint .pre_init() and .init() callbacks to return errors
     and handle them (Marek Vasut)

  UltraRISC PCIe controller driver:

   - Add 'core', 'dbi', and 'aux' clocks to DT binding and manage them
     in the driver (Jia Wang)

   - Use module_platform_driver() since this may be built as a module,
     though not removable because IRQs can't be safely disposed (Jia
     Wang)

  MicroSemi Switchtec management driver:

   - Add Microchip PCI1008 device ID and include it in NTB DMA alias
     quirk (Logan Gunthorpe)

  Miscellaneous:

   - Document how to write PCI Host Controller drivers (Manivannan
     Sadhasivam)

   - Fix typos in documentation (D'Orus Tsitera)

   - Use %pe format specifier to print error pointers so we get symbolic
     errname when available (Krzysztof Wilczyński)"

* tag 'pci-v7.3-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci: (124 commits)
  PCI: vmd: Add Nova Lake (NVL) and Dunlow (DNL) Device IDs
  PCI: tegra264: Add Tegra264 support
  dt-bindings: PCI: tegra264: Switch to PCIe Root Port bindings
  dt-bindings: PCI: tegra264: Strictly distinguish C0 from C1-C5
  PCI/AER: Support Advisory Non-Fatal Errors
  PCI: Fix 32-bit config write in Intel PCH Root Port MPC ACS quirk
  PCI: dwc: Handle return value from endpoint .pre_init callback
  PCI: dwc: Handle return value from endpoint .init callback
  PCI: dwc: Add PCI ID for LECARC PCIe PMU
  PCI/ASPM: Mask ASPM states based on Devicetree properties
  PCI/ASPM: Disable/restore ASPM on every function for multi-function devices
  Documentation: PCI: Document how to write PCI Host Controller drivers
  PCI/ASPM: Use pcie_capability_clear_and_set_word() for ASPM disable/restore
  PCI: Add support for PCIe WAKE# interrupt
  PCI: Allow D3 for native hotplug-capable Root Ports on non-x86 platforms
  dt-bindings: PCI: Correct white-space style
  PCI/ASPM: Avoid L0s for Realtek RTS525A
  PCI: ultrarisc: Use module_platform_driver()
  PCI: ultrarisc: Get and enable DP1000 PCIe controller clocks
  dt-bindings: PCI: ultrarisc: Add required DP1000 PCIe clocks
  ...
Commit
570f7e331f5febb30f1384817463c7e42b65ca7d
Parents
b6b019a1 · 9324becc

Merge commit. Changes below are compared with the first parent: b6b019a1.

Changes

110 files changed · +4181 −993

FileStatusAddDelContent
Documentation/ABI/testing/debugfs-cdns-pcieadded+5−0View file
Documentation/ABI/testing/sysfs-bus-pcimodified+1−1View file
Documentation/PCI/controller/index.rstmodified+1−0View file
Documentation/PCI/controller/pci-controller-drivers.rstadded+402−0View file
Documentation/arch/arm64/silicon-errata.rstmodified+1−0View file
Documentation/devicetree/bindings/pci/brcm,stb-pcie.yamlmodified+1−1View file
Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yamlmodified+25−0View file
Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yamlmodified+6−0View file
Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yamlmodified+79−30View file
Documentation/devicetree/bindings/pci/qcom,hawi-pcie.yamladded+201−0View file
Documentation/devicetree/bindings/pci/qcom,pcie-ipq9574.yamlmodified+15−0View file
Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yamlmodified+3−0View file
Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yamlmodified+1−1View file
Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yamlmodified+31−3View file
Documentation/devicetree/bindings/pci/ti,am65-pci-ep.yamlmodified+4−4View file
Documentation/devicetree/bindings/pci/ti,am65-pci-host.yamlmodified+6−6View file
Documentation/devicetree/bindings/pci/toshiba,tc9563.yamlmodified+18−3View file
Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yamlmodified+16−0View file
MAINTAINERSmodified+4−2View file
arch/alpha/kernel/pci-sysfs.cmodified+16−16View file
arch/arm64/Kconfigmodified+9−0View file
arch/powerpc/kernel/pci-common.cmodified+2−7View file
drivers/ata/ata_generic.cmodified+3−3View file
drivers/char/agp/amd-k7-agp.cmodified+4−22View file
drivers/char/agp/via-agp.cmodified+72−236View file
drivers/dma/switchtec_dma.cmodified+1−0View file
drivers/ipack/carriers/tpci200.cmodified+0−1View file
drivers/ipack/carriers/tpci200.hmodified+0−1View file
drivers/irqchip/irq-gic-v3-its.cmodified+17−7View file
drivers/misc/pci_endpoint_test.cmodified+31−7View file
drivers/net/ethernet/mellanox/mlxsw/pci.cmodified+4−7View file
drivers/pci/controller/Kconfigmodified+10−2View file
drivers/pci/controller/Makefilemodified+1−0View file
drivers/pci/controller/cadence/Kconfigmodified+11−2View file
drivers/pci/controller/cadence/Makefilemodified+1−0View file
drivers/pci/controller/cadence/pci-j721e.cmodified+2−2View file
drivers/pci/controller/cadence/pci-sky1.cmodified+5−0View file
drivers/pci/controller/cadence/pcie-cadence-debugfs.cadded+263−0View file
drivers/pci/controller/cadence/pcie-cadence-ep.cmodified+3−0View file
drivers/pci/controller/cadence/pcie-cadence-host-common.cmodified+4−2View file
drivers/pci/controller/cadence/pcie-cadence-host-hpa.cmodified+20−1View file
drivers/pci/controller/cadence/pcie-cadence-host.cmodified+8−1View file
drivers/pci/controller/cadence/pcie-cadence-lga-regs.hmodified+0−5View file
drivers/pci/controller/cadence/pcie-cadence-plat.cmodified+1−0View file
drivers/pci/controller/cadence/pcie-cadence.hmodified+198−0View file
drivers/pci/controller/dwc/Kconfigmodified+5−2View file
drivers/pci/controller/dwc/pci-dra7xx.cmodified+3−1View file
drivers/pci/controller/dwc/pci-imx6.cmodified+47−25View file
drivers/pci/controller/dwc/pci-keystone.cmodified+8−2View file
drivers/pci/controller/dwc/pci-layerscape-ep.cmodified+4−2View file
drivers/pci/controller/dwc/pci-meson.cmodified+2−2View file
drivers/pci/controller/dwc/pcie-artpec6.cmodified+3−1View file
drivers/pci/controller/dwc/pcie-designware-ep.cmodified+29−4View file
drivers/pci/controller/dwc/pcie-designware-host.cmodified+6−4View file
drivers/pci/controller/dwc/pcie-designware.cmodified+9−19View file
drivers/pci/controller/dwc/pcie-designware.hmodified+3−2View file
drivers/pci/controller/dwc/pcie-dw-rockchip.cmodified+134−4View file
drivers/pci/controller/dwc/pcie-keembay.cmodified+3−1View file
drivers/pci/controller/dwc/pcie-qcom.cmodified+188−6View file
drivers/pci/controller/dwc/pcie-rcar-gen4.cmodified+117−7View file
drivers/pci/controller/dwc/pcie-spacemit-k1.cmodified+1−0View file
drivers/pci/controller/dwc/pcie-tegra194.cmodified+8−8View file
drivers/pci/controller/dwc/pcie-ultrarisc.cmodified+79−8View file
drivers/pci/controller/mobiveil/pcie-mobiveil.cmodified+2−2View file
drivers/pci/controller/mobiveil/pcie-mobiveil.hmodified+0−5View file
drivers/pci/controller/pci-aardvark.cmodified+3−6View file
drivers/pci/controller/pci-host-common.cmodified+40−24View file
drivers/pci/controller/pci-host-common.hmodified+1−0View file
drivers/pci/controller/pci-host-generic.cmodified+1−10View file
drivers/pci/controller/pci-tegra.cmodified+1−2View file
drivers/pci/controller/pci-xgene.cmodified+1−4View file
drivers/pci/controller/pcie-aspeed.cmodified+4−4View file
drivers/pci/controller/pcie-mediatek.cmodified+154−0View file
drivers/pci/controller/pcie-rockchip.cmodified+2−2View file
drivers/pci/controller/pcie-rzg3s-host.cmodified+216−17View file
drivers/pci/controller/pcie-tegra264.cadded+467−0View file
drivers/pci/controller/pcie-xilinx-nwl.cmodified+2−7View file
drivers/pci/controller/plda/pcie-plda-host.cmodified+42−10View file
drivers/pci/controller/plda/pcie-starfive.cmodified+20−12View file
drivers/pci/controller/vmd.cmodified+168−35View file
drivers/pci/doe.cmodified+2−2View file
drivers/pci/ecam.cmodified+13−0View file
drivers/pci/hotplug/acpiphp_ibm.cmodified+1−2View file
drivers/pci/of.cmodified+79−0View file
drivers/pci/p2pdma.cmodified+5−0View file
drivers/pci/pci-acpi.cmodified+2−2View file
drivers/pci/pci-driver.cmodified+109−85View file
drivers/pci/pci-sysfs.cmodified+111−66View file
drivers/pci/pci.cmodified+29−4View file
drivers/pci/pci.hmodified+60−12View file
drivers/pci/pcie/aer.cmodified+216−59View file
drivers/pci/pcie/aspm.cmodified+102−47View file
drivers/pci/pcie/bwctrl.cmodified+0−22View file
drivers/pci/pcie/err.cmodified+1−5View file
drivers/pci/pcie/portdrv.cmodified+15−15View file
drivers/pci/probe.cmodified+2−0View file
drivers/pci/proc.cmodified+15−1View file
drivers/pci/pwrctrl/pci-pwrctrl-tc9563.cmodified+97−47View file
drivers/pci/quirks.cmodified+9−1View file
drivers/pci/remove.cmodified+1−0View file
drivers/pci/search.cmodified+5−3View file
drivers/pci/setup-bus.cmodified+1−1View file
drivers/pci/switch/switchtec.cmodified+1−0View file
drivers/scsi/nsp32.cmodified+4−4View file
drivers/scsi/nsp32.hmodified+4−4View file
include/linux/of_pci.hmodified+6−0View file
include/linux/pci-ecam.hmodified+3−0View file
include/linux/pci.hmodified+4−0View file
include/linux/pci_ids.hmodified+1−0View file
include/linux/pcie-dwc.hmodified+4−0View file

Only the first 600 diff lines are shown. Download the complete patch.

Documentation/ABI/testing/debugfs-cdns-pcie

View file
diff --git a/Documentation/ABI/testing/debugfs-cdns-pcie b/Documentation/ABI/testing/debugfs-cdns-pcie
new file mode 100644
index 0000000..be96378
--- /dev/null
+++ b/Documentation/ABI/testing/debugfs-cdns-pcie
@@ -0,0 +1,5 @@
+What: /sys/kernel/debug/cdns_pcie_<dev>/ltssm_status
+Date: July 2026
+Contact: Hans Zhang <[email protected]>
+Description: (RO) Read will return the current PCIe LTSSM state in both
+ string and raw value.
\ No newline at end of file

Documentation/ABI/testing/sysfs-bus-pci

View file
diff --git a/Documentation/ABI/testing/sysfs-bus-pci b/Documentation/ABI/testing/sysfs-bus-pci
index b767db2..55ea1db 100644
--- a/Documentation/ABI/testing/sysfs-bus-pci
+++ b/Documentation/ABI/testing/sysfs-bus-pci
@@ -171,7 +171,7 @@ Description:
all devices attached through the subordinate bus of a specific
bridge device, writing 1 to this will try to do it. This will
affect all devices attached to the system through this bridge
- similiar to writing 1 to their individual "reset" file, so use
+ similar to writing 1 to their individual "reset" file, so use
with caution.
What: /sys/bus/pci/devices/.../vpd

Documentation/PCI/controller/index.rst

View file
diff --git a/Documentation/PCI/controller/index.rst b/Documentation/PCI/controller/index.rst
index c2ce9cc..c15e2c9 100644
--- a/Documentation/PCI/controller/index.rst
+++ b/Documentation/PCI/controller/index.rst
@@ -7,4 +7,5 @@ PCI Native Host Bridge and Endpoint Drivers
.. toctree::
:maxdepth: 2
+ pci-controller-drivers
rcar-pcie-firmware

Documentation/PCI/controller/pci-controller-drivers.rst

View file
diff --git a/Documentation/PCI/controller/pci-controller-drivers.rst b/Documentation/PCI/controller/pci-controller-drivers.rst
new file mode 100644
index 0000000..749a8bf
--- /dev/null
+++ b/Documentation/PCI/controller/pci-controller-drivers.rst
@@ -0,0 +1,402 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+===================================
+Writing PCI Host Controller Drivers
+===================================
+
+:Author: Manivannan Sadhasivam <[email protected]>
+
+Introduction
+============
+
+A PCI Host Controller driver controls PCI Root Complex (RC) hardware. The
+Root Complex hardware comprises a single PCI Host Bridge and one or more
+Root Port or Root Complex Integrated Endpoint (RCiEP) devices::
+
+ +------------------+
+ | CPU |
+ +------------------+
+ |
+ +--------------------------------------------+
+ | | Root |
+ | +------------------+ Complex |
+ | | Host Bridge | |
+ | +------------------+ |
+ | | |
+ | Bus 0 | |
+ | +------------|----------+ |
+ | | | | |
+ | +----------+ +----------+ +-------+ |
+ | | Root | | Root | | RCiEP | |
+ | | Port | | Port | +-------+ |
+ | +----------+ +----------+ |
+ | | | |
+ | Bus 1 | Bus 2 | |
+ | | | |
+ +-------|-------------|----------------------+
+ | |
+ +-----------+ +-----------+
+ | Endpoint | | Endpoint |
+ +-----------+ +-----------+
+
+Host Bridge: Used to connect CPU(s) to the PCI hierarchy.
+
+Root Port: Virtual PCI-PCI bridge connecting the Host Bridge to a PCI bus.
+
+RCiEP: Embedded PCIe Endpoint inside Root Complex connected to the Host
+Bridge.
+
+Endpoint: PCIe device connected to a Root Port through a Link.
+
+Enumeration
+===========
+
+The Host Bridge device is not discoverable, so it is typically enumerated
+with the help of firmware interfaces like ACPI or Devicetree. But the Root
+Port and RCiEP devices are discoverable through the standard enumeration
+process defined in the PCIe spec.
+
+A Host Controller driver usually configures both Host Bridge and Root
+Port(s) based on platform requirements. In the case of ACPI on standardized
+platforms (e.g. x86), no platform-specific host controller driver is
+required as the firmware configures the Root Complex before OS boot and
+exposes the resource information through ACPI tables. For more info, refer
+to :doc:`../acpi-info`.
+
+For Devicetree platforms, a dedicated host controller driver is often
+required because the Root Complex hardware typically needs vendor-specific
+initialization like PHY, clocks, power domains, and there is no standard
+mechanism equivalent to ACPI/MCFG to convey resource information to the OS.
+So on these platforms, Root Complex hardware is enumerated through
+Devicetree nodes as below::
+
+ pcie@10000000 {
+ compatible = "vendor,soc-pcie";
+ reg = <0x0 0x10000000 0x0 0x1000>,
+ <0x0 0x10001000 0x0 0x1000>;
+ reg-names = "cfg", "app";
+ device_type = "pci";
+ bus-range = <0x00 0xff>;
+ linux,pci-domain = <0>;
+ num-lanes = <4>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ ranges = <0x01000000 0x0 0x00000000 0x0 0x20000000 0x0 0x00100000>,
+ <0x02000000 0x0 0x20100000 0x0 0x20100000 0x0 0x1ff00000>;
+ dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
+
+ clocks = <&clkc PCIE_CORE_CLK>,
+ <&clkc PCIE_AUX_CLK>;
+ clock-names = "core", "aux";
+ resets = <&reset PCIE_RESET>;
+ power-domains = <&power PCIE_PD>;
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &gic 0 0 GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &gic 0 0 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &gic 0 0 GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+
+ pcie@0 {
+ compatible = "pciclass,0604";
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ phys = <&pcie_phy>;
+ reset-gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+
+Note the presence of two nodes in the above example. The ``pcie@10000000``
+node represents a PCI Host Bridge device, and ``pcie@0`` represents a
+single Root Port device. The Host Bridge node should contain properties
+associated with the Host Bridge device such as ranges, interrupts, clocks,
+power-domains etc... and the Root Port node should contain port-specific
+properties such as phys, reset-gpios, wake-gpios etc...
+
+NOTE: Legacy Devicetrees used a single node to describe both Host Bridge
+and Root Port devices, but that design is now deprecated.
+
+Driver Design
+=============
+
+Prerequisites
+-------------
+
+Before starting to write a new Host Controller driver, check if any of the
+existing drivers can be reused. For example, if the Root Complex supports
+the Enhanced Configuration Access Mechanism (ECAM) and the bootloader has
+configured the ECAM mapping before OS boot, the ``CONFIG_PCI_HOST_GENERIC``
+driver can be used.
+
+If the Root Complex hardware (IP) is from IP vendors such as Synopsys or
+Cadence, the existing ``CONFIG_PCIE_DW_PLAT_HOST`` and
+``CONFIG_PCIE_CADENCE_PLAT_HOST`` drivers can be reused. If not, then check
+if any of the existing glue drivers available for these IPs could be
+reused.
+
+If the Root Complex hardware is designed in-house by the SoC vendor, check
+if there is an existing driver from the vendor for their previous
+generation Root Complex hardware. Often, the existing driver can be
+reused with minimal modifications.
+
+Only if the Root Complex doesn't satisfy above prerequisites should a new
+Host Controller driver be written.
+
+Probe
+-----
+
+During the Host Controller driver probe(), it initializes the Root Complex
+hardware and registers the Host Bridge with the PCI core. The typical steps
+are described below.
+
+Initialize Resources
+~~~~~~~~~~~~~~~~~~~~
+
+At the start of the probe(), initialize Host Bridge-specific resources such
+as clocks, PHYs, regulators, and resets. These resources are described in
+the Host Bridge Devicetree node and should be brought up before accessing
+the controller hardware.
+
+NOTE: Use the devm_*() managed APIs wherever possible so the resources are
+released automatically on probe failure and on driver detach.
+
+Configuration Space Access
+~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The PCI core accesses the Configuration Space of the enumerated devices
+through the callbacks provided by the driver in struct pci_ops. These
+callbacks abstract how the Root Complex generates a Configuration Request
+for a given Bus, Device and Function number.
+
+If the Root Complex supports ECAM, the generic accessors can be reused by
+using pci_ecam_map_bus() along with pci_generic_config_read() and
+pci_generic_config_write(). Such drivers can often be built on top of
+pci_host_common_probe() without providing any custom accessors.
+
+Setup Address Translation
+~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The Host Bridge translates accesses between the CPU address domain and the
+PCI address domain in both directions:
+
+- Outbound: CPU addresses are translated to PCI bus addresses for the
+ Memory and I/O accesses initiated by the CPU towards the downstream
+ devices. These windows are derived from the ``ranges`` property of the
+ Host Bridge Devicetree node.
+
+- Inbound: PCI bus addresses are translated to system memory addresses for
+ the accesses (such as DMA) initiated by the downstream devices. These
+ windows are derived from the ``dma-ranges`` property.
+
+The PCI core parses ``ranges`` and ``dma-ranges`` into the Host Bridge
+resource lists, and the driver programs one translation window per entry.
+Note that the CPU address and the PCI bus address of a window may differ,
+so the offset between them has to be accounted for while programming the
+windows.
+
+NOTE: If the hardware supports ECAM, it is strongly recommended to use ECAM
+for the Configuration Space so a translation window need not be
+reprogrammed for every Configuration access.
+
+Interrupt Handling
+~~~~~~~~~~~~~~~~~~
+
+Downstream devices can signal interrupts either through INTx or through
+Message Signaled Interrupts (MSI/MSI-X). The driver has to enable the
+mechanisms supported by the Root Complex.
+
+INTx interrupts are conveyed to the Root Complex through the Assert_INTx
+and Deassert_INTx messages and are then reported as system interrupts. The
+driver typically creates an IRQ domain for the four interrupts (INTA to
+INTD) and demultiplexes an incoming interrupt to the corresponding virtual
+IRQ.
+
+An MSI/MSI-X is signaled by the downstream device as a Memory Write to a
+Root Complex-specific address. There are two ways to handle them:
+
+- If the Root Complex integrates its own MSI controller, the driver has to
+ create an MSI IRQ domain, program the MSI target address and demultiplex
+ the incoming MSIs to the corresponding virtual IRQs. MSI-X is handled
+ through the same domain.
+
+- If the MSIs are handled by an external interrupt controller (such as the
+ GIC ITS), the Root Complex Devicetree node needs to have an
+ ``msi-parent`` property and the driver need not implement an MSI
+ controller.
+
+
+Powering up the Slot/Endpoint
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Power ON any slots or Endpoints connected to the bus with the help of the
+PWRCTRL subsystem APIs such as pci_pwrctrl_create_devices() and
+pci_pwrctrl_power_on_devices(). Note that this requires defining the
+supplies in the Root Port or Endpoint Devicetree node.
+
+Link Training
+~~~~~~~~~~~~~
+
+Once the resources are initialized, the driver has to initiate Link
+training by enabling the LTSSM (Link Training and Status State Machine) of
+the Root Port. If a PERST# signal is present, it should be deasserted to
+bring the downstream device out of fundamental reset before enabling the
+LTSSM.
+
+Before PERST# is deasserted, the driver must satisfy the power sequencing
+delays defined by the PCI Express Card Electromechanical (CEM)
+Specification. The power supplies must be stable for at least T_PVPERL
+(``PCIE_T_PVPERL_MS``, 100 ms) and the reference clock must be stable for
+at least T_PERST-CLK (``PCIE_T_PERST_CLK_US``, 100 us) before PERST# is
+deasserted.
+
+After the LTSSM is enabled, the driver should wait (with a timeout) for the
+LTSSM to reach the L0 state, indicating that the Link is up.
+
+Once the Link is up, the PCI Express Base Specification (Conventional
+Reset) requires software to wait for at least ``PCIE_RESET_CONFIG_WAIT_MS``
+(100 ms) before sending the first Configuration Request to the downstream
+device. For a Link operating up to 5.0 GT/s, this delay is counted from the
+exit of the Conventional Reset (PERST# deassertion), while for a Link
+operating above 5.0 GT/s it is counted from the completion of Link
+training. The driver should honor this delay before the bus is scanned.
+
+NOTE: A failure to establish the Link should NOT be treated as a probe
+failure unless the Root Port is not Hotplug capable. If the Root Port is
+Hotplug capable, then the driver should still register the Host Bridge and
+scan the bus, so that the downstream device can be discovered later when
+the Link comes up.
+
+Register the Host Bridge
+~~~~~~~~~~~~~~~~~~~~~~~~
+
+Finally, allocate the Host Bridge device with devm_pci_alloc_host_bridge(),
+assign the Configuration Space accessors (struct pci_ops) to it, and start
+the bus scan by calling pci_host_probe(). This is the last step of the
+probe(). pci_host_probe() creates the Root bus for the Host Bridge and
+scans/enumerates all the Root Port, RCiEP and Endpoint devices connected to
+the bus.
+
+If the Root Complex IP is from a known IP vendor, the IP specific helpers
+should be reused for the above operations wherever applicable.
+
+Power Management
+----------------
+
+A Host Controller driver participates in both runtime and system-wide power
+management. In both cases, the driver is responsible for the power state of
+the Root Complex hardware, while the PCI core manages the power state of
+the enumerated devices.
+
+Runtime PM
+~~~~~~~~~~
+
+Runtime PM allows the Root Complex hardware to be powered down when it is
+idle. The driver typically enables runtime PM with pm_runtime_enable() and
+takes a reference with pm_runtime_get_sync() during probe(), so that the
+controller stays powered while it is in use. The reference is dropped in
+remove().
+
+If the Root Complex can be powered down when idle, the driver implements
+the runtime_suspend and runtime_resume callbacks to disable and enable the
+controller resources such as the clocks, PHYs, and power domain. These
+callbacks should manage only the controller resources and must not touch
+the state of the enumerated devices, which is handled by the PCI core.
+
+System PM
+~~~~~~~~~
+
+During system suspend and resume, the driver has to save and restore the
+state of the Root Complex and put the Link into a low power state.
+
+These operations are performed in the _noirq() PM callbacks (for example,
+using NOIRQ_SYSTEM_SLEEP_PM_OPS()), because the controller resources such
+as the clocks and PHY are shared by all the child devices. Suspending them
+earlier would break the child devices whose own suspend callbacks may still
+access their Configuration Space.
+
+In the suspend callback, the driver should:
+
+- Broadcast a PME_Turn_Off message and wait for the PME_TO_Ack, so that the
+ Link can transition to the L2/L3 state.
+- Stop the LTSSM and disable the controller resources such as the clocks,
+ PHY and power domain.
+- Save any controller state that is not retained across the low power
+ state.
+- Power off the downstream devices using pci_pwrctrl_power_off_devices().
+
+In the resume callback, the driver should reverse the above by enabling the
+controller resources, restoring the saved state, re-initializing the Root
+Complex and re-establishing the Link as done during probe().
+
+NOTE: If the Link is in the ASPM L1 (or L1 substates) state, some drivers
+keep the Link in L1 across suspend for a faster resume, instead of
+transitioning it to L2/L3. This is a driver policy decision based on the
+platform and the devices connected.
+
+Shutdown
+--------
+
+The shutdown() callback is invoked during system reboot or when
+transitioning to a new kernel through kexec. Its purpose is to quiesce the
+Root Complex so that the downstream devices cannot corrupt the memory or
+interrupt the new kernel.
+
+The driver should:
+
+- Disable the interrupts (INTx and MSI) reported by the Root Complex so
+ that no spurious interrupt is delivered to the new kernel.
+- Broadcast a PME_Turn_Off message and stop the LTSSM to bring the Link
+ down so that any in-flight DMA from the downstream devices is stopped
+ before the reset.
+- Power down the controller resources.
+
+Unlike remove(), shutdown() does not need to tear down the software state
+such as the Root bus, since the system is going down anyway.
+
+NOTE: shutdown() is optional. It is mainly required on platforms where the
+downstream devices could perform DMA or raise interrupts during the
+transition to reboot or kexec.
+
+Remove
+------
+
+remove() is called when the driver is detached, and it should undo
+everything done in probe() in the reverse order.
+
+The first step is to remove the enumerated devices and the Root bus, by
+calling pci_stop_root_bus() followed by pci_remove_root_bus() under the
+pci_lock_rescan_remove() lock. This detaches all the child devices before
+the controller resources are released.
+
+After the bus is removed, the driver should:
+
+- Disable the interrupts reported by the Root Complex.
+- Stop the LTSSM to bring the Link down.
+- Power down the PHY and disable the clocks, regulators and resets.
+- Drop the runtime PM reference with pm_runtime_put_sync() and disable
+ runtime PM with pm_runtime_disable().
+
+Resources allocated through the devm_*() APIs are released automatically
+after remove() returns and need not be freed explicitly.
+
+NOTE: A Host Controller driver is encouraged to be built as a loadable
+module, but it should not be removed at runtime if it implements its own
+IRQ domains such as MSI or INTx controllers. The IRQ mappings created for
+such domains can persist even after the interrupts are released and cannot
+be disposed of safely, so tearing down the IRQ domains on removal is
+fragile. Such drivers should therefore prevent their removal. See the
+following thread for more details:
+https://lore.kernel.org/linux-pci/[email protected]/

Documentation/arch/arm64/silicon-errata.rst

View file
diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/arch/arm64/silicon-errata.rst
index 61ceb4e..ac3248b 100644
--- a/Documentation/arch/arm64/silicon-errata.rst
+++ b/Documentation/arch/arm64/silicon-errata.rst
@@ -364,6 +364,7 @@ stable kernels.
+----------------+-----------------+-----------------+-----------------------------+
| Qualcomm Tech. | Kryo4xx Gold | N/A | ARM64_ERRATUM_1286807 |
+----------------+-----------------+-----------------+-----------------------------+
+| Renesas | S4/V4H/V4M | N/A | RENESAS_ERRATUM_GEN4GICITS1 |
+----------------+-----------------+-----------------+-----------------------------+
| Rockchip | RK3588 | #3588001 | ROCKCHIP_ERRATUM_3588001 |
+----------------+-----------------+-----------------+-----------------------------+

Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml

View file
diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
index 812ef59..328b815 100644
--- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
@@ -214,7 +214,7 @@ examples:
dma-ranges = <0x42000000 0x1 0x00000000 0x0 0x40000000 0x0 0x80000000>,
<0x42000000 0x1 0x80000000 0x3 0x00000000 0x0 0x80000000>;
brcm,enable-ssc;
- brcm,scb-sizes = <0x0000000080000000 0x0000000080000000>;
+ brcm,scb-sizes = <0x0000000080000000 0x0000000080000000>;
/* PCIe bridge, Root Port */
pci@0,0 {

Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml

View file
diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
index e8b8131..4f56e8e 100644
--- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
@@ -58,12 +58,18 @@ properties:
items:
- description: builtin MSI controller.
- description: builtin DMA controller.
+ - description: PCIe event interrupt.
+ - description: builtin AER SPI standalone interrupt line.
+ - description: builtin PME SPI standalone interrupt line.
interrupt-names:
minItems: 1
items:
- const: msi
- const: dma
+ - const: intr
+ - const: aer
+ - const: pme
reset-gpio:
deprecated: true
@@ -249,6 +255,25 @@ allOf:
- const: ref
- const: extref # Optional
+ - if:
+ properties:
+ compatible:
+ enum:
+ - fsl,imx6q-pcie
+ - fsl,imx6sx-pcie
+ - fsl,imx6qp-pcie
+ - fsl,imx7d-pcie
+ - fsl,imx8mm-pcie
+ - fsl,imx8mp-pcie
+ - fsl,imx8mq-pcie
+ - fsl,imx8q-pcie
+ then:
+ properties:
+ interrupts:
+ maxItems: 2
+ interrupt-names:
+ maxItems: 2
+
unevaluatedProperties: false
examples:

Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml

View file
diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
index 4db700f..b88717d 100644
--- a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
+++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
@@ -51,6 +51,7 @@ properties:
- mediatek,mt7981-pcie
- mediatek,mt7986-pcie
- mediatek,mt8188-pcie
+ - mediatek,mt8189-pcie
- mediatek,mt8195-pcie
- const: mediatek,mt8192-pcie
- items:
@@ -115,6 +116,10 @@ properties:
power-domains:
maxItems: 1
+ memory-region:
+ maxItems: 1
+ description: phandle to restricted DMA buffer
+
mediatek,pbus-csr:
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
@@ -193,6 +198,7 @@ allOf:
contains:
enum:
- mediatek,mt8188-pcie
+ - mediatek,mt8189-pcie
- mediatek,mt8195-pcie
then:
properties:

Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml

View file
diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml b/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml
index dc4f872..f0114de 100644
--- a/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml
@@ -10,32 +10,23 @@ maintainers:
- Thierry Reding <[email protected]>
- Jon Hunter <[email protected]>
+description: |
+ Of the six PCIe controllers found on Tegra264, one (C0) is used for the
+ internal GPU and the other five (C1-C5) are routed to connectors such as
+ PCI or M.2 slots. Therefore the UPHY registers (XPL) exist only for C1
+ through C5, but not for C0.
+
properties:
compatible:
const: nvidia,tegra264-pcie
reg:
- description: |
- Of the six PCIe controllers found on Tegra264, one (C0) is used for the
- internal GPU and the other five (C1-C5) are routed to connectors such as
- PCI or M.2 slots. Therefore the UPHY registers (XPL) exist only for C1
- through C5, but not for C0.
minItems: 4
- items:
- - description: ECAM-compatible configuration space
- - description: application layer registers
- - description: transaction layer registers
- - description: privileged transaction layer registers
- - description: data link/physical layer registers (not available on C0)
+ maxItems: 5
reg-names:
minItems: 4
- items:
- - const: ecam
- - const: xal
- - const: xtl
- - const: xtl-pri
- - const: xpl
+ maxItems: 5
interrupts:
minItems: 1
@@ -61,6 +52,49 @@ properties:
- description: PCIe controller ID
maximum: 5
+patternProperties:
+ '^pcie@':
+ type: object

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drivers/pci/controller/dwc/pcie-ultrarisc.c

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drivers/pci/controller/mobiveil/pcie-mobiveil.c

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drivers/pci/controller/mobiveil/pcie-mobiveil.h

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drivers/pci/controller/pci-aardvark.c

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drivers/pci/controller/pci-host-common.c

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drivers/pci/controller/pci-host-common.h

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drivers/pci/controller/pci-host-generic.c

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drivers/pci/controller/pci-tegra.c

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drivers/pci/controller/pci-xgene.c

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drivers/pci/controller/pcie-aspeed.c

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drivers/pci/controller/pcie-mediatek.c

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drivers/pci/controller/pcie-rockchip.c

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drivers/pci/controller/pcie-rzg3s-host.c

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drivers/pci/controller/pcie-tegra264.c

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drivers/pci/controller/pcie-xilinx-nwl.c

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drivers/pci/controller/plda/pcie-plda-host.c

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drivers/pci/controller/plda/pcie-starfive.c

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drivers/pci/controller/vmd.c

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drivers/pci/doe.c

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drivers/pci/ecam.c

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drivers/pci/hotplug/acpiphp_ibm.c

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drivers/pci/of.c

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drivers/pci/p2pdma.c

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drivers/pci/pci-acpi.c

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drivers/pci/pci-driver.c

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drivers/pci/pci-sysfs.c

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drivers/pci/pci.c

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drivers/pci/pci.h

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drivers/pci/pcie/aer.c

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drivers/pci/pcie/aspm.c

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drivers/pci/pcie/bwctrl.c

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drivers/pci/pcie/err.c

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drivers/pci/pcie/portdrv.c

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drivers/pci/probe.c

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drivers/pci/proc.c

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drivers/pci/pwrctrl/pci-pwrctrl-tc9563.c

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drivers/pci/quirks.c

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drivers/pci/remove.c

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drivers/pci/search.c

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drivers/pci/setup-bus.c

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drivers/pci/switch/switchtec.c

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drivers/scsi/nsp32.c

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drivers/scsi/nsp32.h

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include/linux/of_pci.h

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include/linux/pci-ecam.h

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include/linux/pci.h

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include/linux/pci_ids.h

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include/linux/pcie-dwc.h

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