Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

5d8a00ee · Linus Torvalds <[email protected]> · 2017-02-25 14:28:06 -08:00

Pull clk updates from Stephen Boyd:
 "The usual collection of new drivers, non-critical fixes, and updates
  to existing clk drivers. The bulk of the work is on Allwinner and
  Rockchip SoCs, but there's also an Intel Atom driver in here too.

  New Drivers:
   - Tegra BPMP firmware
   - Hisilicon hi3660 SoCs
   - Rockchip rk3328 SoCs
   - Intel Atom PMC
   - STM32F746
   - IDT VersaClock 5P49V5923 and 5P49V5933
   - Marvell mv98dx3236 SoCs
   - Allwinner V3s SoCs

  Removed Drivers:
   - Samsung Exynos4415 SoCs

  Updates:
   - Migrate ABx500 to OF
   - Qualcomm IPQ4019 CPU clks and general PLL support
   - Qualcomm MSM8974 RPM
   - Rockchip non-critical fixes and clk id additions
   - Samsung Exynos4412 CPUs
   - Socionext UniPhier NAND and eMMC support
   - ZTE zx296718 i2s and other audio clks
   - Renesas CAN and MSIOF clks for R-Car M3-W
   - Renesas resets for R-Car Gen2 and Gen3 and RZ/G1
   - TI CDCE913, CDCE937, and CDCE949 clk generators
   - Marvell Armada ap806 CPU frequencies
   - STM32F4* I2S/SAI support
   - Broadcom BCM2835 DSI support
   - Allwinner sun5i and A80 conversion to new style clk bindings"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (130 commits)
  clk: renesas: mstp: ensure register writes complete
  clk: qcom: Do not drop device node twice
  clk: mvebu: adjust clock handling for the CP110 system controller
  clk: mvebu: Expand mv98dx3236-core-clock support
  clk: zte: add i2s clocks for zx296718
  clk: sunxi-ng: sun9i-a80: Fix wrong pointer passed to PTR_ERR()
  clk: sunxi-ng: select SUNXI_CCU_MULT for sun5i
  clk: sunxi-ng: Check kzalloc() for errors and cleanup error path
  clk: tegra: Add BPMP clock driver
  clk: uniphier: add eMMC clock for LD11 and LD20 SoCs
  clk: uniphier: add NAND clock for all UniPhier SoCs
  ARM: dts: sun9i: Switch to new clock bindings
  clk: sunxi-ng: Add A80 Display Engine CCU
  clk: sunxi-ng: Add A80 USB CCU
  clk: sunxi-ng: Add A80 CCU
  clk: sunxi-ng: Support separately grouped PLL lock status register
  clk: sunxi-ng: mux: Get closest parent rate possible with CLK_SET_RATE_PARENT
  clk: sunxi-ng: mux: honor CLK_SET_RATE_NO_REPARENT flag
  clk: sunxi-ng: mux: Fix determine_rate for mux clocks with pre-dividers
  clk: qcom: SDHCI enablement on Nexus 5X / 6P
  ...

Commit: 5d8a00eee2ed2e548a5d21b0edf495f3f7bf8bb4
Parents: 7067739d · f59de563

Merge commit. Changes below are compared with the first parent: 7067739d.

Changes

156 files changed · +12306 −3072

File	Status	Add	Del	Content
Documentation/devicetree/bindings/clock/brcm,bcm2835-cprman.txt	modified	+14	−1	View file
Documentation/devicetree/bindings/clock/exynos4415-clock.txt	deleted	+0	−38	View before deletion
Documentation/devicetree/bindings/clock/hi3660-clock.txt	added	+42	−0	View file
Documentation/devicetree/bindings/clock/idt,versaclock5.txt	added	+65	−0	View file
Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt	modified	+1	−0	View file
Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt	modified	+1	−0	View file
Documentation/devicetree/bindings/clock/qcom,rpmcc.txt	modified	+1	−0	View file
Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt	modified	+6	−0	View file
Documentation/devicetree/bindings/clock/rockchip,rk3328-cru.txt	added	+57	−0	View file
Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt	modified	+6	−0	View file
Documentation/devicetree/bindings/clock/st,stm32-rcc.txt	modified	+20	−0	View file
Documentation/devicetree/bindings/clock/stericsson,abx500.txt	added	+20	−0	View file
Documentation/devicetree/bindings/clock/sun9i-de.txt	added	+28	−0	View file
Documentation/devicetree/bindings/clock/sun9i-usb.txt	added	+24	−0	View file
Documentation/devicetree/bindings/clock/sunxi-ccu.txt	modified	+2	−0	View file
Documentation/devicetree/bindings/clock/ti,cdce925.txt	modified	+11	−4	View file
Documentation/devicetree/bindings/clock/zx296718-clk.txt	modified	+3	−0	View file
MAINTAINERS	modified	+5	−0	View file
arch/arm/boot/dts/sun5i-a10s.dtsi	modified	+16	−69	View file
arch/arm/boot/dts/sun5i-a13.dtsi	modified	+18	−122	View file
arch/arm/boot/dts/sun5i-gr8.dtsi	modified	+56	−464	View file
arch/arm/boot/dts/sun5i-r8.dtsi	modified	+5	−5	View file
arch/arm/boot/dts/sun5i.dtsi	modified	+36	−317	View file
arch/arm/boot/dts/sun9i-a80.dtsi	modified	+107	−297	View file
arch/x86/Kconfig	modified	+0	−4	View file
arch/x86/platform/atom/Makefile	modified	+0	−1	View file
drivers/acpi/acpi_lpss.c	modified	+1	−1	View file
drivers/clk/Kconfig	modified	+16	−5	View file
drivers/clk/Makefile	modified	+3	−0	View file
drivers/clk/axs10x/i2s_pll_clock.c	modified	+1	−0	View file
drivers/clk/bcm/clk-bcm2835.c	modified	+254	−49	View file
drivers/clk/clk-cdce925.c	modified	+83	−25	View file
drivers/clk/clk-conf.c	modified	+9	−6	View file
drivers/clk/clk-cs2000-cp.c	modified	+22	−0	View file
drivers/clk/clk-scpi.c	modified	+8	−6	View file
drivers/clk/clk-stm32f4.c	modified	+848	−24	View file
drivers/clk/clk-versaclock5.c	added	+791	−0	View file
drivers/clk/clk-wm831x.c	modified	+2	−1	View file
drivers/clk/hisilicon/Kconfig	modified	+7	−0	View file
drivers/clk/hisilicon/Makefile	modified	+1	−0	View file
drivers/clk/hisilicon/clk-hi3660.c	added	+567	−0	View file
drivers/clk/hisilicon/clkgate-separated.c	modified	+1	−0	View file
drivers/clk/imx/clk-imx6q.c	modified	+13	−8	View file
drivers/clk/imx/clk-imx7d.c	modified	+1	−0	View file
drivers/clk/imx/clk-pllv3.c	modified	+99	−0	View file
drivers/clk/imx/clk-vf610.c	modified	+2	−2	View file
drivers/clk/imx/clk.h	modified	+1	−0	View file
drivers/clk/mediatek/Kconfig	modified	+10	−9	View file
drivers/clk/meson/meson8b.c	modified	+0	−1	View file
drivers/clk/mvebu/Makefile	modified	+1	−1	View file
drivers/clk/mvebu/ap806-system-controller.c	modified	+23	−5	View file
drivers/clk/mvebu/armada-xp.c	modified	+26	−0	View file
drivers/clk/mvebu/clk-corediv.c	modified	+23	−0	View file
drivers/clk/mvebu/clk-cpu.c	modified	+8	−0	View file
drivers/clk/mvebu/cp110-system-controller.c	modified	+11	−2	View file
drivers/clk/mvebu/mv98dx3236.c	added	+180	−0	View file
drivers/clk/qcom/clk-smd-rpm.c	modified	+71	−0	View file
drivers/clk/qcom/common.c	modified	+0	−1	View file
drivers/clk/qcom/gcc-ipq4019.c	modified	+465	−14	View file
drivers/clk/qcom/gcc-mdm9615.c	modified	+30	−0	View file
drivers/clk/qcom/gcc-msm8994.c	modified	+18	−0	View file
drivers/clk/qcom/gcc-msm8996.c	modified	+1	−0	View file
drivers/clk/qcom/gdsc.c	modified	+45	−13	View file
drivers/clk/renesas/clk-mstp.c	modified	+14	−3	View file
drivers/clk/renesas/r8a7795-cpg-mssr.c	modified	+1	−0	View file
drivers/clk/renesas/r8a7796-cpg-mssr.c	modified	+10	−0	View file
drivers/clk/renesas/renesas-cpg-mssr.c	modified	+134	−15	View file
drivers/clk/rockchip/Makefile	modified	+2	−0	View file
drivers/clk/rockchip/clk-muxgrf.c	added	+102	−0	View file
drivers/clk/rockchip/clk-pll.c	modified	+13	−3	View file
drivers/clk/rockchip/clk-rk3188.c	modified	+2	−2	View file
drivers/clk/rockchip/clk-rk3288.c	modified	+21	−15	View file
drivers/clk/rockchip/clk-rk3328.c	added	+895	−0	View file
drivers/clk/rockchip/clk-rk3399.c	modified	+1	−1	View file
drivers/clk/rockchip/clk.c	modified	+7	−1	View file
drivers/clk/rockchip/clk.h	modified	+40	−0	View file
drivers/clk/samsung/Makefile	modified	+0	−1	View file
drivers/clk/samsung/clk-exynos-audss.c	modified	+10	−14	View file
drivers/clk/samsung/clk-exynos4415.c	deleted	+0	−1022	View before deletion
drivers/clk/samsung/clk-exynos5433.c	modified	+24	−20	View file
drivers/clk/samsung/clk-pll.c	modified	+38	−7	View file
drivers/clk/samsung/clk-s3c2410.c	modified	+2	−2	View file
drivers/clk/samsung/clk-s3c2412.c	modified	+2	−2	View file
drivers/clk/samsung/clk-s3c2443.c	modified	+2	−2	View file
drivers/clk/samsung/clk-s3c64xx.c	modified	+2	−2	View file
drivers/clk/sunxi-ng/Kconfig	modified	+32	−0	View file
drivers/clk/sunxi-ng/Makefile	modified	+5	−0	View file
drivers/clk/sunxi-ng/ccu-sun5i.c	added	+1022	−0	View file
drivers/clk/sunxi-ng/ccu-sun5i.h	added	+67	−0	View file
drivers/clk/sunxi-ng/ccu-sun6i-a31.c	modified	+2	−2	View file
drivers/clk/sunxi-ng/ccu-sun8i-a33.c	modified	+13	−3	View file
drivers/clk/sunxi-ng/ccu-sun8i-h3.c	modified	+10	−0	View file
drivers/clk/sunxi-ng/ccu-sun8i-v3s.c	added	+591	−0	View file
drivers/clk/sunxi-ng/ccu-sun8i-v3s.h	added	+63	−0	View file
drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c	added	+283	−0	View file
drivers/clk/sunxi-ng/ccu-sun9i-a80-de.h	added	+33	−0	View file
drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c	added	+144	−0	View file
drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.h	added	+25	−0	View file
drivers/clk/sunxi-ng/ccu-sun9i-a80.c	added	+1223	−0	View file
drivers/clk/sunxi-ng/ccu-sun9i-a80.h	added	+57	−0	View file
drivers/clk/sunxi-ng/ccu_common.c	modified	+22	−2	View file
drivers/clk/sunxi-ng/ccu_common.h	modified	+4	−0	View file
drivers/clk/sunxi-ng/ccu_div.c	modified	+12	−0	View file
drivers/clk/sunxi-ng/ccu_div.h	modified	+9	−1	View file
drivers/clk/sunxi-ng/ccu_mp.c	modified	+7	−3	View file
drivers/clk/sunxi-ng/ccu_mult.c	modified	+24	−6	View file
drivers/clk/sunxi-ng/ccu_mult.h	modified	+18	−6	View file
drivers/clk/sunxi-ng/ccu_mux.c	modified	+38	−5	View file
drivers/clk/sunxi-ng/ccu_nk.c	modified	+14	−8	View file
drivers/clk/sunxi-ng/ccu_nkm.c	modified	+17	−9	View file
drivers/clk/sunxi-ng/ccu_nkmp.c	modified	+17	−8	View file
drivers/clk/sunxi-ng/ccu_nm.c	modified	+12	−5	View file
drivers/clk/tegra/Kconfig	modified	+4	−0	View file
drivers/clk/tegra/Makefile	modified	+1	−0	View file
drivers/clk/tegra/clk-bpmp.c	added	+620	−0	View file
drivers/clk/ti/divider.c	modified	+30	−1	View file
drivers/clk/uniphier/clk-uniphier-core.c	modified	+2	−5	View file
drivers/clk/uniphier/clk-uniphier-cpugear.c	modified	+0	−1	View file
drivers/clk/uniphier/clk-uniphier-sys.c	modified	+21	−0	View file
drivers/clk/ux500/abx500-clk.c	modified	+26	−18	View file
drivers/clk/ux500/u8500_of_clk.c	modified	+3	−0	View file
drivers/clk/x86/Makefile	modified	+1	−0	View file
drivers/clk/x86/clk-pmc-atom.c	added	+371	−0	View file
drivers/clk/zte/clk-zx296718.c	modified	+149	−9	View file
drivers/clk/zte/clk.c	modified	+127	−0	View file
drivers/clk/zte/clk.h	modified	+21	−0	View file
drivers/platform/x86/Kconfig	modified	+5	−0	View file
drivers/platform/x86/Makefile	modified	+1	−0	View file
arch/x86/platform/atom/pmc_atom.c → drivers/platform/x86/pmc_atom.c	renamed	+80	−8	View file
include/dt-bindings/clock/bcm2835.h	modified	+2	−0	View file
include/dt-bindings/clock/exynos4415.h	deleted	+0	−360	View before deletion
include/dt-bindings/clock/exynos5433.h	modified	+4	−1	View file
include/dt-bindings/clock/hi3660-clock.h	added	+194	−0	View file
include/dt-bindings/clock/imx7d-clock.h	modified	+2	−1	View file
include/dt-bindings/clock/qcom,gcc-ipq4019.h	modified	+11	−0	View file
include/dt-bindings/clock/qcom,gcc-mdm9615.h	modified	+2	−0	View file
include/dt-bindings/clock/qcom,gcc-msm8994.h	modified	+1	−0	View file
include/dt-bindings/clock/qcom,gcc-msm8996.h	modified	+1	−0	View file
include/dt-bindings/clock/qcom,rpmcc.h	modified	+38	−2	View file
include/dt-bindings/clock/rk3188-cru-common.h	modified	+2	−0	View file
include/dt-bindings/clock/rk3288-cru.h	modified	+2	−0	View file
include/dt-bindings/clock/rk3328-cru.h	added	+400	−0	View file
include/dt-bindings/clock/ste-ab8500.h	added	+11	−0	View file
include/dt-bindings/clock/stm32fx-clock.h	modified	+20	−0	View file
include/dt-bindings/clock/sun5i-ccu.h	added	+103	−0	View file
include/dt-bindings/clock/sun8i-v3s-ccu.h	added	+107	−0	View file
include/dt-bindings/clock/sun9i-a80-ccu.h	added	+162	−0	View file
include/dt-bindings/clock/sun9i-a80-de.h	added	+80	−0	View file
include/dt-bindings/clock/sun9i-a80-usb.h	added	+59	−0	View file
include/dt-bindings/reset/sun5i-ccu.h	added	+32	−0	View file
include/dt-bindings/reset/sun8i-v3s-ccu.h	added	+78	−0	View file
include/dt-bindings/reset/sun9i-a80-ccu.h	added	+102	−0	View file
include/dt-bindings/reset/sun9i-a80-de.h	added	+58	−0	View file
include/dt-bindings/reset/sun9i-a80-usb.h	added	+56	−0	View file
include/linux/platform_data/x86/clk-pmc-atom.h	added	+44	−0	View file
arch/x86/include/asm/pmc_atom.h → include/linux/platform_data/x86/pmc_atom.h	renamed	+1	−1	View file

Only the first 600 diff lines are shown. Download the complete patch.

Documentation/devicetree/bindings/clock/brcm,bcm2835-cprman.txt

View file

diff --git a/Documentation/devicetree/bindings/clock/brcm,bcm2835-cprman.txt b/Documentation/devicetree/bindings/clock/brcm,bcm2835-cprman.txt
index e56a1df..dd906db 100644
--- a/Documentation/devicetree/bindings/clock/brcm,bcm2835-cprman.txt
+++ b/Documentation/devicetree/bindings/clock/brcm,bcm2835-cprman.txt
@@ -16,7 +16,20 @@ Required properties:
 - #clock-cells:	Should be <1>. The permitted clock-specifier values can be
 		  found in include/dt-bindings/clock/bcm2835.h
 - reg:		Specifies base physical address and size of the registers
-- clocks:	The external oscillator clock phandle
+- clocks:	phandles to the parent clocks used as input to the module, in
+		  the following order:
+
+		  - External oscillator
+		  - DSI0 byte clock
+		  - DSI0 DDR2 clock
+		  - DSI0 DDR clock
+		  - DSI1 byte clock
+		  - DSI1 DDR2 clock
+		  - DSI1 DDR clock
+
+		  Only external oscillator is required.  The DSI clocks may
+		  not be present, in which case their children will be
+		  unusable.
 
 Example:
 

Documentation/devicetree/bindings/clock/exynos4415-clock.txt

View before deletion

diff --git a/Documentation/devicetree/bindings/clock/exynos4415-clock.txt b/Documentation/devicetree/bindings/clock/exynos4415-clock.txt
deleted file mode 100644
index 847d98b..0000000
--- a/Documentation/devicetree/bindings/clock/exynos4415-clock.txt
+++ /dev/null
@@ -1,38 +0,0 @@
-* Samsung Exynos4415 Clock Controller
-
-The Exynos4415 clock controller generates and supplies clock to various
-consumer devices within the Exynos4415 SoC.
-
-Required properties:
-
-- compatible: should be one of the following:
-  - "samsung,exynos4415-cmu" - for the main system clocks controller
-    (CMU_LEFTBUS, CMU_RIGHTBUS, CMU_TOP, CMU_CPU clock domains).
-  - "samsung,exynos4415-cmu-dmc" - for the Exynos4415 SoC DRAM Memory
-    Controller (DMC) domain clock controller.
-
-- reg: physical base address of the controller and length of memory mapped
-  region.
-
-- #clock-cells: should be 1.
-
-Each clock is assigned an identifier and client nodes can use this identifier
-to specify the clock which they consume.
-
-All available clocks are defined as preprocessor macros in
-dt-bindings/clock/exynos4415.h header and can be used in device
-tree sources.
-
-Example 1: An example of a clock controller node is listed below.
-
-	cmu: clock-controller@10030000 {
-		compatible = "samsung,exynos4415-cmu";
-		reg = <0x10030000 0x18000>;
-		#clock-cells = <1>;
-	};
-
-	cmu-dmc: clock-controller@105C0000 {
-		compatible = "samsung,exynos4415-cmu-dmc";
-		reg = <0x105C0000 0x3000>;
-		#clock-cells = <1>;
-	};

Documentation/devicetree/bindings/clock/hi3660-clock.txt

View file

diff --git a/Documentation/devicetree/bindings/clock/hi3660-clock.txt b/Documentation/devicetree/bindings/clock/hi3660-clock.txt
new file mode 100644
index 0000000..cc9b86c
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/hi3660-clock.txt
@@ -0,0 +1,42 @@
+* Hisilicon Hi3660 Clock Controller
+
+The Hi3660 clock controller generates and supplies clock to various
+controllers within the Hi3660 SoC.
+
+Required Properties:
+
+- compatible: the compatible should be one of the following strings to
+	indicate the clock controller functionality.
+
+	- "hisilicon,hi3660-crgctrl"
+	- "hisilicon,hi3660-pctrl"
+	- "hisilicon,hi3660-pmuctrl"
+	- "hisilicon,hi3660-sctrl"
+	- "hisilicon,hi3660-iomcu"
+
+- reg: physical base address of the controller and length of memory mapped
+  region.
+
+- #clock-cells: should be 1.
+
+Each clock is assigned an identifier and client nodes use this identifier
+to specify the clock which they consume.
+
+All these identifier could be found in <dt-bindings/clock/hi3660-clock.h>.
+
+Examples:
+	crg_ctrl: clock-controller@fff35000 {
+		compatible = "hisilicon,hi3660-crgctrl", "syscon";
+		reg = <0x0 0xfff35000 0x0 0x1000>;
+		#clock-cells = <1>;
+	};
+
+	uart0: serial@fdf02000 {
+		compatible = "arm,pl011", "arm,primecell";
+		reg = <0x0 0xfdf02000 0x0 0x1000>;
+		interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>,
+			 <&crg_ctrl HI3660_PCLK>;
+		clock-names = "uartclk", "apb_pclk";
+		status = "disabled";
+	};

Documentation/devicetree/bindings/clock/idt,versaclock5.txt

View file

diff --git a/Documentation/devicetree/bindings/clock/idt,versaclock5.txt b/Documentation/devicetree/bindings/clock/idt,versaclock5.txt
new file mode 100644
index 0000000..87e9c47
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/idt,versaclock5.txt
@@ -0,0 +1,65 @@
+Binding for IDT VersaClock5 programmable i2c clock generator.
+
+The IDT VersaClock5 are programmable i2c clock generators providing
+from 3 to 12 output clocks.
+
+==I2C device node==
+
+Required properties:
+- compatible:	shall be one of "idt,5p49v5923" , "idt,5p49v5933".
+- reg:		i2c device address, shall be 0x68 or 0x6a.
+- #clock-cells:	from common clock binding; shall be set to 1.
+- clocks:	from common clock binding; list of parent clock handles,
+		- 5p49v5923: (required) either or both of XTAL or CLKIN
+					reference clock.
+		- 5p49v5933: (optional) property not present (internal
+					Xtal used) or CLKIN reference
+					clock.
+- clock-names:	from common clock binding; clock input names, can be
+		- 5p49v5923: (required) either or both of "xin", "clkin".
+		- 5p49v5933: (optional) property not present or "clkin".
+
+==Mapping between clock specifier and physical pins==
+
+When referencing the provided clock in the DT using phandle and
+clock specifier, the following mapping applies:
+
+5P49V5923:
+	0 -- OUT0_SEL_I2CB
+	1 -- OUT1
+	2 -- OUT2
+
+5P49V5933:
+	0 -- OUT0_SEL_I2CB
+	1 -- OUT1
+	2 -- OUT4
+
+==Example==
+
+/* 25MHz reference crystal */
+ref25: ref25m {
+	compatible = "fixed-clock";
+	#clock-cells = <0>;
+	clock-frequency = <25000000>;
+};
+
+i2c-master-node {
+
+	/* IDT 5P49V5923 i2c clock generator */
+	vc5: clock-generator@6a {
+		compatible = "idt,5p49v5923";
+		reg = <0x6a>;
+		#clock-cells = <1>;
+
+		/* Connect XIN input to 25MHz reference */
+		clocks = <&ref25m>;
+		clock-names = "xin";
+	};
+};
+
+/* Consumer referencing the 5P49V5923 pin OUT1 */
+consumer {
+	...
+	clocks = <&vc5 1>;
+	...
+}

Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt

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diff --git a/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt
index 520562a..c7b4e3a 100644
--- a/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt
+++ b/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt
@@ -7,6 +7,7 @@ Required properties:
 - compatible : must be "marvell,armada-370-corediv-clock",
 		       "marvell,armada-375-corediv-clock",
 		       "marvell,armada-380-corediv-clock",
+                       "marvell,mv98dx3236-corediv-clock",
 
 - reg : must be the register address of Core Divider control register
 - #clock-cells : from common clock binding; shall be set to 1

Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt

View file

diff --git a/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt
index 99c2146..7f28506 100644
--- a/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt
+++ b/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt
@@ -3,6 +3,7 @@ Device Tree Clock bindings for cpu clock of Marvell EBU platforms
 Required properties:
 - compatible : shall be one of the following:
 	"marvell,armada-xp-cpu-clock" - cpu clocks for Armada XP
+	"marvell,mv98dx3236-cpu-clock" - cpu clocks for 98DX3236 SoC
 - reg : Address and length of the clock complex register set, followed
         by address and length of the PMU DFS registers
 - #clock-cells : should be set to 1.

Documentation/devicetree/bindings/clock/qcom,rpmcc.txt

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diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
index 87d3714..a7235e9 100644
--- a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
@@ -11,6 +11,7 @@ Required properties :
                compatible "qcom,rpmcc" should be also included.
 
 			"qcom,rpmcc-msm8916", "qcom,rpmcc"
+			"qcom,rpmcc-msm8974", "qcom,rpmcc"
 			"qcom,rpmcc-apq8064", "qcom,rpmcc"
 
 - #clock-cells : shall contain 1

Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt

View file

diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
index c469194..f4f944d 100644
--- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
@@ -42,6 +42,10 @@ Required Properties:
 	Domain bindings in
 	Documentation/devicetree/bindings/power/power_domain.txt.
 
+  - #reset-cells: Must be 1
+      - The single reset specifier cell must be the module number, as defined
+	in the datasheet.
+
 
 Examples
 --------
@@ -55,6 +59,7 @@ Examples
 		clock-names = "extal", "extalr";
 		#clock-cells = <2>;
 		#power-domain-cells = <0>;
+		#reset-cells = <1>;
 	};
 
 
@@ -69,5 +74,6 @@ Examples
 		dmas = <&dmac1 0x13>, <&dmac1 0x12>;
 		dma-names = "tx", "rx";
 		power-domains = <&cpg>;
+		resets = <&cpg 310>;
 		status = "disabled";
 	};

Documentation/devicetree/bindings/clock/rockchip,rk3328-cru.txt

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diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3328-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3328-cru.txt
new file mode 100644
index 0000000..e71c675
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3328-cru.txt
@@ -0,0 +1,57 @@
+* Rockchip RK3328 Clock and Reset Unit
+
+The RK3328 clock controller generates and supplies clock to various
+controllers within the SoC and also implements a reset controller for SoC
+peripherals.
+
+Required Properties:
+
+- compatible: should be "rockchip,rk3328-cru"
+- reg: physical base address of the controller and length of memory mapped
+  region.
+- #clock-cells: should be 1.
+- #reset-cells: should be 1.
+
+Optional Properties:
+
+- rockchip,grf: phandle to the syscon managing the "general register files"
+  If missing pll rates are not changeable, due to the missing pll lock status.
+
+Each clock is assigned an identifier and client nodes can use this identifier
+to specify the clock which they consume. All available clocks are defined as
+preprocessor macros in the dt-bindings/clock/rk3328-cru.h headers and can be
+used in device tree sources. Similar macros exist for the reset sources in
+these files.
+
+External clocks:
+
+There are several clocks that are generated outside the SoC. It is expected
+that they are defined using standard clock bindings with following
+clock-output-names:
+ - "xin24m" - crystal input - required,
+ - "clkin_i2s" - external I2S clock - optional,
+ - "gmac_clkin" - external GMAC clock - optional
+ - "phy_50m_out" - output clock of the pll in the mac phy
+
+Example: Clock controller node:
+
+	cru: clock-controller@ff440000 {
+		compatible = "rockchip,rk3328-cru";
+		reg = <0x0 0xff440000 0x0 0x1000>;
+		rockchip,grf = <&grf>;
+
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+Example: UART controller node that consumes the clock generated by the clock
+  controller:
+
+	uart0: serial@ff120000 {
+		compatible = "snps,dw-apb-uart";
+		reg = <0xff120000 0x100>;
+		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+		reg-shift = <2>;
+		reg-io-width = <4>;
+		clocks = <&cru SCLK_UART0>;
+	};

Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt

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diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt
index 3888dd3..3bc56fa 100644
--- a/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt
+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt
@@ -13,6 +13,12 @@ Required Properties:
 - #clock-cells: should be 1.
 - #reset-cells: should be 1.
 
+Optional Properties:
+
+- rockchip,grf: phandle to the syscon managing the "general register files".
+  It is used for GRF muxes, if missing any muxes present in the GRF will not
+  be available.
+
 Each clock is assigned an identifier and client nodes can use this identifier
 to specify the clock which they consume. All available clocks are defined as
 preprocessor macros in the dt-bindings/clock/rk3399-cru.h headers and can be

Documentation/devicetree/bindings/clock/st,stm32-rcc.txt

View file

diff --git a/Documentation/devicetree/bindings/clock/st,stm32-rcc.txt b/Documentation/devicetree/bindings/clock/st,stm32-rcc.txt
index 8f19d87..b240121 100644
--- a/Documentation/devicetree/bindings/clock/st,stm32-rcc.txt
+++ b/Documentation/devicetree/bindings/clock/st,stm32-rcc.txt
@@ -10,6 +10,7 @@ Required properties:
 - compatible: Should be:
   "st,stm32f42xx-rcc"
   "st,stm32f469-rcc"
+  "st,stm32f746-rcc"
 - reg: should be register base and length as documented in the
   datasheet
 - #reset-cells: 1, see below
@@ -84,6 +85,25 @@ The secondary index is bound with the following magic numbers:
 	12	CLK_I2SQ_PDIV	(post divisor of pll i2s q divisor)
 	13	CLK_SAIQ_PDIV	(post divisor of pll sai q divisor)
 
+	14	CLK_HSI		(Internal ocscillator clock)
+	15	CLK_SYSCLK	(System Clock)
+	16	CLK_HDMI_CEC	(HDMI-CEC clock)
+	17	CLK_SPDIF	(SPDIF-Rx clock)
+	18	CLK_USART1	(U(s)arts clocks)
+	19	CLK_USART2
+	20	CLK_USART3
+	21	CLK_UART4
+	22	CLK_UART5
+	23	CLK_USART6
+	24	CLK_UART7
+	25	CLK_UART8
+	26	CLK_I2C1	(I2S clocks)
+	27	CLK_I2C2
+	28	CLK_I2C3
+	29	CLK_I2C4
+	30	CLK_LPTIMER	(LPTimer1 clock)
+)
+
 Example:
 
 	/* Misc clock, FCLK */

Documentation/devicetree/bindings/clock/stericsson,abx500.txt

View file

diff --git a/Documentation/devicetree/bindings/clock/stericsson,abx500.txt b/Documentation/devicetree/bindings/clock/stericsson,abx500.txt
new file mode 100644
index 0000000..dbaa886
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/stericsson,abx500.txt
@@ -0,0 +1,20 @@
+Clock bindings for ST-Ericsson ABx500 clocks
+
+Required properties :
+- compatible : shall contain the following:
+  "stericsson,ab8500-clk"
+- #clock-cells should be <1>
+
+The ABx500 clocks need to be placed as a subnode of an AB8500
+device node, see mfd/ab8500.txt
+
+All available clocks are defined as preprocessor macros in
+dt-bindings/clock/ste-ab8500.h header and can be used in device
+tree sources.
+
+Example:
+
+clock-controller {
+	compatible = "stericsson,ab8500-clk";
+	#clock-cells = <1>;
+};

Documentation/devicetree/bindings/clock/sun9i-de.txt

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diff --git a/Documentation/devicetree/bindings/clock/sun9i-de.txt b/Documentation/devicetree/bindings/clock/sun9i-de.txt
new file mode 100644
index 0000000..fb18f32
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/sun9i-de.txt
@@ -0,0 +1,28 @@
+Allwinner A80 Display Engine Clock Control Binding
+--------------------------------------------------
+
+Required properties :
+- compatible: must contain one of the following compatibles:
+		- "allwinner,sun9i-a80-de-clks"
+
+- reg: Must contain the registers base address and length
+- clocks: phandle to the clocks feeding the display engine subsystem.
+	  Three are needed:
+  - "mod": the display engine module clock
+  - "dram": the DRAM bus clock for the system
+  - "bus": the bus clock for the whole display engine subsystem
+- clock-names: Must contain the clock names described just above
+- resets: phandle to the reset control for the display engine subsystem.
+- #clock-cells : must contain 1
+- #reset-cells : must contain 1
+
+Example:
+de_clocks: clock@3000000 {
+	compatible = "allwinner,sun9i-a80-de-clks";
+	reg = <0x03000000 0x30>;
+	clocks = <&ccu CLK_DE>, <&ccu CLK_SDRAM>, <&ccu CLK_BUS_DE>;
+	clock-names = "mod", "dram", "bus";
+	resets = <&ccu RST_BUS_DE>;
+	#clock-cells = <1>;
+	#reset-cells = <1>;
+};

Documentation/devicetree/bindings/clock/sun9i-usb.txt

View file

diff --git a/Documentation/devicetree/bindings/clock/sun9i-usb.txt b/Documentation/devicetree/bindings/clock/sun9i-usb.txt
new file mode 100644
index 0000000..3564bd4
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/sun9i-usb.txt
@@ -0,0 +1,24 @@
+Allwinner A80 USB Clock Control Binding
+---------------------------------------
+
+Required properties :
+- compatible: must contain one of the following compatibles:
+		- "allwinner,sun9i-a80-usb-clocks"
+
+- reg: Must contain the registers base address and length
+- clocks: phandle to the clocks feeding the USB subsystem. Two are needed:
+  - "bus": the bus clock for the whole USB subsystem
+  - "hosc": the high frequency oscillator (usually at 24MHz)
+- clock-names: Must contain the clock names described just above
+- #clock-cells : must contain 1
+- #reset-cells : must contain 1
+
+Example:
+usb_clocks: clock@a08000 {
+	compatible = "allwinner,sun9i-a80-usb-clks";
+	reg = <0x00a08000 0x8>;
+	clocks = <&ccu CLK_BUS_USB>, <&osc24M>;
+	clock-names = "bus", "hosc";
+	#clock-cells = <1>;
+	#reset-cells = <1>;
+};

Documentation/devicetree/bindings/clock/sunxi-ccu.txt

View file

diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
index 74d44a4..bae5668 100644
--- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
@@ -7,6 +7,8 @@ Required properties :
 		- "allwinner,sun8i-a23-ccu"
 		- "allwinner,sun8i-a33-ccu"
 		- "allwinner,sun8i-h3-ccu"
+		- "allwinner,sun8i-v3s-ccu"
+		- "allwinner,sun9i-a80-ccu"
 		- "allwinner,sun50i-a64-ccu"
 
 - reg: Must contain the registers base address and length

Documentation/devicetree/bindings/clock/ti,cdce925.txt

View file

diff --git a/Documentation/devicetree/bindings/clock/ti,cdce925.txt b/Documentation/devicetree/bindings/clock/ti,cdce925.txt
index 4c7669a..0d01f2d 100644
--- a/Documentation/devicetree/bindings/clock/ti,cdce925.txt
+++ b/Documentation/devicetree/bindings/clock/ti,cdce925.txt
@@ -1,15 +1,22 @@
-Binding for TO CDCE925 programmable I2C clock synthesizers.
+Binding for TI CDCE913/925/937/949 programmable I2C clock synthesizers.
 
 Reference
 This binding uses the common clock binding[1].
 
 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
-[2] http://www.ti.com/product/cdce925
+[2] http://www.ti.com/product/cdce913
+[3] http://www.ti.com/product/cdce925
+[4] http://www.ti.com/product/cdce937
+[5] http://www.ti.com/product/cdce949
 
 The driver provides clock sources for each output Y1 through Y5.
 
 Required properties:
- - compatible: Shall be "ti,cdce925"
+ - compatible: Shall be one of the following:
+	- "ti,cdce913": 1-PLL, 3 Outputs
+	- "ti,cdce925": 2-PLL, 5 Outputs
+	- "ti,cdce937": 3-PLL, 7 Outputs
+	- "ti,cdce949": 4-PLL, 9 Outputs
  - reg: I2C device address.
  - clocks: Points to a fixed parent clock that provides the input frequency.
  - #clock-cells: From common clock bindings: Shall be 1.
@@ -18,7 +25,7 @@ Optional properties:
  - xtal-load-pf: Crystal load-capacitor value to fine-tune performance on a
                  board, or to compensate for external influences.
 
-For both PLL1 and PLL2 an optional child node can be used to specify spread
+For all PLL1, PLL2, ... an optional child node can be used to specify spread
 spectrum clocking parameters for a board.
   - spread-spectrum: SSC mode as defined in the data sheet.
   - spread-spectrum-center: Use "centered" mode instead of "max" mode. When

Documentation/devicetree/bindings/clock/zx296718-clk.txt

View file

diff --git a/Documentation/devicetree/bindings/clock/zx296718-clk.txt b/Documentation/devicetree/bindings/clock/zx296718-clk.txt
index 8c18b7b..4ad7038 100644
--- a/Documentation/devicetree/bindings/clock/zx296718-clk.txt
+++ b/Documentation/devicetree/bindings/clock/zx296718-clk.txt
@@ -13,6 +13,9 @@ Required properties:
 	"zte,zx296718-lsp1crm":
 		zx296718 device level clock selection and gating
 
+	"zte,zx296718-audiocrm":
+		zx296718 audio clock selection, divider and gating
+
 - reg: Address and length of the register set
 
 The clock consumer should specify the desired clock by having the clock

MAINTAINERS

View file

diff --git a/MAINTAINERS b/MAINTAINERS
index 8f05fac..dedc66c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6270,6 +6270,11 @@ S:	Maintained
 F:	drivers/mfd/lpc_ich.c
 F:	drivers/gpio/gpio-ich.c
 
+IDT VersaClock 5 CLOCK DRIVER
+M:	Marek Vasut <[email protected]>
+S:	Maintained
+F:	drivers/clk/clk-versaclock5.c
+
 IDE SUBSYSTEM
 M:	"David S. Miller" <[email protected]>
 L:	[email protected]

arch/arm/boot/dts/sun5i-a10s.dtsi

View file

diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index 62b3ffe..24b0f5f 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -65,8 +65,9 @@
 			compatible = "allwinner,simple-framebuffer",
 				     "simple-framebuffer";
 			allwinner,pipeline = "de_be0-lcd0-hdmi";
-			clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>,
-				 <&ahb_gates 43>, <&ahb_gates 44>;
+			clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_AHB_HDMI>,
+				 <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DRAM_DE_BE>,
+				 <&ccu CLK_DE_BE>, <&ccu CLK_HDMI>;
 			status = "disabled";
 		};
 
@@ -74,8 +75,8 @@
 			compatible = "allwinner,simple-framebuffer",
 				     "simple-framebuffer";
 			allwinner,pipeline = "de_be0-lcd0";
-			clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>,
-				 <&ahb_gates 44>;
+			clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
+				 <&ccu CLK_TCON_CH0>, <&ccu CLK_DRAM_DE_BE>;
 			status = "disabled";
 		};
 
@@ -83,77 +84,19 @@
 			compatible = "allwinner,simple-framebuffer",
 				     "simple-framebuffer";
 			allwinner,pipeline = "de_be0-lcd0-tve0";
-			clocks = <&pll3>, <&pll5 1>, <&ahb_gates 34>,
-				 <&ahb_gates 36>, <&ahb_gates 44>;
+			clocks = <&ccu CLK_AHB_TVE>, <&ccu CLK_AHB_LCD>,
+				 <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
+				 <&ccu CLK_TCON_CH1>, <&ccu CLK_DRAM_DE_BE>;
 			status = "disabled";
 		};
 	};
 
-	clocks {
-		ahb_gates: clk@01c20060 {
-			#clock-cells = <1>;
-			compatible = "allwinner,sun5i-a10s-ahb-gates-clk";
-			reg = <0x01c20060 0x8>;
-			clocks = <&ahb>;
-			clock-indices = <0>, <1>,
-					<2>, <5>, <6>,
-					<7>, <8>, <9>,
-					<10>, <13>,
-					<14>, <17>, <18>,
-					<20>, <21>, <22>,
-					<26>, <28>, <32>,
-					<34>, <36>, <40>,
-					<43>, <44>,