diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c index a0364ca..ea97fec 100644 --- a/arch/x86/events/amd/uncore.c +++ b/arch/x86/events/amd/uncore.c @@ -966,7 +966,7 @@ static void amd_uncore_umc_read(struct perf_event *event) * UMC counters do not have RDPMC assignments. Read counts directly * from the corresponding PERF_CTR. */ - rdmsrl(hwc->event_base, new); + rdmsrq(hwc->event_base, new); /* * Unlike the other uncore counters, UMC counters saturate and set the @@ -975,7 +975,7 @@ static void amd_uncore_umc_read(struct perf_event *event) * that the counter never gets a chance to saturate. */ if (new & BIT_ULL(63 - COUNTER_SHIFT)) { - wrmsrl(hwc->event_base, 0); + wrmsrq(hwc->event_base, 0); local64_set(&hwc->prev_count, 0); } else { local64_set(&hwc->prev_count, new); diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 6f4e0e5..c819b06 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -3417,12 +3417,12 @@ static void intel_pmu_config_acr(int idx, u64 mask, u32 reload) } if (cpuc->acr_cfg_b[idx] != mask) { - wrmsrl(msr_b + msr_offset, mask); + wrmsrq(msr_b + msr_offset, mask); cpuc->acr_cfg_b[idx] = mask; } /* Only update CFG_C reload when ACR is actively enabled (mask != 0) */ if (mask && ((cpuc->cfg_c_val[idx] & ARCH_PEBS_RELOAD) != reload)) { - wrmsrl(msr_c + msr_offset, reload); + wrmsrq(msr_c + msr_offset, reload); cpuc->cfg_c_val[idx] = reload; } } diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c index cb72af9..91a093d 100644 --- a/arch/x86/events/intel/ds.c +++ b/arch/x86/events/intel/ds.c @@ -780,9 +780,7 @@ void init_debug_store_on_cpu(int cpu) if (!ds) return; - wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, - (u32)((u64)(unsigned long)ds), - (u32)((u64)(unsigned long)ds >> 32)); + wrmsrq_on_cpu(cpu, MSR_IA32_DS_AREA, (u64)(unsigned long)ds); } void fini_debug_store_on_cpu(int cpu) @@ -790,7 +788,7 @@ void fini_debug_store_on_cpu(int cpu) if (!per_cpu(cpu_hw_events, cpu).ds) return; - wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0); + wrmsrq_on_cpu(cpu, MSR_IA32_DS_AREA, 0); } static DEFINE_PER_CPU(void *, insn_buffer); @@ -1095,8 +1093,7 @@ void init_arch_pebs_on_cpu(int cpu) * contiguous physical buffer (__alloc_pages_node() with order) */ arch_pebs_base = virt_to_phys(cpuc->pebs_vaddr) | PEBS_BUFFER_SHIFT; - wrmsr_on_cpu(cpu, MSR_IA32_PEBS_BASE, (u32)arch_pebs_base, - (u32)(arch_pebs_base >> 32)); + wrmsrq_on_cpu(cpu, MSR_IA32_PEBS_BASE, arch_pebs_base); x86_pmu.pebs_active = 1; } @@ -1105,7 +1102,7 @@ inline void fini_arch_pebs_on_cpu(int cpu) if (!x86_pmu.arch_pebs) return; - wrmsr_on_cpu(cpu, MSR_IA32_PEBS_BASE, 0, 0); + wrmsrq_on_cpu(cpu, MSR_IA32_PEBS_BASE, 0); } /* diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index 9c2ea29..2f41a92 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -256,29 +256,15 @@ int msr_set_bit(u32 msr, u8 bit); int msr_clear_bit(u32 msr, u8 bit); #ifdef CONFIG_SMP -int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h); -int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h); int rdmsrq_on_cpu(unsigned int cpu, u32 msr_no, u64 *q); int wrmsrq_on_cpu(unsigned int cpu, u32 msr_no, u64 q); void rdmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr __percpu *msrs); void wrmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr __percpu *msrs); -int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h); -int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h); int rdmsrq_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q); int wrmsrq_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 q); int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]); int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]); #else /* CONFIG_SMP */ -static inline int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h) -{ - rdmsr(msr_no, *l, *h); - return 0; -} -static inline int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h) -{ - wrmsr(msr_no, l, h); - return 0; -} static inline int rdmsrq_on_cpu(unsigned int cpu, u32 msr_no, u64 *q) { rdmsrq(msr_no, *q); @@ -292,21 +278,12 @@ static inline int wrmsrq_on_cpu(unsigned int cpu, u32 msr_no, u64 q) static inline void rdmsr_on_cpus(const struct cpumask *m, u32 msr_no, struct msr __percpu *msrs) { - rdmsr_on_cpu(0, msr_no, raw_cpu_ptr(&msrs->l), raw_cpu_ptr(&msrs->h)); + rdmsrq_on_cpu(0, msr_no, raw_cpu_ptr(&msrs->q)); } static inline void wrmsr_on_cpus(const struct cpumask *m, u32 msr_no, struct msr __percpu *msrs) { - wrmsr_on_cpu(0, msr_no, raw_cpu_read(msrs->l), raw_cpu_read(msrs->h)); -} -static inline int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, - u32 *l, u32 *h) -{ - return rdmsr_safe(msr_no, l, h); -} -static inline int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h) -{ - return wrmsr_safe(msr_no, l, h); + wrmsrq_on_cpu(0, msr_no, raw_cpu_read(msrs->q)); } static inline int rdmsrq_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q) { @@ -325,11 +302,5 @@ static inline int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]) return wrmsr_safe_regs(regs); } #endif /* CONFIG_SMP */ - -/* Compatibility wrappers: */ -#define rdmsrl(msr, val) rdmsrq(msr, val) -#define wrmsrl(msr, val) wrmsrq(msr, val) -#define rdmsrl_on_cpu(cpu, msr, q) rdmsrq_on_cpu(cpu, msr, q) - #endif /* __ASSEMBLER__ */ #endif /* _ASM_X86_MSR_H */ diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 222fa9c..36e0df4 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -969,13 +969,13 @@ store_threshold_limit(struct threshold_block *b, const char *buf, size_t size) static ssize_t show_error_count(struct threshold_block *b, char *buf) { - u32 lo, hi; + struct msr val; /* CPU might be offline by now */ - if (rdmsr_on_cpu(b->cpu, b->address, &lo, &hi)) + if (rdmsrq_on_cpu(b->cpu, b->address, &val.q)) return -ENODEV; - return sprintf(buf, "%u\n", ((hi & THRESHOLD_MAX) - + return sprintf(buf, "%u\n", ((val.h & THRESHOLD_MAX) - (THRESHOLD_MAX - b->threshold_limit))); } diff --git a/arch/x86/kernel/cpu/mce/inject.c b/arch/x86/kernel/cpu/mce/inject.c index d02c4f5..6d30e77 100644 --- a/arch/x86/kernel/cpu/mce/inject.c +++ b/arch/x86/kernel/cpu/mce/inject.c @@ -316,18 +316,18 @@ static struct notifier_block inject_nb = { */ static int toggle_hw_mce_inject(unsigned int cpu, bool enable) { - u32 l, h; + struct msr val; int err; - err = rdmsr_on_cpu(cpu, MSR_K7_HWCR, &l, &h); + err = rdmsrq_on_cpu(cpu, MSR_K7_HWCR, &val.q); if (err) { pr_err("%s: error reading HWCR\n", __func__); return err; } - enable ? (l |= BIT(18)) : (l &= ~BIT(18)); + enable ? (val.l |= BIT(18)) : (val.l &= ~BIT(18)); - err = wrmsr_on_cpu(cpu, MSR_K7_HWCR, l, h); + err = wrmsrq_on_cpu(cpu, MSR_K7_HWCR, val.q); if (err) pr_err("%s: error writing HWCR\n", __func__); diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/resctrl/monitor.c index 59215fe..e4918c3 100644 --- a/arch/x86/kernel/cpu/resctrl/monitor.c +++ b/arch/x86/kernel/cpu/resctrl/monitor.c @@ -301,7 +301,7 @@ static int __cntr_id_read(u32 cntr_id, u64 *val) * is set if the counter data is unavailable. */ wrmsr(MSR_IA32_QM_EVTSEL, ABMC_EXTENDED_EVT_ID | ABMC_EVT_ID, cntr_id); - rdmsrl(MSR_IA32_QM_CTR, msr_val); + rdmsrq(MSR_IA32_QM_CTR, msr_val); if (msr_val & RMID_VAL_ERROR) return -EIO; @@ -532,7 +532,7 @@ static void resctrl_abmc_config_one_amd(void *info) { union l3_qos_abmc_cfg *abmc_cfg = info; - wrmsrl(MSR_IA32_L3_QOS_ABMC_CFG, abmc_cfg->full); + wrmsrq(MSR_IA32_L3_QOS_ABMC_CFG, abmc_cfg->full); } /* diff --git a/arch/x86/kernel/msr.c b/arch/x86/kernel/msr.c index 4469c78..34bdb75 100644 --- a/arch/x86/kernel/msr.c +++ b/arch/x86/kernel/msr.c @@ -53,7 +53,7 @@ static ssize_t msr_read(struct file *file, char __user *buf, size_t count, loff_t *ppos) { u32 __user *tmp = (u32 __user *) buf; - u32 data[2]; + u64 data; u32 reg = *ppos; int cpu = iminor(file_inode(file)); int err = 0; @@ -63,7 +63,7 @@ static ssize_t msr_read(struct file *file, char __user *buf, return -EINVAL; /* Invalid chunk size */ for (; count; count -= 8) { - err = rdmsr_safe_on_cpu(cpu, reg, &data[0], &data[1]); + err = rdmsrq_safe_on_cpu(cpu, reg, &data); if (err) break; if (copy_to_user(tmp, &data, 8)) { @@ -109,7 +109,7 @@ static ssize_t msr_write(struct file *file, const char __user *buf, size_t count, loff_t *ppos) { const u32 __user *tmp = (const u32 __user *)buf; - u32 data[2]; + u64 data; u32 reg = *ppos; int cpu = iminor(file_inode(file)); int err = 0; @@ -134,7 +134,7 @@ static ssize_t msr_write(struct file *file, const char __user *buf, add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); - err = wrmsr_safe_on_cpu(cpu, reg, data[0], data[1]); + err = wrmsrq_safe_on_cpu(cpu, reg, data); if (err) break; diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c index 4c718f8..a554f19 100644 --- a/arch/x86/kernel/process.c +++ b/arch/x86/kernel/process.c @@ -969,7 +969,7 @@ void amd_e400_c1e_apic_setup(void) void __init arch_post_acpi_subsys_init(void) { - u32 lo, hi; + u64 val; if (!boot_cpu_has_bug(X86_BUG_AMD_E400)) return; @@ -979,8 +979,8 @@ void __init arch_post_acpi_subsys_init(void) * the machine is affected K8_INTP_C1E_ACTIVE_MASK bits are set in * MSR_K8_INT_PENDING_MSG. */ - rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi); - if (!(lo & K8_INTP_C1E_ACTIVE_MASK)) + rdmsrq(MSR_K8_INT_PENDING_MSG, val); + if (!(val & K8_INTP_C1E_ACTIVE_MASK)) return; boot_cpu_set_bug(X86_BUG_AMD_APIC_C1E); diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c index b85e715..d44afbe 100644 --- a/arch/x86/kernel/process_64.c +++ b/arch/x86/kernel/process_64.c @@ -708,7 +708,7 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p) /* Reset hw history on AMD CPUs */ if (cpu_feature_enabled(X86_FEATURE_AMD_WORKLOAD_CLASS)) - wrmsrl(MSR_AMD_WORKLOAD_HRST, 0x1); + wrmsrq(MSR_AMD_WORKLOAD_HRST, 0x1); return prev_p; } diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c index e218352..aee70e5 100644 --- a/arch/x86/kvm/pmu.c +++ b/arch/x86/kvm/pmu.c @@ -1313,14 +1313,14 @@ static void kvm_pmu_load_guest_pmcs(struct kvm_vcpu *vcpu) pmc = &pmu->gp_counters[i]; if (pmc->counter != rdpmc(i)) - wrmsrl(gp_counter_msr(i), pmc->counter); - wrmsrl(gp_eventsel_msr(i), pmc->eventsel_hw); + wrmsrq(gp_counter_msr(i), pmc->counter); + wrmsrq(gp_eventsel_msr(i), pmc->eventsel_hw); } for (i = 0; i < pmu->nr_arch_fixed_counters; i++) { pmc = &pmu->fixed_counters[i]; if (pmc->counter != rdpmc(INTEL_PMC_FIXED_RDPMC_BASE | i)) - wrmsrl(fixed_counter_msr(i), pmc->counter); + wrmsrq(fixed_counter_msr(i), pmc->counter); } } diff --git a/arch/x86/kvm/vmx/tdx.c b/arch/x86/kvm/vmx/tdx.c index 04ce321..cb50e23 100644 --- a/arch/x86/kvm/vmx/tdx.c +++ b/arch/x86/kvm/vmx/tdx.c @@ -823,7 +823,7 @@ static void tdx_prepare_switch_to_host(struct kvm_vcpu *vcpu) return; ++vcpu->stat.host_state_reload; - wrmsrl(MSR_KERNEL_GS_BASE, vt->msr_host_kernel_gs_base); + wrmsrq(MSR_KERNEL_GS_BASE, vt->msr_host_kernel_gs_base); vt->guest_state_loaded = false; } @@ -1048,10 +1048,10 @@ static void tdx_load_host_xsave_state(struct kvm_vcpu *vcpu) /* * Likewise, even if a TDX hosts didn't support XSS both arms of - * the comparison would be 0 and the wrmsrl would be skipped. + * the comparison would be 0 and the wrmsrq would be skipped. */ if (kvm_host.xss != (kvm_tdx->xfam & kvm_caps.supported_xss)) - wrmsrl(MSR_IA32_XSS, kvm_host.xss); + wrmsrq(MSR_IA32_XSS, kvm_host.xss); } #define TDX_DEBUGCTL_PRESERVED (DEBUGCTLMSR_BTF | \ diff --git a/arch/x86/lib/msr-smp.c b/arch/x86/lib/msr-smp.c index b8f6341..0c66277 100644 --- a/arch/x86/lib/msr-smp.c +++ b/arch/x86/lib/msr-smp.c @@ -31,22 +31,6 @@ static void __wrmsr_on_cpu(void *info) wrmsr(rv->msr_no, reg->l, reg->h); } -int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h) -{ - int err; - struct msr_info rv; - - memset(&rv, 0, sizeof(rv)); - - rv.msr_no = msr_no; - err = smp_call_function_single(cpu, __rdmsr_on_cpu, &rv, 1); - *l = rv.reg.l; - *h = rv.reg.h; - - return err; -} -EXPORT_SYMBOL(rdmsr_on_cpu); - int rdmsrq_on_cpu(unsigned int cpu, u32 msr_no, u64 *q) { int err; @@ -62,22 +46,6 @@ int rdmsrq_on_cpu(unsigned int cpu, u32 msr_no, u64 *q) } EXPORT_SYMBOL(rdmsrq_on_cpu); -int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h) -{ - int err; - struct msr_info rv; - - memset(&rv, 0, sizeof(rv)); - - rv.msr_no = msr_no; - rv.reg.l = l; - rv.reg.h = h; - err = smp_call_function_single(cpu, __wrmsr_on_cpu, &rv, 1); - - return err; -} -EXPORT_SYMBOL(wrmsr_on_cpu); - int wrmsrq_on_cpu(unsigned int cpu, u32 msr_no, u64 q) { int err; @@ -164,46 +132,6 @@ static void __wrmsr_safe_on_cpu(void *info) rv->err = wrmsr_safe(rv->msr_no, rv->reg.l, rv->reg.h); } -int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h) -{ - struct msr_info_completion rv; - call_single_data_t csd; - int err; - - INIT_CSD(&csd, __rdmsr_safe_on_cpu, &rv); - - memset(&rv, 0, sizeof(rv)); - init_completion(&rv.done); - rv.msr.msr_no = msr_no; - - err = smp_call_function_single_async(cpu, &csd); - if (!err) { - wait_for_completion(&rv.done); - err = rv.msr.err; - } - *l = rv.msr.reg.l; - *h = rv.msr.reg.h; - - return err; -} -EXPORT_SYMBOL(rdmsr_safe_on_cpu); - -int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h) -{ - int err; - struct msr_info rv; - - memset(&rv, 0, sizeof(rv)); - - rv.msr_no = msr_no; - rv.reg.l = l; - rv.reg.h = h; - err = smp_call_function_single(cpu, __wrmsr_safe_on_cpu, &rv, 1); - - return err ? err : rv.err; -} -EXPORT_SYMBOL(wrmsr_safe_on_cpu); - int wrmsrq_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 q) { int err; @@ -222,11 +150,22 @@ EXPORT_SYMBOL(wrmsrq_safe_on_cpu); int rdmsrq_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q) { - u32 low, high; + struct msr_info_completion rv; + call_single_data_t csd; int err; - err = rdmsr_safe_on_cpu(cpu, msr_no, &low, &high); - *q = (u64)high << 32 | low; + INIT_CSD(&csd, __rdmsr_safe_on_cpu, &rv); + + memset(&rv, 0, sizeof(rv)); + init_completion(&rv.done); + rv.msr.msr_no = msr_no; + + err = smp_call_function_single_async(cpu, &csd); + if (!err) { + wait_for_completion(&rv.done); + err = rv.msr.err; + } + *q = rv.msr.reg.q; return err; } diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index f5154c7..3a80ace 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -472,7 +472,7 @@ static int msr_init_perf(struct amd_cpudata *cpudata) if (ret) return ret; - ret = rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, &cppc_req); + ret = rdmsrq_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, &cppc_req); if (ret) return ret; diff --git a/drivers/cpufreq/amd_freq_sensitivity.c b/drivers/cpufreq/amd_freq_sensitivity.c index 13fed4b..739d54d 100644 --- a/drivers/cpufreq/amd_freq_sensitivity.c +++ b/drivers/cpufreq/amd_freq_sensitivity.c @@ -51,10 +51,8 @@ static unsigned int amd_powersave_bias_target(struct cpufreq_policy *policy, if (!policy->freq_table) return freq_next; - rdmsr_on_cpu(policy->cpu, MSR_AMD64_FREQ_SENSITIVITY_ACTUAL, - &actual.l, &actual.h); - rdmsr_on_cpu(policy->cpu, MSR_AMD64_FREQ_SENSITIVITY_REFERENCE, - &reference.l, &reference.h); + rdmsrq_on_cpu(policy->cpu, MSR_AMD64_FREQ_SENSITIVITY_ACTUAL, &actual.q); + rdmsrq_on_cpu(policy->cpu, MSR_AMD64_FREQ_SENSITIVITY_REFERENCE, &reference.q); actual.h &= 0x00ffffff; reference.h &= 0x00ffffff; diff --git a/drivers/cpufreq/p4-clockmod.c b/drivers/cpufreq/p4-clockmod.c index 69c1923..c1690aa 100644 --- a/drivers/cpufreq/p4-clockmod.c +++ b/drivers/cpufreq/p4-clockmod.c @@ -51,24 +51,24 @@ static unsigned int cpufreq_p4_get(unsigned int cpu); static int cpufreq_p4_setdc(unsigned int cpu, unsigned int newstate) { - u32 l, h; + struct msr val; if ((newstate > DC_DISABLE) || (newstate == DC_RESV)) return -EINVAL; - rdmsr_on_cpu(cpu, MSR_IA32_THERM_STATUS, &l, &h); + rdmsrq_on_cpu(cpu, MSR_IA32_THERM_STATUS, &val.q); - if (l & 0x01) + if (val.l & 0x01) pr_debug("CPU#%d currently thermal throttled\n", cpu); if (has_N44_O17_errata[cpu] && (newstate == DC_25PT || newstate == DC_DFLT)) newstate = DC_38PT; - rdmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, &l, &h); + rdmsrq_on_cpu(cpu, MSR_IA32_THERM_CONTROL, &val.q); if (newstate == DC_DISABLE) { pr_debug("CPU#%d disabling modulation\n", cpu); - wrmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, l & ~(1<<4), h); + wrmsrq_on_cpu(cpu, MSR_IA32_THERM_CONTROL, val.q & ~(1ULL << 4)); } else { pr_debug("CPU#%d setting duty cycle to %d%%\n", cpu, ((125 * newstate) / 10)); @@ -77,9 +77,9 @@ static int cpufreq_p4_setdc(unsigned int cpu, unsigned int newstate) * bits 3-1 : duty cycle * bit 0 : reserved */ - l = (l & ~14); - l = l | (1<<4) | ((newstate & 0x7)<<1); - wrmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, l, h); + val.l = (val.l & ~14); + val.l = val.l | (1<<4) | ((newstate & 0x7)<<1); + wrmsrq_on_cpu(cpu, MSR_IA32_THERM_CONTROL, val.q); } return 0; @@ -205,18 +205,18 @@ static int cpufreq_p4_cpu_init(struct cpufreq_policy *policy) static unsigned int cpufreq_p4_get(unsigned int cpu) { - u32 l, h; + struct msr val; - rdmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, &l, &h); + rdmsrq_on_cpu(cpu, MSR_IA32_THERM_CONTROL, &val.q); - if (l & 0x10) { - l = l >> 1; - l &= 0x7; + if (val.l & 0x10) { + val.l = val.l >> 1; + val.l &= 0x7; } else - l = DC_DISABLE; + val.l = DC_DISABLE; - if (l != DC_DISABLE) - return stock_freq * l / 8; + if (val.l != DC_DISABLE) + return stock_freq * val.l / 8; return stock_freq; } diff --git a/drivers/cpufreq/speedstep-centrino.c b/drivers/cpufreq/speedstep-centrino.c index 3e6e85a..9237ed8 100644 --- a/drivers/cpufreq/speedstep-centrino.c +++ b/drivers/cpufreq/speedstep-centrino.c @@ -322,11 +322,11 @@ static unsigned extract_clock(unsigned msr, unsigned int cpu, int failsafe) /* Return the current CPU frequency in kHz */ static unsigned int get_cur_freq(unsigned int cpu) { - unsigned l, h; + struct msr val; unsigned clock_freq; - rdmsr_on_cpu(cpu, MSR_IA32_PERF_STATUS, &l, &h); - clock_freq = extract_clock(l, cpu, 0); + rdmsrq_on_cpu(cpu, MSR_IA32_PERF_STATUS, &val.q); + clock_freq = extract_clock(val.l, cpu, 0); if (unlikely(clock_freq == 0)) { /* @@ -335,8 +335,8 @@ static unsigned int get_cur_freq(unsigned int cpu) * P-state transition (like TM2). Get the last freq set * in PERF_CTL. */ - rdmsr_on_cpu(cpu, MSR_IA32_PERF_CTL, &l, &h); - clock_freq = extract_clock(l, cpu, 1); + rdmsrq_on_cpu(cpu, MSR_IA32_PERF_CTL, &val.q); + clock_freq = extract_clock(val.l, cpu, 1); } return clock_freq; } @@ -417,7 +417,8 @@ static void centrino_cpu_exit(struct cpufreq_policy *policy) */ static int centrino_target(struct cpufreq_policy *policy, unsigned int index) { - unsigned int msr, oldmsr = 0, h = 0, cpu = policy->cpu; + unsigned int msr, cpu = policy->cpu; + struct msr oldmsr = { .q = 0 }; int retval = 0; unsigned int j, first_cpu; struct cpufreq_frequency_table *op_points; @@ -459,22 +460,22 @@ static int centrino_target(struct cpufreq_policy *policy, unsigned int index) msr = op_points->driver_data; if (first_cpu) { - rdmsr_on_cpu(good_cpu, MSR_IA32_PERF_CTL, &oldmsr, &h); - if (msr == (oldmsr & 0xffff)) { + rdmsrq_on_cpu(good_cpu, MSR_IA32_PERF_CTL, &oldmsr.q); + if (msr == (oldmsr.l & 0xffff)) { pr_debug("no change needed - msr was and needs " - "to be %x\n", oldmsr); + "to be %x\n", oldmsr.l); retval = 0; goto out; } first_cpu = 0; /* all but 16 LSB are reserved, treat them with care */ - oldmsr &= ~0xffff; + oldmsr.l &= ~0xffff; msr &= 0xffff; - oldmsr |= msr; + oldmsr.l |= msr; } - wrmsr_on_cpu(good_cpu, MSR_IA32_PERF_CTL, oldmsr, h); + wrmsrq_on_cpu(good_cpu, MSR_IA32_PERF_CTL, oldmsr.q); if (policy->shared_type == CPUFREQ_SHARED_TYPE_ANY) break; @@ -490,7 +491,7 @@ static int centrino_target(struct cpufreq_policy *policy, unsigned int index) */ for_each_cpu(j, covered_cpus) - wrmsr_on_cpu(j, MSR_IA32_PERF_CTL, oldmsr, h); + wrmsrq_on_cpu(j, MSR_IA32_PERF_CTL, oldmsr.q); } retval = 0; diff --git a/drivers/hv/mshv_vtl_main.c b/drivers/hv/mshv_vtl_main.c index c194007..0d3d416 100644 --- a/drivers/hv/mshv_vtl_main.c +++ b/drivers/hv/mshv_vtl_main.c @@ -596,9 +596,9 @@ static int mshv_vtl_get_set_reg(struct hv_register_assoc *regs, bool set) } else { /* Handle MSRs */ if (set) - wrmsrl(reg_table[i].msr_addr, *reg64); + wrmsrq(reg_table[i].msr_addr, *reg64); else - rdmsrl(reg_table[i].msr_addr, *reg64); + rdmsrq(reg_table[i].msr_addr, *reg64); } return 0; } diff --git a/drivers/hwmon/coretemp.c b/drivers/hwmon/coretemp.c index 6a0d947..70711a7 100644 --- a/drivers/hwmon/coretemp.c +++ b/drivers/hwmon/coretemp.c @@ -169,7 +169,7 @@ static int adjust_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev) int tjmax_ee = 85000; int usemsr_ee = 1; int err; - u32 eax, edx; + u64 val; int i; u16 devfn = PCI_DEVFN(0, 0); struct pci_dev *host_bridge = pci_get_domain_bus_and_slot(0, 0, devfn); @@ -220,14 +220,14 @@ static int adjust_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev) * http://softwarecommunity.intel.com/Wiki/Mobility/720.htm * For Core2 cores, check MSR 0x17, bit 28 1 = Mobile CPU */ - err = rdmsr_safe_on_cpu(id, 0x17, &eax, &edx); + err = rdmsrq_safe_on_cpu(id, 0x17, &val); if (err) { dev_warn(dev, "Unable to access MSR 0x17, assuming desktop" " CPU\n"); usemsr_ee = 0; } else if (c->x86_vfm < INTEL_CORE2_PENRYN && - !(eax & 0x10000000)) { + !(val & 0x10000000)) { /* * Trust bit 28 up to Penryn, I could not find any * documentation on that; if you happen to know @@ -235,8 +235,8 @@ static int adjust_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev) */ usemsr_ee = 0; } else { - /* Platform ID bits 52:50 (EDX starts at bit 32) */ - platform_id = (edx >> 18) & 0x7; + /* Platform ID bits 52:50 */ + platform_id = (val >> 50) & 0x7; /* * Mobile Penryn CPU seems to be platform ID 7 or 5 @@ -255,12 +255,12 @@ static int adjust_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev) } if (usemsr_ee) { - err = rdmsr_safe_on_cpu(id, 0xee, &eax, &edx); + err = rdmsrq_safe_on_cpu(id, 0xee, &val); if (err) { dev_warn(dev, "Unable to access MSR 0xEE, for Tjmax, left" " at default\n"); - } else if (eax & 0x40000000) { + } else if (val & 0x40000000) { tjmax = tjmax_ee; } } else if (tjmax == 100000) { @@ -278,7 +278,7 @@ static int get_tjmax(struct temp_data *tdata, struct device *dev) { struct cpuinfo_x86 *c = &cpu_data(tdata->cpu); int err; - u32 eax, edx; + u64 msrval; u32 val; /* use static tjmax once it is set */ @@ -289,11 +289,11 @@ static int get_tjmax(struct temp_data *tdata, struct device *dev) * A new feature of current Intel(R) processors, the * IA32_TEMPERATURE_TARGET contains the TjMax value */ - err = rdmsr_safe_on_cpu(tdata->cpu, MSR_IA32_TEMPERATURE_TARGET, &eax, &edx); + err = rdmsrq_safe_on_cpu(tdata->cpu, MSR_IA32_TEMPERATURE_TARGET, &msrval); if (err) { dev_warn_once(dev, "Unable to read TjMax from CPU %u\n", tdata->cpu); } else { - val = (eax >> 16) & 0xff; + val = (msrval >> 16) & 0xff; if (val) return val * 1000; } @@ -314,7 +314,7 @@ static int get_tjmax(struct temp_data *tdata, struct device *dev) static int get_ttarget(struct temp_data *tdata, struct device *dev) { - u32 eax, edx; + u64 val; int tjmax, ttarget_offset, ret; /* @@ -324,14 +324,14 @@ static int get_ttarget(struct temp_data *tdata, struct device *dev) if (tdata->tjmax) return -ENODEV; - ret = rdmsr_safe_on_cpu(tdata->cpu, MSR_IA32_TEMPERATURE_TARGET, &eax, &edx); + ret = rdmsrq_safe_on_cpu(tdata->cpu, MSR_IA32_TEMPERATURE_TARGET, &val); if (ret) return ret; - tjmax = (eax >> 16) & 0xff; + tjmax = (val >> 16) & 0xff; /* Read the still undocumented bits 8:15 of IA32_TEMPERATURE_TARGET. */ - ttarget_offset = (eax >> 8) & 0xff; + ttarget_offset = (val >> 8) & 0xff; return (tjmax - ttarget_offset) * 1000; } @@ -356,15 +356,15 @@ static ssize_t show_label(struct device *dev, static ssize_t show_crit_alarm(struct device *dev, struct device_attribute *devattr, char *buf) { - u32 eax, edx; + struct msr val; struct temp_data *tdata = container_of(devattr, struct temp_data, sd_attrs[ATTR_CRIT_ALARM]); mutex_lock(&tdata->update_lock); - rdmsr_on_cpu(tdata->cpu, tdata->status_reg, &eax, &edx); + rdmsrq_on_cpu(tdata->cpu, tdata->status_reg, &val.q); mutex_unlock(&tdata->update_lock); - return sprintf(buf, "%d\n", (eax >> 5) & 1); + return sprintf(buf, "%d\n", (val.l >> 5) & 1); } static ssize_t show_tjmax(struct device *dev, @@ -398,7 +398,7 @@ static ssize_t show_ttarget(struct device *dev, static ssize_t show_temp(struct device *dev, struct device_attribute *devattr, char *buf) { - u32 eax, edx; + struct msr val; struct temp_data *tdata = container_of(devattr, struct temp_data, sd_attrs[ATTR_TEMP]); int tjmax; @@ -407,14 +407,14 @@ static ssize_t show_temp(struct device *dev, tjmax = get_tjmax(tdata, dev); /* Check whether the time interval has elapsed */ if (time_after(jiffies, tdata->last_updated + HZ)) { - rdmsr_on_cpu(tdata->cpu, tdata->status_reg, &eax, &edx); + rdmsrq_on_cpu(tdata->cpu, tdata->status_reg, &val.q); /* * Ignore the valid bit. In all observed cases the register * value is either low or zero if the valid bit is 0. * Return it instead of reporting an error which doesn't * really help at all. */ - tdata->temp = tjmax - ((eax >> 16) & 0xff) * 1000; + tdata->temp = tjmax - ((val.l >> 16) & 0xff) * 1000; tdata->last_updated = jiffies; } @@ -560,7 +560,7 @@ static int create_core_data(struct platform_device *pdev, unsigned int cpu, struct temp_data *tdata; struct platform_data *pdata = platform_get_drvdata(pdev); struct cpuinfo_x86 *c = &cpu_data(cpu); - u32 eax, edx; + u64 val; int err; if (!housekeeping_cpu(cpu, HK_TYPE_MISC)) @@ -571,7 +571,7 @@ static int create_core_data(struct platform_device *pdev, unsigned int cpu, return -ENOMEM; /* Test if we can access the status register */ - err = rdmsr_safe_on_cpu(cpu, tdata->status_reg, &eax, &edx); + err = rdmsrq_safe_on_cpu(cpu, tdata->status_reg, &val); if (err) goto err; diff --git a/drivers/hwmon/via-cputemp.c b/drivers/hwmon/via-cputemp.c index a5c03ed..ec42120 100644 --- a/drivers/hwmon/via-cputemp.c +++ b/drivers/hwmon/via-cputemp.c @@ -65,28 +65,28 @@ static ssize_t temp_show(struct device *dev, struct device_attribute *devattr, char *buf) { struct via_cputemp_data *data = dev_get_drvdata(dev); - u32 eax, edx; + u64 val; int err; - err = rdmsr_safe_on_cpu(data->id, data->msr_temp, &eax, &edx); + err = rdmsrq_safe_on_cpu(data->id, data->msr_temp, &val); if (err) return -EAGAIN; - return sprintf(buf, "%lu\n", ((unsigned long)eax & 0xffffff) * 1000); + return sprintf(buf, "%lu\n", ((unsigned long)val & 0xffffff) * 1000); } static ssize_t cpu0_vid_show(struct device *dev, struct device_attribute *devattr, char *buf) { struct via_cputemp_data *data = dev_get_drvdata(dev); - u32 eax, edx; + u64 val; int err; - err = rdmsr_safe_on_cpu(data->id, data->msr_vid, &eax, &edx); + err = rdmsrq_safe_on_cpu(data->id, data->msr_vid, &val); if (err) return -EAGAIN; - return sprintf(buf, "%d\n", vid_from_reg(~edx & 0x7f, data->vrm)); + return sprintf(buf, "%d\n", vid_from_reg(~(val >> 32) & 0x7f, data->vrm)); } static SENSOR_DEVICE_ATTR_RO(temp1_input, temp, SHOW_TEMP); @@ -112,7 +112,7 @@ static int via_cputemp_probe(struct platform_device *pdev) struct via_cputemp_data *data; struct cpuinfo_x86 *c = &cpu_data(pdev->id); int err; - u32 eax, edx; + u64 val; data = devm_kzalloc(&pdev->dev, sizeof(struct via_cputemp_data), GFP_KERNEL); @@ -143,7 +143,7 @@ static int via_cputemp_probe(struct platform_device *pdev) } /* test if we can access the TEMPERATURE MSR */ - err = rdmsr_safe_on_cpu(data->id, data->msr_temp, &eax, &edx); + err = rdmsrq_safe_on_cpu(data->id, data->msr_temp, &val); if (err) { dev_err(&pdev->dev, "Unable to access TEMPERATURE MSR, giving up\n"); diff --git a/drivers/idle/intel_idle.c b/drivers/idle/intel_idle.c index b2705d7..d74b478 100644 --- a/drivers/idle/intel_idle.c +++ b/drivers/idle/intel_idle.c @@ -2428,7 +2428,7 @@ static void intel_c1_demotion_toggle(void *enable) { unsigned long long msr_val; - rdmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr_val); + rdmsrq(MSR_PKG_CST_CONFIG_CONTROL, msr_val); /* * Enable/disable C1 undemotion along with C1 demotion, as this is the * most sensible configuration in general. @@ -2437,7 +2437,7 @@ static void intel_c1_demotion_toggle(void *enable) msr_val |= NHM_C1_AUTO_DEMOTE | SNB_C1_AUTO_UNDEMOTE; else msr_val &= ~(NHM_C1_AUTO_DEMOTE | SNB_C1_AUTO_UNDEMOTE); - wrmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr_val); + wrmsrq(MSR_PKG_CST_CONFIG_CONTROL, msr_val); } static ssize_t intel_c1_demotion_store(struct device *dev, @@ -2468,7 +2468,7 @@ static ssize_t intel_c1_demotion_show(struct device *dev, * Read the MSR value for a CPU and assume it is the same for all CPUs. Any other * configuration would be a BIOS bug. */ - rdmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr_val); + rdmsrq(MSR_PKG_CST_CONFIG_CONTROL, msr_val); return sysfs_emit(buf, "%d\n", !!(msr_val & NHM_C1_AUTO_DEMOTE)); } static DEVICE_ATTR_RW(intel_c1_demotion); diff --git a/drivers/thermal/intel/intel_tcc.c b/drivers/thermal/intel/intel_tcc.c index ab61fb1..59f70bb 100644 --- a/drivers/thermal/intel/intel_tcc.c +++ b/drivers/thermal/intel/intel_tcc.c @@ -181,17 +181,17 @@ static u32 get_temp_mask(bool pkg) */ int intel_tcc_get_tjmax(int cpu) { - u32 low, high; + struct msr msrval; int val, err; if (cpu < 0) - err = rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &low, &high); + err = rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &msrval.l, &msrval.h); else - err = rdmsr_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, &low, &high); + err = rdmsrq_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, &msrval.q); if (err) return err; - val = (low >> 16) & 0xff; + val = (msrval.l >> 16) & 0xff; return val ? val : -ENODATA; } @@ -208,17 +208,17 @@ EXPORT_SYMBOL_NS_GPL(intel_tcc_get_tjmax, "INTEL_TCC"); */ int intel_tcc_get_offset(int cpu) { - u32 low, high; + struct msr val; int err; if (cpu < 0) - err = rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &low, &high); + err = rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &val.l, &val.h); else - err = rdmsr_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, &low, &high); + err = rdmsrq_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, &val.q); if (err) return err; - return (low >> 24) & intel_tcc_temp_masks.tcc_offset; + return (val.l >> 24) & intel_tcc_temp_masks.tcc_offset; } EXPORT_SYMBOL_NS_GPL(intel_tcc_get_offset, "INTEL_TCC"); @@ -235,7 +235,7 @@ EXPORT_SYMBOL_NS_GPL(intel_tcc_get_offset, "INTEL_TCC"); int intel_tcc_set_offset(int cpu, int offset) { - u32 low, high; + struct msr val; int err; if (!intel_tcc_temp_masks.tcc_offset) @@ -245,23 +245,23 @@ int intel_tcc_set_offset(int cpu, int offset) return -EINVAL; if (cpu < 0) - err = rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &low, &high); + err = rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &val.l, &val.h); else - err = rdmsr_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, &low, &high); + err = rdmsrq_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, &val.q); if (err) return err; /* MSR Locked */ - if (low & BIT(31)) + if (val.l & BIT(31)) return -EPERM; - low &= ~(intel_tcc_temp_masks.tcc_offset << 24); - low |= offset << 24; + val.l &= ~(intel_tcc_temp_masks.tcc_offset << 24); + val.l |= offset << 24; if (cpu < 0) - return wrmsr_safe(MSR_IA32_TEMPERATURE_TARGET, low, high); + return wrmsr_safe(MSR_IA32_TEMPERATURE_TARGET, val.l, val.h); else - return wrmsr_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, low, high); + return wrmsrq_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, val.q); } EXPORT_SYMBOL_NS_GPL(intel_tcc_set_offset, "INTEL_TCC"); @@ -279,7 +279,8 @@ EXPORT_SYMBOL_NS_GPL(intel_tcc_set_offset, "INTEL_TCC"); int intel_tcc_get_temp(int cpu, int *temp, bool pkg) { u32 msr = pkg ? MSR_IA32_PACKAGE_THERM_STATUS : MSR_IA32_THERM_STATUS; - u32 low, high, mask; + u32 mask; + struct msr val; int tjmax, err; tjmax = intel_tcc_get_tjmax(cpu); @@ -287,19 +288,19 @@ int intel_tcc_get_temp(int cpu, int *temp, bool pkg) return tjmax; if (cpu < 0) - err = rdmsr_safe(msr, &low, &high); + err = rdmsr_safe(msr, &val.l, &val.h); else - err = rdmsr_safe_on_cpu(cpu, msr, &low, &high); + err = rdmsrq_safe_on_cpu(cpu, msr, &val.q); if (err) return err; /* Temperature is beyond the valid thermal sensor range */ - if (!(low & BIT(31))) + if (!(val.l & BIT(31))) return -ENODATA; mask = get_temp_mask(pkg); - *temp = tjmax - ((low >> 16) & mask); + *temp = tjmax - ((val.l >> 16) & mask); return 0; } diff --git a/drivers/thermal/intel/x86_pkg_temp_thermal.c b/drivers/thermal/intel/x86_pkg_temp_thermal.c index 5401097..144603c 100644 --- a/drivers/thermal/intel/x86_pkg_temp_thermal.c +++ b/drivers/thermal/intel/x86_pkg_temp_thermal.c @@ -125,8 +125,9 @@ sys_set_trip_temp(struct thermal_zone_device *tzd, { struct zone_device *zonedev = thermal_zone_device_priv(tzd); unsigned int trip_index = THERMAL_TRIP_PRIV_TO_INT(trip->priv); - u32 l, h, mask, shift, intr; + u32 mask, shift, intr; int tj_max, val, ret; + struct msr v; if (temp == THERMAL_TEMP_INVALID) temp = 0; @@ -141,8 +142,7 @@ sys_set_trip_temp(struct thermal_zone_device *tzd, if (trip_index >= MAX_NUMBER_OF_TRIPS || val < 0 || val > 0x7f) return -EINVAL; - ret = rdmsr_on_cpu(zonedev->cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, - &l, &h); + ret = rdmsrq_on_cpu(zonedev->cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, &v.q); if (ret < 0) return ret; @@ -155,20 +155,19 @@ sys_set_trip_temp(struct thermal_zone_device *tzd, shift = THERM_SHIFT_THRESHOLD0; intr = THERM_INT_THRESHOLD0_ENABLE; } - l &= ~mask; + v.l &= ~mask; /* * When users space sets a trip temperature == 0, which is indication * that, it is no longer interested in receiving notifications. */ if (!temp) { - l &= ~intr; + v.l &= ~intr; } else { - l |= val << shift; - l |= intr; + v.l |= val << shift; + v.l |= intr; } - return wrmsr_on_cpu(zonedev->cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, - l, h); + return wrmsrq_on_cpu(zonedev->cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, v.q); } /* Thermal zone callback registry */ @@ -277,7 +276,8 @@ static int pkg_temp_thermal_trips_init(int cpu, int tj_max, struct thermal_trip *trips, int num_trips) { unsigned long thres_reg_value; - u32 mask, shift, eax, edx; + u32 mask, shift; + struct msr val; int ret, i; for (i = 0; i < num_trips; i++) { @@ -290,12 +290,11 @@ static int pkg_temp_thermal_trips_init(int cpu, int tj_max, shift = THERM_SHIFT_THRESHOLD0; } - ret = rdmsr_on_cpu(cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, - &eax, &edx); + ret = rdmsrq_on_cpu(cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, &val.q); if (ret < 0) return ret; - thres_reg_value = (eax & mask) >> shift; + thres_reg_value = (val.l & mask) >> shift; trips[i].temperature = thres_reg_value ? tj_max - thres_reg_value * 1000 : THERMAL_TEMP_INVALID;