Merge tag 'mailbox-v5.11' of git://git.linaro.org/landing-teams/working/fujitsu/integration
Merge commit. Changes below are compared with the first parent: 74f602dc.
Changes
8 files changed · +1391 −11
| File | Status | Add | Del | Content |
|---|---|---|---|---|
| Documentation/devicetree/bindings/mailbox/arm,mhuv2.yaml | added | +209 | −0 | View file |
| MAINTAINERS | modified | +9 | −0 | View file |
| drivers/mailbox/Kconfig | modified | +8 | −1 | View file |
| drivers/mailbox/Makefile | modified | +2 | −0 | View file |
| drivers/mailbox/arm_mhu_db.c | modified | +1 | −1 | View file |
| drivers/mailbox/arm_mhuv2.c | added | +1136 | −0 | View file |
| drivers/mailbox/stm32-ipcc.c | modified | +6 | −9 | View file |
| include/linux/mailbox/arm_mhuv2_message.h | added | +20 | −0 | View file |
Only the first 600 diff lines are shown. Download the complete patch.
Documentation/devicetree/bindings/mailbox/arm,mhuv2.yaml
View filediff --git a/Documentation/devicetree/bindings/mailbox/arm,mhuv2.yaml b/Documentation/devicetree/bindings/mailbox/arm,mhuv2.yaml
new file mode 100644
index 0000000..6608545
--- /dev/null
+++ b/Documentation/devicetree/bindings/mailbox/arm,mhuv2.yaml
@@ -0,0 +1,209 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mailbox/arm,mhuv2.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM MHUv2 Mailbox Controller
+
+maintainers:
+ - Tushar Khandelwal <[email protected]>
+ - Viresh Kumar <[email protected]>
+
+description: |
+ The Arm Message Handling Unit (MHU) Version 2 is a mailbox controller that has
+ between 1 and 124 channel windows (each 32-bit wide) to provide unidirectional
+ communication with remote processor(s), where the number of channel windows
+ are implementation dependent.
+
+ Given the unidirectional nature of the controller, an MHUv2 mailbox may only
+ be written to or read from. If a pair of MHU controllers is implemented
+ between two processing elements to provide bidirectional communication, these
+ must be specified as two separate mailboxes.
+
+ If the interrupts property is present in device tree node, then its treated as
+ a "receiver" mailbox, otherwise a "sender".
+
+ An MHU controller must be specified along with the supported transport
+ protocols. The transport protocols determine the method of data transmission
+ as well as the number of provided mailbox channels.
+
+ Following are the possible transport protocols.
+
+ - Data-transfer: Each transfer is made of one or more words, using one or more
+ channel windows.
+
+ - Doorbell: Each transfer is made up of single bit flag, using any one of the
+ bits in a channel window. A channel window can support up to 32 doorbells
+ and the entire window shall be used in doorbell protocol. Optionally, data
+ may be transmitted through a shared memory region, wherein the MHU is used
+ strictly as an interrupt generation mechanism but that is out of the scope
+ of these bindings.
+
+# We need a select here so we don't match all nodes with 'arm,primecell'
+select:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - arm,mhuv2-tx
+ - arm,mhuv2-rx
+ required:
+ - compatible
+
+properties:
+ compatible:
+ oneOf:
+ - description: Sender mode
+ items:
+ - const: arm,mhuv2-tx
+ - const: arm,primecell
+
+ - description: Receiver-mode
+ items:
+ - const: arm,mhuv2-rx
+ - const: arm,primecell
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ description: |
+ The MHUv2 controller always implements an interrupt in the "receiver"
+ mode, while the interrupt in the "sender" mode was not available in the
+ version MHUv2.0, but the later versions do have it.
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ maxItems: 1
+
+ arm,mhuv2-protocols:
+ $ref: /schemas/types.yaml#/definitions/uint32-matrix
+ description: |
+ The MHUv2 controller may contain up to 124 channel windows (each 32-bit
+ wide). The hardware and the DT bindings allows any combination of those to
+ be used for various transport protocols.
+
+ This property allows a platform to describe how these channel windows are
+ used in various transport protocols. The entries in this property shall be
+ present as an array of tuples, where each tuple describes details about
+ one of the transport protocol being implemented over some channel
+ window(s).
+
+ The first field of a tuple signifies the transfer protocol, 0 is reserved
+ for doorbell protocol, and 1 is reserved for data-transfer protocol.
+ Using any other value in the first field of a tuple makes it invalid.
+
+ The second field of a tuple signifies the number of channel windows where
+ the protocol would be used and should be set to a non zero value. For
+ doorbell protocol this field signifies the number of 32-bit channel
+ windows that implement the doorbell protocol. For data-transfer protocol,
+ this field signifies the number of 32-bit channel windows that implement
+ the data-transfer protocol.
+
+ The total number of channel windows specified here shouldn't be more than
+ the ones implemented by the platform, though one can specify lesser number
+ of windows here than what the platform implements.
+
+ mhu: mailbox@2b1f0000 {
+ ...
+
+ arm,mhuv2-protocols = <0 2>, <1 1>, <1 5>, <1 7>;
+ }
+
+ The above example defines the protocols of an ARM MHUv2 mailbox
+ controller, where a total of 15 channel windows are used. The first two
+ windows are used in doorbell protocol (64 doorbells), followed by 1, 5 and
+ 7 windows (separately) used in data-transfer protocol.
+
+ minItems: 1
+ maxItems: 124
+ items:
+ items:
+ - enum: [ 0, 1 ]
+ - minimum: 0
+ maximum: 124
+
+
+ '#mbox-cells':
+ description: |
+ It is always set to 2. The first argument in the consumers 'mboxes'
+ property represents the channel window group, which may be used in
+ doorbell, or data-transfer protocol, and the second argument (only
+ relevant in doorbell protocol, should be 0 otherwise) represents the
+ doorbell number within the 32 bit wide channel window.
+
+ From the example given above for arm,mhuv2-protocols, here is how a client
+ node can reference them.
+
+ mboxes = <&mhu 0 5>; // Channel Window Group 0, doorbell 5.
+ mboxes = <&mhu 1 7>; // Channel Window Group 1, doorbell 7.
+ mboxes = <&mhu 2 0>; // Channel Window Group 2, data transfer protocol with 1 window.
+ mboxes = <&mhu 3 0>; // Channel Window Group 3, data transfer protocol with 5 windows.
+ mboxes = <&mhu 4 0>; // Channel Window Group 4, data transfer protocol with 7 windows.
+
+ const: 2
+
+if:
+ # Interrupt is compulsory for receiver
+ properties:
+ compatible:
+ contains:
+ const: arm,mhuv2-rx
+then:
+ required:
+ - interrupts
+
+required:
+ - compatible
+ - reg
+ - '#mbox-cells'
+ - arm,mhuv2-protocols
+
+additionalProperties: false
+
+examples:
+ # Multiple transport protocols implemented by the mailbox controllers
+ - |
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ mhu_tx: mailbox@2b1f0000 {
+ #mbox-cells = <2>;
+ compatible = "arm,mhuv2-tx", "arm,primecell";
+ reg = <0 0x2b1f0000 0 0x1000>;
+ clocks = <&clock 0>;
+ clock-names = "apb_pclk";
+ interrupts = <0 45 4>;
+ arm,mhuv2-protocols = <1 5>, <1 2>, <1 5>, <1 7>, <0 2>;
+ };
+
+ mhu_rx: mailbox@2b1f1000 {
+ #mbox-cells = <2>;
+ compatible = "arm,mhuv2-rx", "arm,primecell";
+ reg = <0 0x2b1f1000 0 0x1000>;
+ clocks = <&clock 0>;
+ clock-names = "apb_pclk";
+ interrupts = <0 46 4>;
+ arm,mhuv2-protocols = <1 1>, <1 7>, <0 2>;
+ };
+
+ mhu_client: scb@2e000000 {
+ compatible = "fujitsu,mb86s70-scb-1.0";
+ reg = <0 0x2e000000 0 0x4000>;
+
+ mboxes =
+ //data-transfer protocol with 5 windows, mhu-tx
+ <&mhu_tx 2 0>,
+ //data-transfer protocol with 7 windows, mhu-tx
+ <&mhu_tx 3 0>,
+ //doorbell protocol channel 4, doorbell 27, mhu-tx
+ <&mhu_tx 4 27>,
+ //data-transfer protocol with 1 window, mhu-rx
+ <&mhu_rx 0 0>;
+ };
+ };
MAINTAINERS
View filediff --git a/MAINTAINERS b/MAINTAINERS
index b35b04a..4654ce8 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -10524,6 +10524,15 @@ F: drivers/mailbox/
F: include/linux/mailbox_client.h
F: include/linux/mailbox_controller.h
+MAILBOX ARM MHUv2
+M: Viresh Kumar <[email protected]>
+M: Tushar Khandelwal <[email protected]>
+S: Maintained
+F: drivers/mailbox/arm_mhuv2.c
+F: include/linux/mailbox/arm_mhuv2_message.h
+F: Documentation/devicetree/bindings/mailbox/arm,mhuv2.yaml
+
MAN-PAGES: MANUAL PAGES FOR LINUX -- Sections 2, 3, 4, 5, and 7
M: Michael Kerrisk <[email protected]>
drivers/mailbox/Kconfig
View filediff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig
index 05b1009..f4abe35 100644
--- a/drivers/mailbox/Kconfig
+++ b/drivers/mailbox/Kconfig
@@ -16,6 +16,13 @@ config ARM_MHU
The controller has 3 mailbox channels, the last of which can be
used in Secure mode only.
+config ARM_MHU_V2
+ tristate "ARM MHUv2 Mailbox"
+ depends on ARM_AMBA
+ help
+ Say Y here if you want to build the ARM MHUv2 controller driver,
+ which provides unidirectional mailboxes between processing elements.
+
config IMX_MBOX
tristate "i.MX Mailbox"
depends on ARCH_MXC || COMPILE_TEST
@@ -201,7 +208,7 @@ config BCM_FLEXRM_MBOX
config STM32_IPCC
tristate "STM32 IPCC Mailbox"
- depends on MACH_STM32MP157
+ depends on MACH_STM32MP157 || COMPILE_TEST
help
Mailbox implementation for STMicroelectonics STM32 family chips
with hardware for Inter-Processor Communication Controller (IPCC)
drivers/mailbox/Makefile
View filediff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile
index 2e06e02..7194fa9 100644
--- a/drivers/mailbox/Makefile
+++ b/drivers/mailbox/Makefile
@@ -7,6 +7,8 @@ obj-$(CONFIG_MAILBOX_TEST) += mailbox-test.o
obj-$(CONFIG_ARM_MHU) += arm_mhu.o arm_mhu_db.o
+obj-$(CONFIG_ARM_MHU_V2) += arm_mhuv2.o
+
obj-$(CONFIG_IMX_MBOX) += imx-mailbox.o
obj-$(CONFIG_ARMADA_37XX_RWTM_MBOX) += armada-37xx-rwtm-mailbox.o
drivers/mailbox/arm_mhu_db.c
View filediff --git a/drivers/mailbox/arm_mhu_db.c b/drivers/mailbox/arm_mhu_db.c
index 275efe4..8eb66c4 100644
--- a/drivers/mailbox/arm_mhu_db.c
+++ b/drivers/mailbox/arm_mhu_db.c
@@ -180,7 +180,7 @@ static void mhu_db_shutdown(struct mbox_chan *chan)
/* Reset channel */
mhu_db_mbox_clear_irq(chan);
- kfree(chan->con_priv);
+ devm_kfree(mbox->dev, chan->con_priv);
chan->con_priv = NULL;
}
drivers/mailbox/arm_mhuv2.c
View filediff --git a/drivers/mailbox/arm_mhuv2.c b/drivers/mailbox/arm_mhuv2.c
new file mode 100644
index 0000000..67fb108
--- /dev/null
+++ b/drivers/mailbox/arm_mhuv2.c
@@ -0,0 +1,1136 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ARM Message Handling Unit Version 2 (MHUv2) driver.
+ *
+ * Copyright (C) 2020 ARM Ltd.
+ * Copyright (C) 2020 Linaro Ltd.
+ *
+ * An MHUv2 mailbox controller can provide up to 124 channel windows (each 32
+ * bit long) and the driver allows any combination of both the transport
+ * protocol modes: data-transfer and doorbell, to be used on those channel
+ * windows.
+ *
+ * The transport protocols should be specified in the device tree entry for the
+ * device. The transport protocols determine how the underlying hardware
+ * resources of the device are utilized when transmitting data. Refer to the
+ * device tree bindings of the ARM MHUv2 controller for more details.
+ *
+ * The number of registered mailbox channels is dependent on both the underlying
+ * hardware - mainly the number of channel windows implemented by the platform,
+ * as well as the selected transport protocols.
+ *
+ * The MHUv2 controller can work both as a sender and receiver, but the driver
+ * and the DT bindings support unidirectional transfers for better allocation of
+ * the channels. That is, this driver will be probed for two separate devices
+ * for each mailbox controller, a sender device and a receiver device.
+ */
+
+#include <linux/amba/bus.h>
+#include <linux/interrupt.h>
+#include <linux/mailbox_controller.h>
+#include <linux/mailbox/arm_mhuv2_message.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/spinlock.h>
+
+/* ====== MHUv2 Registers ====== */
+
+/* Maximum number of channel windows */
+#define MHUV2_CH_WN_MAX 124
+/* Number of combined interrupt status registers */
+#define MHUV2_CMB_INT_ST_REG_CNT 4
+#define MHUV2_STAT_BYTES (sizeof(u32))
+#define MHUV2_STAT_BITS (MHUV2_STAT_BYTES * __CHAR_BIT__)
+
+#define LSB_MASK(n) ((1 << (n * __CHAR_BIT__)) - 1)
+#define MHUV2_PROTOCOL_PROP "arm,mhuv2-protocols"
+
+/* Register Message Handling Unit Configuration fields */
+struct mhu_cfg_t {
+ u32 num_ch : 7;
+ u32 pad : 25;
+} __packed;
+
+/* register Interrupt Status fields */
+struct int_st_t {
+ u32 nr2r : 1;
+ u32 r2nr : 1;
+ u32 pad : 30;
+} __packed;
+
+/* Register Interrupt Clear fields */
+struct int_clr_t {
+ u32 nr2r : 1;
+ u32 r2nr : 1;
+ u32 pad : 30;
+} __packed;
+
+/* Register Interrupt Enable fields */
+struct int_en_t {
+ u32 r2nr : 1;
+ u32 nr2r : 1;
+ u32 chcomb : 1;
+ u32 pad : 29;
+} __packed;
+
+/* Register Implementer Identification fields */
+struct iidr_t {
+ u32 implementer : 12;
+ u32 revision : 4;
+ u32 variant : 4;
+ u32 product_id : 12;
+} __packed;
+
+/* Register Architecture Identification Register fields */
+struct aidr_t {
+ u32 arch_minor_rev : 4;
+ u32 arch_major_rev : 4;
+ u32 pad : 24;
+} __packed;
+
+/* Sender Channel Window fields */
+struct mhu2_send_ch_wn_reg {
+ u32 stat;
+ u8 pad1[0x0C - 0x04];
+ u32 stat_set;
+ u32 int_st;
+ u32 int_clr;
+ u32 int_en;
+ u8 pad2[0x20 - 0x1C];
+} __packed;
+
+/* Sender frame register fields */
+struct mhu2_send_frame_reg {
+ struct mhu2_send_ch_wn_reg ch_wn[MHUV2_CH_WN_MAX];
+ struct mhu_cfg_t mhu_cfg;
+ u32 resp_cfg;
+ u32 access_request;
+ u32 access_ready;
+ struct int_st_t int_st;
+ struct int_clr_t int_clr;
+ struct int_en_t int_en;
+ u32 reserved0;
+ u32 chcomb_int_st[MHUV2_CMB_INT_ST_REG_CNT];
+ u8 pad[0xFC8 - 0xFB0];
+ struct iidr_t iidr;
+ struct aidr_t aidr;
+} __packed;
+
+/* Receiver Channel Window fields */
+struct mhu2_recv_ch_wn_reg {
+ u32 stat;
+ u32 stat_masked;
+ u32 stat_clear;
+ u8 reserved0[0x10 - 0x0C];
+ u32 mask;
+ u32 mask_set;
+ u32 mask_clear;
+ u8 pad[0x20 - 0x1C];
+} __packed;
+
+/* Receiver frame register fields */
+struct mhu2_recv_frame_reg {
+ struct mhu2_recv_ch_wn_reg ch_wn[MHUV2_CH_WN_MAX];
+ struct mhu_cfg_t mhu_cfg;
+ u8 reserved0[0xF90 - 0xF84];
+ struct int_st_t int_st;
+ struct int_clr_t int_clr;
+ struct int_en_t int_en;
+ u32 pad;
+ u32 chcomb_int_st[MHUV2_CMB_INT_ST_REG_CNT];
+ u8 reserved2[0xFC8 - 0xFB0];
+ struct iidr_t iidr;
+ struct aidr_t aidr;
+} __packed;
+
+
+/* ====== MHUv2 data structures ====== */
+
+enum mhuv2_transport_protocol {
+ DOORBELL = 0,
+ DATA_TRANSFER = 1
+};
+
+enum mhuv2_frame {
+ RECEIVER_FRAME,
+ SENDER_FRAME
+};
+
+/**
+ * struct mhuv2 - MHUv2 mailbox controller data
+ *
+ * @mbox: Mailbox controller belonging to the MHU frame.
+ * @send/recv: Base address of the register mapping region.
+ * @frame: Frame type: RECEIVER_FRAME or SENDER_FRAME.
+ * @irq: Interrupt.
+ * @windows: Channel windows implemented by the platform.
+ * @minor: Minor version of the controller.
+ * @length: Length of the protocols array in bytes.
+ * @protocols: Raw protocol information, derived from device tree.
+ * @doorbell_pending_lock: spinlock required for correct operation of Tx
+ * interrupt for doorbells.
+ */
+struct mhuv2 {
+ struct mbox_controller mbox;
+ union {
+ struct mhu2_send_frame_reg __iomem *send;
+ struct mhu2_recv_frame_reg __iomem *recv;
+ };
+ enum mhuv2_frame frame;
+ unsigned int irq;
+ unsigned int windows;
+ unsigned int minor;
+ unsigned int length;
+ u32 *protocols;
+
+ spinlock_t doorbell_pending_lock;
+};
+
+#define mhu_from_mbox(_mbox) container_of(_mbox, struct mhuv2, mbox)
+
+/**
+ * struct mhuv2_protocol_ops - MHUv2 operations
+ *
+ * Each transport protocol must provide an implementation of the operations
+ * provided here.
+ *
+ * @rx_startup: Startup callback for receiver.
+ * @rx_shutdown: Shutdown callback for receiver.
+ * @read_data: Reads and clears newly available data.
+ * @tx_startup: Startup callback for receiver.
+ * @tx_shutdown: Shutdown callback for receiver.
+ * @last_tx_done: Report back if the last tx is completed or not.
+ * @send_data: Send data to the receiver.
+ */
+struct mhuv2_protocol_ops {
+ int (*rx_startup)(struct mhuv2 *mhu, struct mbox_chan *chan);
+ void (*rx_shutdown)(struct mhuv2 *mhu, struct mbox_chan *chan);
+ void *(*read_data)(struct mhuv2 *mhu, struct mbox_chan *chan);
+
+ void (*tx_startup)(struct mhuv2 *mhu, struct mbox_chan *chan);
+ void (*tx_shutdown)(struct mhuv2 *mhu, struct mbox_chan *chan);
+ int (*last_tx_done)(struct mhuv2 *mhu, struct mbox_chan *chan);
+ int (*send_data)(struct mhuv2 *mhu, struct mbox_chan *chan, void *arg);
+};
+
+/*
+ * MHUv2 mailbox channel's private information
+ *
+ * @ops: protocol specific ops for the channel.
+ * @ch_wn_idx: Channel window index allocated to the channel.
+ * @windows: Total number of windows consumed by the channel, only relevant
+ * in DATA_TRANSFER protocol.
+ * @doorbell: Doorbell bit number within the ch_wn_idx window, only relevant
+ * in DOORBELL protocol.
+ * @pending: Flag indicating pending doorbell interrupt, only relevant in
+ * DOORBELL protocol.
+ */
+struct mhuv2_mbox_chan_priv {
+ const struct mhuv2_protocol_ops *ops;
+ u32 ch_wn_idx;
+ union {
+ u32 windows;
+ struct {
+ u32 doorbell;
+ u32 pending;
+ };
+ };
+};
+
+/* Macro for reading a bitfield within a physically mapped packed struct */
+#define readl_relaxed_bitfield(_regptr, _field) \
+ ({ \
+ u32 _regval; \
+ _regval = readl_relaxed((_regptr)); \
+ (*(typeof((_regptr)))(&_regval))._field; \
+ })
+
+/* Macro for writing a bitfield within a physically mapped packed struct */
+#define writel_relaxed_bitfield(_value, _regptr, _field) \
+ ({ \
+ u32 _regval; \
+ _regval = readl_relaxed(_regptr); \
+ (*(typeof(_regptr))(&_regval))._field = _value; \
+ writel_relaxed(_regval, _regptr); \
+ })
+
+
+/* =================== Doorbell transport protocol operations =============== */
+
+static int mhuv2_doorbell_rx_startup(struct mhuv2 *mhu, struct mbox_chan *chan)
+{
+ struct mhuv2_mbox_chan_priv *priv = chan->con_priv;
+
+ writel_relaxed(BIT(priv->doorbell),
+ &mhu->recv->ch_wn[priv->ch_wn_idx].mask_clear);
+ return 0;
+}
+
+static void mhuv2_doorbell_rx_shutdown(struct mhuv2 *mhu,
+ struct mbox_chan *chan)
+{
+ struct mhuv2_mbox_chan_priv *priv = chan->con_priv;
+
+ writel_relaxed(BIT(priv->doorbell),
+ &mhu->recv->ch_wn[priv->ch_wn_idx].mask_set);
+}
+
+static void *mhuv2_doorbell_read_data(struct mhuv2 *mhu, struct mbox_chan *chan)
+{
+ struct mhuv2_mbox_chan_priv *priv = chan->con_priv;
+
+ writel_relaxed(BIT(priv->doorbell),
+ &mhu->recv->ch_wn[priv->ch_wn_idx].stat_clear);
+ return NULL;
+}
+
+static int mhuv2_doorbell_last_tx_done(struct mhuv2 *mhu,
+ struct mbox_chan *chan)
+{
+ struct mhuv2_mbox_chan_priv *priv = chan->con_priv;
+
+ return !(readl_relaxed(&mhu->send->ch_wn[priv->ch_wn_idx].stat) &
+ BIT(priv->doorbell));
+}
+
+static int mhuv2_doorbell_send_data(struct mhuv2 *mhu, struct mbox_chan *chan,
+ void *arg)
+{
+ struct mhuv2_mbox_chan_priv *priv = chan->con_priv;
+ unsigned long flags;
+
+ spin_lock_irqsave(&mhu->doorbell_pending_lock, flags);
+
+ priv->pending = 1;
+ writel_relaxed(BIT(priv->doorbell),
+ &mhu->send->ch_wn[priv->ch_wn_idx].stat_set);
This diff is incomplete. Download the complete patch.
drivers/mailbox/stm32-ipcc.c
View fileThis diff is incomplete. Download the complete patch.
include/linux/mailbox/arm_mhuv2_message.h
View fileThis diff is incomplete. Download the complete patch.