Merge tag 'edac_urgent_for_v7.3_rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras

a5ebb762 · Linus Torvalds <[email protected]> · 2026-10-10 16:57:30 -07:00

Pull EDAC fix from Borislav Petkov:

 - amd64_edac: Shorten the ErrorInformation field read from the MCA_SYND
   MSR to only two bits. It is perfectly fine to do so because no system
   ever supported more than 2 bits of information (the Chip Selects used
   were only 4 maximum) and newer hardware will use only 2 bits anyway

* tag 'edac_urgent_for_v7.3_rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras:
  EDAC/amd64: Mask UMC chip select to the four implemented selects

Commit: a5ebb76233b79db01e82e061173cb73c6d2b5c6b
Parents: bb934c29 · 7484bc43

Merge commit. Changes below are compared with the first parent: bb934c29.

Changes

1 files changed · +2 −2

File	Status	Add	Del	Content
drivers/edac/amd64_edac.c	modified	+2	−2	View file

drivers/edac/amd64_edac.c

View file

diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index 475235c..0c0d11c 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -2796,13 +2796,13 @@ static inline void decode_bus_error(int node_id, struct mce *m)
  * the instance_id. For example, instance_id=0xYXXXXX where Y is the channel
  * number.
  *
- * For DRAM ECC errors, the Chip Select number is given in bits [2:0] of
+ * For DRAM ECC errors, the Chip Select number is given in bits [1:0] of
  * the MCA_SYND[ErrorInformation] field.
  */
 static void umc_get_err_info(struct mce *m, struct err_info *err)
 {
 	err->channel = (m->ipid & GENMASK(31, 0)) >> 20;
-	err->csrow = m->synd & 0x7;
+	err->csrow = m->synd & 0x3;
 }
 
 static void decode_umc_error(int node_id, struct mce *m)