Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

bdc753c7 · Linus Torvalds <[email protected]> · 2022-10-08 10:06:48 -07:00

Pull clk updates from Stephen Boyd:
 "We have some late breaking reports that a patch series to rework clk
  rate range support broke boot on some devices, so I've left that
  branch out of this. Hopefully we can get to that next week, or punt on
  it and let it bake another cycle. That means we don't really have any
  changes to the core framework this time around besides a few typo
  fixes. Instead this is all clk driver updates and fixes.

  The usual suspects are here (again), with Qualcomm dominating the
  diffstat. We look to have gained support for quite a few new Qualcomm
  SoCs and Dmitry worked on updating many of the existing Qualcomm
  drivers to use clk_parent_data. After that we have MediaTek drivers
  getting some much needed updates, in particular to support GPU DVFS.
  There are also quite a few Samsung clk driver patches, but that's
  mostly because there was a maintainer change and so last release we
  missed some of those patches.

  Overall things look normal, but I'm slowly reviewing core framework
  code nowadays and that shows given the rate range patches had to be
  yanked last minute. Let's hope this situation changes soon.

  New Drivers:
   - Support for Renesas VersaClock7 clock generator family
   - Add Spreadtrum UMS512 SoC clk support
   - New clock drivers for MediaTek Helio X10 MT6795
   - Display clks for Qualcomm SM6115, SM8450
   - GPU clks for Qualcomm SC8280XP
   - Qualcomm MSM8909 and SM6375 global and SMD RPM clk drivers

  Deleted Drivers:
   - Remove DaVinci DM644x and DM646x clk driver support

  Updates:
   - Convert Baikal-T1 CCU driver to platform driver
   - Split reset support out of primary Baikal-T1 CCU driver
   - Add some missing clks required for RPiVid Video Decoder on
     RaspberryPi
   - Mark PLLC critical on bcm2835
   - More devm helpers for fixed rate registration
   - Various PXA168 clk driver fixes
   - Add resets for MediaTek MT8195 PCIe and USB
   - Miscellaneous of_node_put() fixes
   - Nuke dt-bindings/clk path (again) by moving headers to
     dt-bindings/clock
   - Convert gpio-clk-gate binding to YAML
   - Various fixes to AMD/Xilinx Zynqmp clk driver
   - Graduate AMD/Xilinx "clocking wizard" driver from staging
   - Add missing DPI1_HDMI clock in MT8195 VDOSYS1
   - Clock driver changes to support GPU DVFS on MT8183, MT8192, MT8195
   - Fix GPU clock topology on MT8195
   - Propogate rate changes from GPU clock gate up the tree
   - Clock mux notifiers for GPU-related PLLs
   - Conversion of more "simple" drivers to mtk_clk_simple_probe()
   - Hook up mtk_clk_simple_remove() for "simple" MT8192 clock drivers
   - Fixes to previous |struct clk| to |struct clk_hw| conversion on
     MediaTek
   - Shrink MT8192 clock driver by deduplicating clock parent lists
   - Change order between 'sim_enet_root_clk' and 'enet_qos_root_clk'
     clocks for i.MX8MP
   - Drop unnecessary newline in i.MX8MM dt-bindings
   - Add more MU1 and SAI clocks dt-bindings Ids
   - Introduce slice busy bit check for i.MX93 composite clock
   - Introduce white list bit check for i.MX93 composite clock
   - Add new i.MX93 clock gate
   - Add MU1 and MU2 clocks to i.MX93 clock provider
   - Add SAI IPG clocks to i.MX93 clock provider
   - add generic clocks for U(S)ART available on SAMA5D2 SoCs
   - reset controller support for Polarfire clocks
   - .round_rate and .set rate support for clk-mpfs
   - code cleanup for clk-mpfs
   - PLL support for PolarFire SoC's Clock Conditioning Circuitry
   - Add watchdog, I2C, pin control/GPIO, and Ethernet clocks on R-Car
     V4H
   - Add SDHI, Timer (CMT/TMU), and SPI (MSIOF) clocks on R-Car S4-8
   - Add I2C clocks and resets on RZ/V2M
   - Document clock support for the RZ/Five SoC
   - mux-variant clock using the table variant to select parents
   - clock controller for the rv1126 soc
   - conversion of rk3128 to yaml and relicensing of the yaml bindings
     to gpl2+MIT (following dt-binding guildelines)
   - Exynos7885: add FSYS, TREX and MFC clock controllers
   - Exynos850: add IS and AUD (audio) clock controllers with bindings
   - ExynosAutov9: add FSYS clock controllers with bindings
   - ExynosAutov9: correct clock IDs in bindings of Peric 0 and 1 clock
     controllers, due to duplicated entries. This is an acceptable ABI
     break: recently developed/added platform so without legacies, acked
     by known users/developers
   - ExynosAutov9: add few missing Peric 0/1 gates
   - ExynosAutov9: correct register offsets of few Peric 0/1 clocks
   - Minor code improvements (use of_device_get_match_data() helper,
     code style)
   - Add Krzysztof Kozlowski as co-maintainer of Samsung SoC clocks, as
     he already maintainers that architecture/platform
   - Keep Qualcomm GDSCs enabled when PWRSTS_RET flag is there, solving
     retention issues during suspend of USB on Qualcomm sc7180/sc7280
     and SC8280XP
   - Qualcomm SM6115 and QCM2260 are moved to reuse PLL configuration
   - Qualcomm SDM660 SDCC1 moved to floor clk ops
   - Support for the APCS PLLs for Qualcomm IPQ8064, IPQ8074 and IPQ6018
     was added/fixed
   - The Qualcomm MSM8996 CPU clocks are updated with support for ACD
   - Support for Qualcomm SDM670 GCC and RPMh clks was added
   - Transition to parent_data, parent_hws and use of ARRAY_SIZE() for
     num_parents was done for many Qualcomm SoCs
   - Support for per-reset defined delay on Qualcomm was introduced"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (283 commits)
  clk: qcom: gcc-sm6375: Ensure unsigned long type
  clk: qcom: gcc-sm6375: Remove unused variables
  clk: qcom: kpss-xcc: convert to parent data API
  clk: introduce (devm_)hw_register_mux_parent_data_table API
  clk: allow building lan966x as a module
  clk: clk-xgene: simplify if-if to if-else
  clk: ast2600: BCLK comes from EPLL
  clk: clocking-wizard: Depend on HAS_IOMEM
  clk: clocking-wizard: Use dev_err_probe() helper
  clk: nxp: fix typo in comment
  clk: pxa: add a check for the return value of kzalloc()
  clk: vc5: Add support for IDT/Renesas VersaClock 5P49V6975
  dt-bindings: clock: vc5: Add 5P49V6975
  clk: mvebu: armada-37xx-tbg: Remove the unneeded result variable
  clk: ti: dra7-atl: Fix reference leak in of_dra7_atl_clk_probe
  clk: Renesas versaclock7 ccf device driver
  dt-bindings: Renesas versaclock7 device tree bindings
  clk: ti: Balance of_node_get() calls for of_find_node_by_name()
  clk: imx: scu: fix memleak on platform_device_add() fails
  clk: vc5: Use regmap_{set,clear}_bits() where appropriate
  ...

Commit: bdc753c7fcb4eb009ae246a188ea7ac6dac98ce1
Parents: f0160397 · f9efefdb

Merge commit. Changes below are compared with the first parent: f0160397.

Changes

318 files changed · +27677 −4389

File	Status	Add	Del	Content
Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml	modified	+2	−0	View file
Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml	modified	+1	−0	View file
Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml	modified	+1	−0	View file
Documentation/devicetree/bindings/clock/cirrus,cs2000-cp.yaml	modified	+0	−1	View file
Documentation/devicetree/bindings/clock/gpio-gate-clock.txt	deleted	+0	−21	View before deletion
Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml	added	+42	−0	View file
Documentation/devicetree/bindings/clock/idt,versaclock5.yaml	modified	+4	−2	View file
Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml	modified	+1	−0	View file
Documentation/devicetree/bindings/clock/mediatek,mt6795-clock.yaml	added	+66	−0	View file
Documentation/devicetree/bindings/clock/mediatek,mt6795-sys-clock.yaml	added	+54	−0	View file
Documentation/devicetree/bindings/clock/mediatek,mt8365-clock.yaml	added	+42	−0	View file
Documentation/devicetree/bindings/clock/mediatek,mt8365-sys-clock.yaml	added	+47	−0	View file
Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml	modified	+1	−0	View file
Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml	added	+80	−0	View file
Documentation/devicetree/bindings/clock/microchip,mpfs.yaml → Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml	renamed	+16	−3	View file
Documentation/devicetree/bindings/clock/qcom,a53pll.yaml	modified	+2	−1	View file
Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml	modified	+9	−0	View file
Documentation/devicetree/bindings/clock/qcom,gcc-msm8660.yaml	added	+54	−0	View file
Documentation/devicetree/bindings/clock/qcom,gcc-msm8909.yaml	added	+58	−0	View file
Documentation/devicetree/bindings/clock/qcom,gcc-msm8916.yaml	added	+66	−0	View file
Documentation/devicetree/bindings/clock/qcom,gcc-msm8976.yaml	modified	+4	−17	View file
Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml	modified	+4	−17	View file
Documentation/devicetree/bindings/clock/qcom,gcc-msm8996.yaml	modified	+4	−21	View file
Documentation/devicetree/bindings/clock/qcom,gcc-msm8998.yaml	modified	+4	−21	View file
Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml	modified	+0	−7	View file
Documentation/devicetree/bindings/clock/qcom,gcc-qcm2290.yaml	modified	+4	−21	View file
Documentation/devicetree/bindings/clock/qcom,gcc-sc7180.yaml	modified	+4	−21	View file
Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.yaml	modified	+4	−17	View file
Documentation/devicetree/bindings/clock/qcom,gcc-sc8180x.yaml	modified	+4	−21	View file
Documentation/devicetree/bindings/clock/qcom,gcc-sc8280xp.yaml	modified	+6	−19	View file
Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml	modified	+50	−34	View file
Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml	modified	+4	−17	View file
Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml	modified	+4	−17	View file
Documentation/devicetree/bindings/clock/qcom,gcc-sm6115.yaml	modified	+4	−21	View file
Documentation/devicetree/bindings/clock/qcom,gcc-sm6125.yaml	modified	+4	−21	View file
Documentation/devicetree/bindings/clock/qcom,gcc-sm6350.yaml	modified	+4	−21	View file
Documentation/devicetree/bindings/clock/qcom,gcc-sm8150.yaml	modified	+4	−21	View file
Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml	modified	+4	−21	View file
Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml	modified	+4	−17	View file
Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml	modified	+4	−17	View file
Documentation/devicetree/bindings/clock/qcom,gpucc.yaml	modified	+2	−0	View file
Documentation/devicetree/bindings/clock/qcom,mmcc.yaml	modified	+177	−32	View file
Documentation/devicetree/bindings/clock/qcom,msm8996-apcc.yaml	modified	+7	−8	View file
Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml	modified	+2	−0	View file
Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml	modified	+1	−0	View file
Documentation/devicetree/bindings/clock/qcom,sm6115-dispcc.yaml	added	+70	−0	View file
Documentation/devicetree/bindings/clock/qcom,sm6375-gcc.yaml	added	+52	−0	View file
Documentation/devicetree/bindings/clock/qcom,sm8450-dispcc.yaml	added	+98	−0	View file
Documentation/devicetree/bindings/clock/renesas,rcar-usb2-clock-sel.yaml	modified	+0	−2	View file
Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml	modified	+1	−1	View file
Documentation/devicetree/bindings/clock/renesas,versaclock7.yaml	added	+64	−0	View file
Documentation/devicetree/bindings/clock/rockchip,px30-cru.yaml	modified	+1	−1	View file
Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.yaml	modified	+1	−1	View file
Documentation/devicetree/bindings/clock/rockchip,rk3128-cru.txt	deleted	+0	−58	View before deletion
Documentation/devicetree/bindings/clock/rockchip,rk3128-cru.yaml	added	+76	−0	View file
Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.yaml	modified	+1	−1	View file
Documentation/devicetree/bindings/clock/rockchip,rk3288-cru.yaml	modified	+1	−1	View file
Documentation/devicetree/bindings/clock/rockchip,rk3308-cru.yaml	modified	+1	−1	View file
Documentation/devicetree/bindings/clock/rockchip,rk3368-cru.yaml	modified	+1	−1	View file
Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml	modified	+1	−1	View file
Documentation/devicetree/bindings/clock/rockchip,rv1108-cru.yaml	modified	+1	−1	View file
Documentation/devicetree/bindings/clock/rockchip,rv1126-cru.yaml	added	+62	−0	View file
Documentation/devicetree/bindings/clock/samsung,s2mps11.yaml	modified	+0	−1	View file
Documentation/devicetree/bindings/clock/ti/gate.txt	modified	+1	−1	View file
Documentation/devicetree/bindings/clock/ti/interface.txt	modified	+1	−1	View file
Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml	added	+77	−0	View file
Documentation/devicetree/bindings/mfd/cirrus,lochnagar.yaml	modified	+1	−1	View file
MAINTAINERS	modified	+11	−1	View file
arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi	modified	+1	−1	View file
arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi	modified	+1	−1	View file
drivers/clk/Kconfig	modified	+10	−1	View file
drivers/clk/Makefile	modified	+1	−0	View file
drivers/clk/at91/dt-compat.c	modified	+84	−24	View file
drivers/clk/at91/sama5d2.c	modified	+10	−0	View file
drivers/clk/baikal-t1/Kconfig	modified	+11	−1	View file
drivers/clk/baikal-t1/Makefile	modified	+1	−0	View file
drivers/clk/baikal-t1/ccu-div.c	modified	+65	−19	View file
drivers/clk/baikal-t1/ccu-div.h	modified	+14	−3	View file
drivers/clk/baikal-t1/ccu-pll.h	modified	+8	−0	View file
drivers/clk/baikal-t1/ccu-rst.c	added	+217	−0	View file
drivers/clk/baikal-t1/ccu-rst.h	added	+67	−0	View file
drivers/clk/baikal-t1/clk-ccu-div.c	modified	+148	−112	View file
drivers/clk/baikal-t1/clk-ccu-pll.c	modified	+97	−26	View file
drivers/clk/bcm/clk-bcm2835.c	modified	+37	−6	View file
drivers/clk/bcm/clk-raspberrypi.c	modified	+11	−0	View file
drivers/clk/berlin/bg2.c	modified	+4	−1	View file
drivers/clk/berlin/bg2q.c	modified	+5	−1	View file
drivers/clk/clk-asm9260.c	modified	+12	−17	View file
drivers/clk/clk-ast2600.c	modified	+1	−1	View file
drivers/clk/clk-fixed-rate.c	modified	+24	−4	View file
drivers/clk/clk-lan966x.c	modified	+1	−1	View file
drivers/clk/clk-lochnagar.c	modified	+1	−1	View file
drivers/clk/clk-nomadik.c	modified	+4	−1	View file
drivers/clk/clk-npcm7xx.c	modified	+0	−29	View file
drivers/clk/clk-oxnas.c	modified	+4	−2	View file
drivers/clk/clk-qoriq.c	modified	+8	−2	View file
drivers/clk/clk-versaclock5.c	modified	+105	−58	View file
drivers/clk/clk-versaclock7.c	added	+1309	−0	View file
drivers/clk/clk-xgene.c	modified	+2	−2	View file
drivers/clk/clk.c	modified	+2	−29	View file
drivers/clk/clkdev.c	modified	+11	−49	View file
drivers/clk/davinci/Makefile	modified	+0	−4	View file
drivers/clk/davinci/da8xx-cfgchip.c	modified	+1	−2	View file
drivers/clk/davinci/pll-dm644x.c	deleted	+0	−81	View before deletion
drivers/clk/davinci/pll-dm646x.c	deleted	+0	−85	View before deletion
drivers/clk/davinci/pll.c	modified	+1	−9	View file
drivers/clk/davinci/pll.h	modified	+0	−6	View file
drivers/clk/davinci/psc-dm644x.c	deleted	+0	−85	View before deletion
drivers/clk/davinci/psc-dm646x.c	deleted	+0	−82	View before deletion
drivers/clk/davinci/psc.c	modified	+0	−6	View file
drivers/clk/davinci/psc.h	modified	+0	−6	View file
drivers/clk/imx/Makefile	modified	+1	−0	View file
drivers/clk/imx/clk-composite-93.c	modified	+166	−5	View file
drivers/clk/imx/clk-gate-93.c	added	+199	−0	View file
drivers/clk/imx/clk-imx8mp.c	modified	+1	−1	View file
drivers/clk/imx/clk-imx93.c	modified	+20	−10	View file
drivers/clk/imx/clk-scu.c	modified	+5	−1	View file
drivers/clk/imx/clk.h	modified	+7	−2	View file
drivers/clk/mediatek/Kconfig	modified	+87	−0	View file
drivers/clk/mediatek/Makefile	modified	+13	−0	View file
drivers/clk/mediatek/clk-apmixed.c	modified	+11	−1	View file
drivers/clk/mediatek/clk-cpumux.c	modified	+2	−0	View file
drivers/clk/mediatek/clk-gate.c	modified	+1	−0	View file
drivers/clk/mediatek/clk-mt2701-bdp.c	modified	+13	−23	View file
drivers/clk/mediatek/clk-mt2701-img.c	modified	+13	−23	View file
drivers/clk/mediatek/clk-mt2701-vdec.c	modified	+13	−23	View file
drivers/clk/mediatek/clk-mt2712-bdp.c	modified	+12	−22	View file
drivers/clk/mediatek/clk-mt2712-img.c	modified	+12	−22	View file
drivers/clk/mediatek/clk-mt2712-jpgdec.c	modified	+12	−22	View file
drivers/clk/mediatek/clk-mt2712-mfg.c	modified	+12	−22	View file
drivers/clk/mediatek/clk-mt2712-vdec.c	modified	+12	−22	View file
drivers/clk/mediatek/clk-mt2712-venc.c	modified	+12	−22	View file
drivers/clk/mediatek/clk-mt6765-audio.c	modified	+12	−22	View file
drivers/clk/mediatek/clk-mt6765-cam.c	modified	+12	−21	View file
drivers/clk/mediatek/clk-mt6765-img.c	modified	+12	−21	View file
drivers/clk/mediatek/clk-mt6765-mipi0a.c	modified	+12	−22	View file
drivers/clk/mediatek/clk-mt6765-mm.c	modified	+12	−21	View file
drivers/clk/mediatek/clk-mt6765-vcodec.c	modified	+12	−22	View file
drivers/clk/mediatek/clk-mt6779-aud.c	modified	+13	−16	View file
drivers/clk/mediatek/clk-mt6779-cam.c	modified	+13	−16	View file
drivers/clk/mediatek/clk-mt6779-img.c	modified	+13	−16	View file
drivers/clk/mediatek/clk-mt6779-ipe.c	modified	+13	−16	View file
drivers/clk/mediatek/clk-mt6779-mfg.c	modified	+12	−15	View file
drivers/clk/mediatek/clk-mt6779-vdec.c	modified	+13	−16	View file
drivers/clk/mediatek/clk-mt6779-venc.c	modified	+13	−16	View file
drivers/clk/mediatek/clk-mt6795-apmixedsys.c	added	+157	−0	View file
drivers/clk/mediatek/clk-mt6795-infracfg.c	added	+151	−0	View file
drivers/clk/mediatek/clk-mt6795-mfg.c	added	+50	−0	View file
drivers/clk/mediatek/clk-mt6795-mm.c	added	+132	−0	View file
drivers/clk/mediatek/clk-mt6795-pericfg.c	added	+160	−0	View file
drivers/clk/mediatek/clk-mt6795-topckgen.c	added	+610	−0	View file
drivers/clk/mediatek/clk-mt6795-vdecsys.c	added	+55	−0	View file
drivers/clk/mediatek/clk-mt6795-vencsys.c	added	+50	−0	View file
drivers/clk/mediatek/clk-mt6797-img.c	modified	+13	−23	View file
drivers/clk/mediatek/clk-mt6797-vdec.c	modified	+13	−23	View file
drivers/clk/mediatek/clk-mt6797-venc.c	modified	+13	−23	View file
drivers/clk/mediatek/clk-mt8183-cam.c	modified	+12	−15	View file
drivers/clk/mediatek/clk-mt8183-img.c	modified	+12	−15	View file
drivers/clk/mediatek/clk-mt8183-ipu0.c	modified	+12	−15	View file
drivers/clk/mediatek/clk-mt8183-ipu1.c	modified	+12	−15	View file
drivers/clk/mediatek/clk-mt8183-ipu_adl.c	modified	+12	−15	View file
drivers/clk/mediatek/clk-mt8183-ipu_conn.c	modified	+12	−15	View file
drivers/clk/mediatek/clk-mt8183-mfgcfg.c	modified	+15	−20	View file
drivers/clk/mediatek/clk-mt8183-vdec.c	modified	+12	−15	View file
drivers/clk/mediatek/clk-mt8183-venc.c	modified	+12	−15	View file
drivers/clk/mediatek/clk-mt8183.c	modified	+28	−0	View file
drivers/clk/mediatek/clk-mt8192-cam.c	modified	+1	−0	View file
drivers/clk/mediatek/clk-mt8192-img.c	modified	+1	−0	View file
drivers/clk/mediatek/clk-mt8192-imp_iic_wrap.c	modified	+1	−0	View file
drivers/clk/mediatek/clk-mt8192-ipe.c	modified	+1	−0	View file
drivers/clk/mediatek/clk-mt8192-mdp.c	modified	+1	−0	View file
drivers/clk/mediatek/clk-mt8192-mfg.c	modified	+5	−2	View file
drivers/clk/mediatek/clk-mt8192-msdc.c	modified	+1	−0	View file
drivers/clk/mediatek/clk-mt8192-scp_adsp.c	modified	+1	−0	View file
drivers/clk/mediatek/clk-mt8192-vdec.c	modified	+1	−0	View file
drivers/clk/mediatek/clk-mt8192-venc.c	modified	+1	−0	View file
drivers/clk/mediatek/clk-mt8192.c	modified	+53	−181	View file
drivers/clk/mediatek/clk-mt8195-infra_ao.c	modified	+13	−3	View file
drivers/clk/mediatek/clk-mt8195-mfg.c	modified	+4	−2	View file
drivers/clk/mediatek/clk-mt8195-topckgen.c	modified	+32	−14	View file
drivers/clk/mediatek/clk-mt8195-vdo0.c	modified	+6	−1	View file
drivers/clk/mediatek/clk-mt8195-vdo1.c	modified	+16	−1	View file
drivers/clk/mediatek/clk-mt8365-apu.c	added	+55	−0	View file
drivers/clk/mediatek/clk-mt8365-cam.c	added	+57	−0	View file
drivers/clk/mediatek/clk-mt8365-mfg.c	added	+63	−0	View file
drivers/clk/mediatek/clk-mt8365-mm.c	added	+112	−0	View file
drivers/clk/mediatek/clk-mt8365-vdec.c	added	+63	−0	View file
drivers/clk/mediatek/clk-mt8365-venc.c	added	+52	−0	View file
drivers/clk/mediatek/clk-mt8365.c	added	+1155	−0	View file
drivers/clk/mediatek/clk-mtk.c	modified	+40	−12	View file
drivers/clk/mediatek/clk-mtk.h	modified	+3	−0	View file
drivers/clk/mediatek/clk-mux.c	modified	+38	−0	View file
drivers/clk/mediatek/clk-mux.h	modified	+15	−0	View file
drivers/clk/mediatek/reset.c	modified	+1	−0	View file
drivers/clk/meson/meson-aoclk.c	modified	+4	−1	View file
drivers/clk/meson/meson-eeclk.c	modified	+4	−1	View file
drivers/clk/meson/meson8b.c	modified	+4	−1	View file
drivers/clk/microchip/Kconfig	modified	+1	−0	View file
drivers/clk/microchip/Makefile	modified	+1	−0	View file
drivers/clk/microchip/clk-mpfs-ccc.c	added	+290	−0	View file
drivers/clk/microchip/clk-mpfs.c	modified	+185	−190	View file
drivers/clk/mmp/clk-of-pxa168.c	modified	+82	−31	View file
drivers/clk/mvebu/armada-37xx-tbg.c	modified	+2	−4	View file
drivers/clk/mvebu/dove-divider.c	modified	+1	−1	View file
drivers/clk/nxp/clk-lpc18xx-cgu.c	modified	+1	−1	View file
drivers/clk/pistachio/clk.h	modified	+2	−2	View file
drivers/clk/pxa/clk-pxa.c	modified	+2	−0	View file
drivers/clk/qcom/Kconfig	modified	+45	−2	View file
drivers/clk/qcom/Makefile	modified	+5	−0	View file
drivers/clk/qcom/a53-pll.c	modified	+3	−1	View file
drivers/clk/qcom/apss-ipq-pll.c	modified	+28	−5	View file
drivers/clk/qcom/apss-ipq6018.c	modified	+7	−8	View file
drivers/clk/qcom/clk-alpha-pll.c	modified	+63	−3	View file
drivers/clk/qcom/clk-alpha-pll.h	modified	+6	−2	View file
drivers/clk/qcom/clk-cpu-8996.c	modified	+177	−152	View file
drivers/clk/qcom/clk-rcg.h	modified	+1	−0	View file
drivers/clk/qcom/clk-rcg2.c	modified	+7	−0	View file
drivers/clk/qcom/clk-rpmh.c	modified	+21	−4	View file
drivers/clk/qcom/clk-smd-rpm.c	modified	+80	−3	View file
drivers/clk/qcom/dispcc-sm6115.c	added	+608	−0	View file
drivers/clk/qcom/dispcc-sm8450.c	added	+1829	−0	View file
drivers/clk/qcom/gcc-msm8660.c	modified	+197	−133	View file
drivers/clk/qcom/gcc-msm8909.c	added	+2731	−0	View file
drivers/clk/qcom/gcc-msm8916.c	modified	+518	−502	View file
drivers/clk/qcom/gcc-msm8939.c	modified	+276	−276	View file
drivers/clk/qcom/gcc-msm8960.c	modified	+268	−168	View file
drivers/clk/qcom/gcc-qcm2290.c	modified	+16	−40	View file
drivers/clk/qcom/gcc-sc7180.c	modified	+1	−1	View file
drivers/clk/qcom/gcc-sc7280.c	modified	+3	−3	View file
drivers/clk/qcom/gcc-sc8280xp.c	modified	+12	−8	View file
drivers/clk/qcom/gcc-sdm660.c	modified	+1	−1	View file
drivers/clk/qcom/gcc-sdm845.c	modified	+398	−2	View file
drivers/clk/qcom/gcc-sm6115.c	modified	+18	−30	View file
drivers/clk/qcom/gcc-sm6350.c	modified	+1	−1	View file
drivers/clk/qcom/gcc-sm6375.c	added	+3919	−0	View file
drivers/clk/qcom/gdsc.c	modified	+27	−8	View file
drivers/clk/qcom/gdsc.h	modified	+5	−0	View file
drivers/clk/qcom/gpucc-sc8280xp.c	added	+461	−0	View file
drivers/clk/qcom/kpss-xcc.c	modified	+9	−17	View file
drivers/clk/qcom/lcc-ipq806x.c	modified	+49	−35	View file
drivers/clk/qcom/lcc-msm8960.c	modified	+64	−147	View file
drivers/clk/qcom/lpassaudiocc-sc7280.c	modified	+65	−1	View file
drivers/clk/qcom/lpasscc-sc7280.c	modified	+0	−44	View file
drivers/clk/qcom/lpasscorecc-sc7280.c	modified	+33	−0	View file
drivers/clk/qcom/mmcc-msm8960.c	modified	+269	−185	View file
drivers/clk/qcom/reset.c	modified	+3	−1	View file
drivers/clk/qcom/reset.h	modified	+1	−0	View file
drivers/clk/renesas/r8a779f0-cpg-mssr.c	modified	+20	−1	View file
drivers/clk/renesas/r8a779g0-cpg-mssr.c	modified	+14	−0	View file
drivers/clk/renesas/r9a07g044-cpg.c	modified	+2	−0	View file
drivers/clk/renesas/r9a09g011-cpg.c	modified	+4	−0	View file
drivers/clk/rockchip/Kconfig	modified	+7	−0	View file
drivers/clk/rockchip/Makefile	modified	+1	−0	View file
drivers/clk/rockchip/clk-rv1126.c	added	+1138	−0	View file
drivers/clk/rockchip/clk.c	modified	+21	−6	View file
drivers/clk/rockchip/clk.h	modified	+36	−0	View file
drivers/clk/samsung/clk-exynos-clkout.c	modified	+2	−4	View file
drivers/clk/samsung/clk-exynos7885.c	modified	+200	−7	View file
drivers/clk/samsung/clk-exynos850.c	modified	+679	−3	View file
drivers/clk/samsung/clk-exynosautov9.c	modified	+391	−10	View file
drivers/clk/sprd/Kconfig	modified	+6	−0	View file
drivers/clk/sprd/Makefile	modified	+1	−0	View file
drivers/clk/sprd/common.c	modified	+5	−4	View file
drivers/clk/sprd/ums512-clk.c	added	+2202	−0	View file
drivers/clk/st/clkgen-fsyn.c	modified	+4	−1	View file
drivers/clk/st/clkgen-mux.c	modified	+4	−1	View file
drivers/clk/sunxi-ng/ccu-sun20i-d1.c	modified	+8	−0	View file
drivers/clk/sunxi-ng/ccu-sun8i-de2.c	modified	+9	−19	View file
drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c	modified	+6	−13	View file
drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c	modified	+3	−6	View file
drivers/clk/tegra/clk-bpmp.c	modified	+1	−1	View file
drivers/clk/tegra/clk-tegra114.c	modified	+1	−0	View file
drivers/clk/tegra/clk-tegra124.c	modified	+1	−0	View file
drivers/clk/tegra/clk-tegra20.c	modified	+1	−0	View file
drivers/clk/tegra/clk-tegra210.c	modified	+1	−0	View file
drivers/clk/tegra/clk-tegra30.c	modified	+1	−0	View file
drivers/clk/ti/clk-dra7-atl.c	modified	+6	−3	View file
drivers/clk/ti/clk.c	modified	+3	−2	View file
drivers/clk/xilinx/Kconfig	modified	+12	−0	View file
drivers/clk/xilinx/Makefile	modified	+1	−0	View file
drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c → drivers/clk/xilinx/clk-xlnx-clock-wizard.c	renamed	+20	−15	View file
drivers/clk/zynqmp/clkc.c	modified	+15	−4	View file
drivers/clk/zynqmp/divider.c	modified	+6	−3	View file
drivers/clk/zynqmp/pll.c	modified	+15	−16	View file
drivers/reset/Kconfig	modified	+7	−0	View file
drivers/reset/Makefile	modified	+1	−1	View file
drivers/reset/reset-mpfs.c	added	+157	−0	View file
drivers/staging/Kconfig	modified	+0	−2	View file
drivers/staging/Makefile	modified	+0	−1	View file
drivers/staging/clocking-wizard/Kconfig	deleted	+0	−10	View before deletion
drivers/staging/clocking-wizard/Makefile	deleted	+0	−2	View before deletion
drivers/staging/clocking-wizard/TODO	deleted	+0	−13	View before deletion
drivers/staging/clocking-wizard/dt-binding.txt	deleted	+0	−30	View before deletion
include/dt-bindings/clock/imx93-clock.h	modified	+8	−1	View file
include/dt-bindings/clk/lochnagar.h → include/dt-bindings/clock/lochnagar.h	renamed	+0	−0	View file
include/dt-bindings/clock/marvell,pxa168.h	modified	+6	−0	View file
include/dt-bindings/clock/mediatek,mt6795-clk.h	added	+275	−0	View file
include/dt-bindings/clock/mediatek,mt8365-clk.h	added	+373	−0	View file
include/dt-bindings/clock/microchip,mpfs-clock.h	modified	+23	−0	View file
include/dt-bindings/clock/mt8195-clk.h	modified	+3	−1	View file
include/dt-bindings/clock/qcom,gcc-msm8909.h	added	+218	−0	View file
include/dt-bindings/clock/qcom,gcc-sdm845.h	modified	+1	−0	View file
include/dt-bindings/clock/qcom,gpucc-sc8280xp.h	added	+35	−0	View file
include/dt-bindings/clock/qcom,lcc-ipq806x.h	modified	+2	−0	View file
include/dt-bindings/clock/qcom,rpmcc.h	modified	+1	−0	View file
include/dt-bindings/clock/qcom,sm6115-dispcc.h	added	+36	−0	View file
include/dt-bindings/clock/qcom,sm6375-gcc.h	added	+234	−0	View file
include/dt-bindings/clock/qcom,sm8450-dispcc.h	added	+103	−0	View file
include/dt-bindings/clock/rockchip,rv1126-cru.h	added	+632	−0	View file
include/dt-bindings/clk/versaclock.h → include/dt-bindings/clock/versaclock.h	renamed	+0	−0	View file
include/dt-bindings/reset/bt1-ccu.h	modified	+9	−0	View file
include/dt-bindings/reset/mediatek,mt6795-resets.h	added	+53	−0	View file
include/dt-bindings/reset/mt8195-resets.h	modified	+3	−0	View file
include/linux/clk-provider.h	modified	+57	−9	View file
include/linux/clk/davinci.h	modified	+0	−8	View file
include/linux/clkdev.h	modified	+0	−2	View file
include/linux/soc/qcom/smd-rpm.h	modified	+1	−0	View file
include/soc/microchip/mpfs.h	modified	+8	−0	View file

Only the first 600 diff lines are shown. Download the complete patch.

Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml

View file

diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml
index 8681b78..1d7c837 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml
@@ -23,6 +23,7 @@ properties:
               - mediatek,mt2701-infracfg
               - mediatek,mt2712-infracfg
               - mediatek,mt6765-infracfg
+              - mediatek,mt6795-infracfg
               - mediatek,mt6779-infracfg_ao
               - mediatek,mt6797-infracfg
               - mediatek,mt7622-infracfg
@@ -60,6 +61,7 @@ if:
         enum:
           - mediatek,mt2701-infracfg
           - mediatek,mt2712-infracfg
+          - mediatek,mt6795-infracfg
           - mediatek,mt7622-infracfg
           - mediatek,mt7986-infracfg
           - mediatek,mt8135-infracfg

Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml

View file

diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
index 6ad023e..597ef18 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
@@ -25,6 +25,7 @@ properties:
               - mediatek,mt2712-mmsys
               - mediatek,mt6765-mmsys
               - mediatek,mt6779-mmsys
+              - mediatek,mt6795-mmsys
               - mediatek,mt6797-mmsys
               - mediatek,mt8167-mmsys
               - mediatek,mt8173-mmsys

Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml

View file

diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml
index 8585f6f..ef62cbb 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml
@@ -21,6 +21,7 @@ properties:
               - mediatek,mt2701-pericfg
               - mediatek,mt2712-pericfg
               - mediatek,mt6765-pericfg
+              - mediatek,mt6795-pericfg
               - mediatek,mt7622-pericfg
               - mediatek,mt7629-pericfg
               - mediatek,mt8135-pericfg

Documentation/devicetree/bindings/clock/cirrus,cs2000-cp.yaml

View file

diff --git a/Documentation/devicetree/bindings/clock/cirrus,cs2000-cp.yaml b/Documentation/devicetree/bindings/clock/cirrus,cs2000-cp.yaml
index 0abd6ba..8283608 100644
--- a/Documentation/devicetree/bindings/clock/cirrus,cs2000-cp.yaml
+++ b/Documentation/devicetree/bindings/clock/cirrus,cs2000-cp.yaml
@@ -23,7 +23,6 @@ properties:
   clocks:
     description:
       Common clock binding for CLK_IN, XTI/REF_CLK
-    minItems: 2
     maxItems: 2
 
   clock-names:

Documentation/devicetree/bindings/clock/gpio-gate-clock.txt

View before deletion

diff --git a/Documentation/devicetree/bindings/clock/gpio-gate-clock.txt b/Documentation/devicetree/bindings/clock/gpio-gate-clock.txt
deleted file mode 100644
index d3379ff..0000000
--- a/Documentation/devicetree/bindings/clock/gpio-gate-clock.txt
+++ /dev/null
@@ -1,21 +0,0 @@
-Binding for simple gpio gated clock.
-
-This binding uses the common clock binding[1].
-
-[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
-
-Required properties:
-- compatible : shall be "gpio-gate-clock".
-- #clock-cells : from common clock binding; shall be set to 0.
-- enable-gpios : GPIO reference for enabling and disabling the clock.
-
-Optional properties:
-- clocks: Maximum of one parent clock is supported.
-
-Example:
-	clock {
-		compatible = "gpio-gate-clock";
-		clocks = <&parentclk>;
-		#clock-cells = <0>;
-		enable-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
-	};

Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml

View file

diff --git a/Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml b/Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml
new file mode 100644
index 0000000..d09d0e3
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/gpio-gate-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Simple GPIO clock gate
+
+maintainers:
+  - Jyri Sarha <[email protected]>
+
+properties:
+  compatible:
+    const: gpio-gate-clock
+
+  clocks:
+    maxItems: 1
+
+  '#clock-cells':
+    const: 0
+
+  enable-gpios:
+    description: GPIO reference for enabling and disabling the clock.
+    maxItems: 1
+
+required:
+  - compatible
+  - '#clock-cells'
+  - enable-gpios
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/gpio/gpio.h>
+
+    clock {
+        compatible = "gpio-gate-clock";
+        clocks = <&parentclk>;
+        #clock-cells = <0>;
+        enable-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
+    };

Documentation/devicetree/bindings/clock/idt,versaclock5.yaml

View file

diff --git a/Documentation/devicetree/bindings/clock/idt,versaclock5.yaml b/Documentation/devicetree/bindings/clock/idt,versaclock5.yaml
index 7c331bf..f9ba986 100644
--- a/Documentation/devicetree/bindings/clock/idt,versaclock5.yaml
+++ b/Documentation/devicetree/bindings/clock/idt,versaclock5.yaml
@@ -56,6 +56,7 @@ properties:
       - idt,5p49v5935
       - idt,5p49v6901
       - idt,5p49v6965
+      - idt,5p49v6975
 
   reg:
     description: I2C device address
@@ -108,7 +109,7 @@ patternProperties:
     properties:
       idt,mode:
         description:
-          The output drive mode. Values defined in dt-bindings/clk/versaclock.h
+          The output drive mode. Values defined in dt-bindings/clock/versaclock.h
         $ref: /schemas/types.yaml#/definitions/uint32
         minimum: 0
         maximum: 6
@@ -134,6 +135,7 @@ allOf:
           enum:
             - idt,5p49v5933
             - idt,5p49v5935
+            - idt,5p49v6975
     then:
       # Devices with builtin crystal + optional external input
       properties:
@@ -151,7 +153,7 @@ additionalProperties: false
 
 examples:
   - |
-    #include <dt-bindings/clk/versaclock.h>
+    #include <dt-bindings/clock/versaclock.h>
 
     /* 25MHz reference crystal */
     ref25: ref25m {

Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml

View file

diff --git a/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml b/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml
index 7705461..731bfe0 100644
--- a/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml
+++ b/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml
@@ -34,6 +34,7 @@ properties:
               - mediatek,mt2712-apmixedsys
               - mediatek,mt6765-apmixedsys
               - mediatek,mt6779-apmixedsys
+              - mediatek,mt6795-apmixedsys
               - mediatek,mt7629-apmixedsys
               - mediatek,mt8167-apmixedsys
               - mediatek,mt8183-apmixedsys

Documentation/devicetree/bindings/clock/mediatek,mt6795-clock.yaml

View file

diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt6795-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt6795-clock.yaml
new file mode 100644
index 0000000..04469ea
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/mediatek,mt6795-clock.yaml
@@ -0,0 +1,66 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/mediatek,mt6795-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek Functional Clock Controller for MT6795
+
+maintainers:
+  - AngeloGioacchino Del Regno <[email protected]>
+  - Chun-Jie Chen <[email protected]>
+
+description: |
+  The clock architecture in MediaTek like below
+  PLLs -->
+          dividers -->
+                      muxes
+                           -->
+                              clock gate
+
+  The devices provide clock gate control in different IP blocks.
+
+properties:
+  compatible:
+    enum:
+      - mediatek,mt6795-mfgcfg
+      - mediatek,mt6795-vdecsys
+      - mediatek,mt6795-vencsys
+
+  reg:
+    maxItems: 1
+
+  '#clock-cells':
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        mfgcfg: clock-controller@13000000 {
+            compatible = "mediatek,mt6795-mfgcfg";
+            reg = <0 0x13000000 0 0x1000>;
+            #clock-cells = <1>;
+        };
+
+        vdecsys: clock-controller@16000000 {
+            compatible = "mediatek,mt6795-vdecsys";
+            reg = <0 0x16000000 0 0x1000>;
+            #clock-cells = <1>;
+        };
+
+        vencsys: clock-controller@18000000 {
+            compatible = "mediatek,mt6795-vencsys";
+            reg = <0 0x18000000 0 0x1000>;
+            #clock-cells = <1>;
+        };
+    };

Documentation/devicetree/bindings/clock/mediatek,mt6795-sys-clock.yaml

View file

diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt6795-sys-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt6795-sys-clock.yaml
new file mode 100644
index 0000000..378b761
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/mediatek,mt6795-sys-clock.yaml
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/mediatek,mt6795-sys-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek System Clock Controller for MT6795
+
+maintainers:
+  - AngeloGioacchino Del Regno <[email protected]>
+  - Chun-Jie Chen <[email protected]>
+
+description:
+  The Mediatek system clock controller provides various clocks and system
+  configuration like reset and bus protection on MT6795.
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - mediatek,mt6795-apmixedsys
+          - mediatek,mt6795-infracfg
+          - mediatek,mt6795-pericfg
+          - mediatek,mt6795-topckgen
+      - const: syscon
+
+  reg:
+    maxItems: 1
+
+  '#clock-cells':
+    const: 1
+
+  '#reset-cells':
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        topckgen: clock-controller@10000000 {
+            compatible = "mediatek,mt6795-topckgen", "syscon";
+            reg = <0 0x10000000 0 0x1000>;
+            #clock-cells = <1>;
+        };
+    };

Documentation/devicetree/bindings/clock/mediatek,mt8365-clock.yaml

View file

diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8365-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8365-clock.yaml
new file mode 100644
index 0000000..b327ecb
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/mediatek,mt8365-clock.yaml
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/mediatek,mt8365-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek Functional Clock Controller for MT8365
+
+maintainers:
+  - Markus Schneider-Pargmann <[email protected]>
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - mediatek,mt8365-apu
+          - mediatek,mt8365-imgsys
+          - mediatek,mt8365-mfgcfg
+          - mediatek,mt8365-vdecsys
+          - mediatek,mt8365-vencsys
+      - const: syscon
+
+  reg:
+    maxItems: 1
+
+  '#clock-cells':
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    apu: clock-controller@19020000 {
+        compatible = "mediatek,mt8365-apu", "syscon";
+        reg = <0x19020000 0x1000>;
+        #clock-cells = <1>;
+    };

Documentation/devicetree/bindings/clock/mediatek,mt8365-sys-clock.yaml

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diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8365-sys-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8365-sys-clock.yaml
new file mode 100644
index 0000000..643f846
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/mediatek,mt8365-sys-clock.yaml
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/mediatek,mt8365-sys-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek System Clock Controller for MT8365
+
+maintainers:
+  - Markus Schneider-Pargmann <[email protected]>
+
+description:
+  The apmixedsys module provides most of PLLs which generated from SoC 26m.
+  The topckgen provides dividers and muxes which provides the clock source to other IP blocks.
+  The infracfg_ao and pericfg_ao provides clock gate in peripheral and infrastructure IP blocks.
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - mediatek,mt8365-topckgen
+          - mediatek,mt8365-infracfg
+          - mediatek,mt8365-apmixedsys
+          - mediatek,mt8365-pericfg
+          - mediatek,mt8365-mcucfg
+      - const: syscon
+
+  reg:
+    maxItems: 1
+
+  '#clock-cells':
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    topckgen: clock-controller@10000000 {
+        compatible = "mediatek,mt8365-topckgen", "syscon";
+        reg = <0x10000000 0x1000>;
+        #clock-cells = <1>;
+    };

Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml

View file

diff --git a/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml b/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml
index 5b8b37a..81531b5 100644
--- a/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml
+++ b/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml
@@ -33,6 +33,7 @@ properties:
               - mediatek,mt2712-topckgen
               - mediatek,mt6765-topckgen
               - mediatek,mt6779-topckgen
+              - mediatek,mt6795-topckgen
               - mediatek,mt7629-topckgen
               - mediatek,mt7986-topckgen
               - mediatek,mt8167-topckgen

Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml

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diff --git a/Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml b/Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml
new file mode 100644
index 0000000..f177036
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml
@@ -0,0 +1,80 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/microchip,mpfs-ccc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip PolarFire SoC Fabric Clock Conditioning Circuitry
+
+maintainers:
+  - Conor Dooley <[email protected]>
+
+description: |
+  Microchip PolarFire SoC has 4 Clock Conditioning Circuitry blocks. Each of
+  these blocks contains two PLLs and 2 DLLs & are located in the four corners of
+  the FPGA. For more information see "PolarFire SoC FPGA Clocking Resources" at:
+  https://onlinedocs.microchip.com/pr/GUID-8F0CC4C0-0317-4262-89CA-CE7773ED1931-en-US-1/index.html
+
+properties:
+  compatible:
+    const: microchip,mpfs-ccc
+
+  reg:
+    items:
+      - description: PLL0's control registers
+      - description: PLL1's control registers
+      - description: DLL0's control registers
+      - description: DLL1's control registers
+
+  clocks:
+    description:
+      The CCC PLL's have two input clocks. It is required that even if the input
+      clocks are identical that both are provided.
+    minItems: 2
+    items:
+      - description: PLL0's refclk0
+      - description: PLL0's refclk1
+      - description: PLL1's refclk0
+      - description: PLL1's refclk1
+      - description: DLL0's refclk
+      - description: DLL1's refclk
+
+  clock-names:
+    minItems: 2
+    items:
+      - const: pll0_ref0
+      - const: pll0_ref1
+      - const: pll1_ref0
+      - const: pll1_ref1
+      - const: dll0_ref
+      - const: dll1_ref
+
+  '#clock-cells':
+    const: 1
+    description: |
+      The clock consumer should specify the desired clock by having the clock
+      ID in its "clocks" phandle cell.
+      See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of
+      PolarFire clock IDs.
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    clock-controller@38100000 {
+        compatible = "microchip,mpfs-ccc";
+        reg = <0x38010000 0x1000>, <0x38020000 0x1000>,
+              <0x39010000 0x1000>, <0x39020000 0x1000>;
+        #clock-cells = <1>;
+        clocks = <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>,
+                  <&refclk_ccc>, <&refclk_ccc>;
+        clock-names = "pll0_ref0", "pll0_ref1", "pll1_ref0", "pll1_ref1",
+                      "dll0_ref", "dll1_ref";
+    };

Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml

View file

diff --git a/Documentation/devicetree/bindings/clock/microchip,mpfs.yaml b/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml
similarity index 85%
rename from Documentation/devicetree/bindings/clock/microchip,mpfs.yaml
rename to Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml
index 016a4f3..b2ce787 100644
--- a/Documentation/devicetree/bindings/clock/microchip,mpfs.yaml
+++ b/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml
@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
 %YAML 1.2
 ---
-$id: http://devicetree.org/schemas/clock/microchip,mpfs.yaml#
+$id: http://devicetree.org/schemas/clock/microchip,mpfs-clkcfg.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
 title: Microchip PolarFire Clock Control Module Binding
@@ -40,8 +40,21 @@ properties:
     const: 1
     description: |
       The clock consumer should specify the desired clock by having the clock
-      ID in its "clocks" phandle cell. See include/dt-bindings/clock/microchip,mpfs-clock.h
-      for the full list of PolarFire clock IDs.
+      ID in its "clocks" phandle cell.
+      See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of
+      PolarFire clock IDs.
+
+  resets:
+    maxItems: 1
+
+  '#reset-cells':
+    description:
+      The AHB/AXI peripherals on the PolarFire SoC have reset support, so from
+      CLK_ENVM to CLK_CFM. The reset consumer should specify the desired
+      peripheral via the clock ID in its "resets" phandle cell.
+      See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of
+      PolarFire clock IDs.
+    const: 1
 
 required:
   - compatible

Documentation/devicetree/bindings/clock/qcom,a53pll.yaml

View file

diff --git a/Documentation/devicetree/bindings/clock/qcom,a53pll.yaml b/Documentation/devicetree/bindings/clock/qcom,a53pll.yaml
index fbd7584..fe6ca4f 100644
--- a/Documentation/devicetree/bindings/clock/qcom,a53pll.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,a53pll.yaml
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
 title: Qualcomm A53 PLL Binding
 
 maintainers:
-  - Sivaprakash Murugesan <[email protected]>
+  - Bjorn Andersson <[email protected]>
 
 description:
   The A53 PLL on few Qualcomm platforms is the main CPU PLL used used for
@@ -17,6 +17,7 @@ properties:
   compatible:
     enum:
       - qcom,ipq6018-a53pll
+      - qcom,ipq8074-a53pll
       - qcom,msm8916-a53pll
       - qcom,msm8939-a53pll
 

Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml

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diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml
index 3cf404c..6b4efd6 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml
@@ -38,6 +38,15 @@ properties:
     description: child tsens device
     $ref: /schemas/thermal/qcom-tsens.yaml#
 
+  clocks:
+    maxItems: 3
+
+  clock-names:
+    items:
+      - const: cxo
+      - const: pxo
+      - const: pll4
+
   nvmem-cells:
     minItems: 1
     maxItems: 2

Documentation/devicetree/bindings/clock/qcom,gcc-msm8660.yaml

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diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8660.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8660.yaml
new file mode 100644
index 0000000..09b2ea6
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8660.yaml
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: GPL-2.0-only

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