Merge tag 'usb-4.21-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb

c0ea81b4 · Linus Torvalds <[email protected]> · 2018-12-28 20:30:00 -08:00

Pull USB/PHY updates from Greg KH:
 "Here is the big set of USB and PHY driver patches for 4.21-rc1.

  All of the usual bits are in here:

  - loads of USB gadget driver updates and additions

  - new device ids

  - phy driver updates

  - xhci reworks and new features

  - typec updates

  Full details are in the shortlog.

  All of these have been in linux-next for a long time with no reported
  issues"

* tag 'usb-4.21-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb: (142 commits)
  USB: serial: option: add Fibocom NL678 series
  cdc-acm: fix abnormal DATA RX issue for Mediatek Preloader.
  usb: r8a66597: Fix a possible concurrency use-after-free bug in r8a66597_endpoint_disable()
  usb: typec: tcpm: Extend the matching rules on PPS APDO selection
  usb: typec: Improve Alt Mode documentation
  usb: musb: dsps: fix runtime pm for peripheral mode
  usb: musb: dsps: fix otg state machine
  USB: serial: pl2303: add ids for Hewlett-Packard HP POS pole displays
  usb: renesas_usbhs: add support for RZ/G2E
  usb: ehci-omap: Fix deferred probe for phy handling
  usb: roles: Add a description for the class to Kconfig
  usb: renesas_usbhs: mark PM functions as __maybe_unused
  usb: core: Remove unnecessary memset()
  usb: host: isp1362-hcd: convert to DEFINE_SHOW_ATTRIBUTE
  phy: qcom-qmp: Expose provided clocks to DT
  dt-bindings: phy-qcom-qmp: Move #clock-cells to child
  phy: qcom-qmp: Utilize fully-specified DT registers
  dt-bindings: phy-qcom-qmp: Fix register underspecification
  phy: ti: fix semicolon.cocci warnings
  phy: dphy: Add configuration helpers
  ...

Commit: c0ea81b4d37837409d0dfd2036098a7babb312ed
Parents: 4d6ad6fb · 4b2c01ad

Merge commit. Changes below are compared with the first parent: 4d6ad6fb.

Changes

118 files changed · +3628 −838

File	Status	Add	Del	Content
Documentation/devicetree/bindings/connector/usb-connector.txt	modified	+2	−0	View file
Documentation/devicetree/bindings/net/cpsw.txt	modified	+7	−1	View file
Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.txt	added	+17	−0	View file
Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt	modified	+65	−12	View file
Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt	modified	+5	−3	View file
Documentation/devicetree/bindings/phy/ti-phy-gmii-sel.txt	added	+68	−0	View file
Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt	modified	+33	−3	View file
Documentation/devicetree/bindings/usb/dwc3.txt	modified	+4	−0	View file
Documentation/driver-api/usb/index.rst	modified	+1	−0	View file
Documentation/driver-api/usb/typec.rst	modified	+1	−0	View file
Documentation/driver-api/usb/typec_bus.rst	modified	+12	−12	View file
Documentation/usb/authorization.txt	modified	+1	−1	View file
MAINTAINERS	modified	+1	−0	View file
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c	modified	+2	−17	View file
drivers/net/ethernet/mscc/ocelot.c	modified	+2	−7	View file
drivers/net/ethernet/ti/cpsw.c	modified	+18	−1	View file
drivers/phy/Kconfig	modified	+9	−0	View file
drivers/phy/Makefile	modified	+2	−0	View file
drivers/phy/allwinner/phy-sun4i-usb.c	modified	+26	−3	View file
drivers/phy/amlogic/phy-meson-gxl-usb2.c	modified	+3	−2	View file
drivers/phy/amlogic/phy-meson-gxl-usb3.c	modified	+3	−2	View file
drivers/phy/cadence/Kconfig	modified	+8	−1	View file
drivers/phy/cadence/Makefile	modified	+1	−0	View file
drivers/phy/cadence/phy-cadence-sierra.c	added	+395	−0	View file
drivers/phy/freescale/Kconfig	added	+5	−0	View file
drivers/phy/freescale/Makefile	added	+1	−0	View file
drivers/phy/freescale/phy-fsl-imx8mq-usb.c	added	+127	−0	View file
drivers/phy/marvell/phy-mvebu-cp110-comphy.c	modified	+55	−42	View file
drivers/phy/mediatek/phy-mtk-tphy.c	modified	+1	−1	View file
drivers/phy/mediatek/phy-mtk-xsphy.c	modified	+1	−1	View file
drivers/phy/motorola/phy-mapphone-mdm6600.c	modified	+51	−20	View file
drivers/phy/mscc/phy-ocelot-serdes.c	modified	+17	−7	View file
drivers/phy/phy-core-mipi-dphy.c	added	+166	−0	View file
drivers/phy/phy-core.c	modified	+67	−3	View file
drivers/phy/qualcomm/phy-qcom-qmp.c	modified	+62	−15	View file
drivers/phy/qualcomm/phy-qcom-qusb2.c	modified	+2	−1	View file
drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.c	modified	+2	−1	View file
drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.c	modified	+2	−1	View file
drivers/phy/qualcomm/phy-qcom-usb-hs.c	modified	+2	−1	View file
drivers/phy/renesas/phy-rcar-gen3-usb2.c	modified	+11	−6	View file
drivers/phy/rockchip/phy-rockchip-inno-usb2.c	modified	+3	−3	View file
drivers/phy/rockchip/phy-rockchip-typec.c	modified	+2	−2	View file
drivers/phy/ti/Kconfig	modified	+10	−0	View file
drivers/phy/ti/Makefile	modified	+1	−0	View file
drivers/phy/ti/phy-da8xx-usb.c	modified	+2	−1	View file
drivers/phy/ti/phy-gmii-sel.c	added	+349	−0	View file
drivers/phy/ti/phy-tusb1210.c	modified	+1	−1	View file
drivers/platform/x86/intel_cht_int33fe.c	modified	+1	−1	View file
drivers/usb/Kconfig	modified	+0	−4	View file
drivers/usb/chipidea/ci_hdrc_imx.c	modified	+138	−20	View file
drivers/usb/chipidea/ci_hdrc_imx.h	modified	+13	−4	View file
drivers/usb/chipidea/host.c	modified	+92	−0	View file
drivers/usb/chipidea/usbmisc_imx.c	modified	+176	−7	View file
drivers/usb/class/cdc-acm.c	modified	+10	−0	View file
drivers/usb/class/cdc-acm.h	modified	+1	−0	View file
drivers/usb/common/Makefile	modified	+0	−1	View file
drivers/usb/core/hcd.c	modified	+0	−2	View file
drivers/usb/core/hub.c	modified	+10	−0	View file
drivers/usb/dwc2/gadget.c	modified	+25	−19	View file
drivers/usb/dwc2/hcd.h	modified	+1	−1	View file
drivers/usb/dwc2/hcd_queue.c	modified	+12	−7	View file
drivers/usb/dwc2/hw.h	modified	+2	−0	View file
drivers/usb/dwc2/params.c	modified	+10	−1	View file
drivers/usb/dwc3/core.c	modified	+14	−5	View file
drivers/usb/dwc3/core.h	modified	+51	−9	View file
drivers/usb/dwc3/debug.h	modified	+29	−0	View file
drivers/usb/dwc3/debugfs.c	modified	+187	−14	View file
drivers/usb/dwc3/drd.c	modified	+13	−2	View file
drivers/usb/dwc3/dwc3-pci.c	modified	+4	−4	View file
drivers/usb/dwc3/gadget.c	modified	+222	−120	View file
drivers/usb/dwc3/gadget.h	modified	+15	−0	View file
drivers/usb/dwc3/host.c	modified	+4	−1	View file
drivers/usb/dwc3/trace.h	modified	+3	−1	View file
drivers/usb/early/ehci-dbgp.c	modified	+19	−19	View file
drivers/usb/gadget/function/f_fs.c	modified	+108	−14	View file
drivers/usb/gadget/function/uvc_queue.c	modified	+1	−1	View file
drivers/usb/gadget/udc/aspeed-vhub/dev.c	modified	+1	−1	View file
drivers/usb/gadget/udc/pch_udc.c	modified	+1	−1	View file
drivers/usb/gadget/udc/renesas_usb3.c	modified	+10	−5	View file
drivers/usb/gadget/udc/s3c2410_udc.c	modified	+2	−15	View file
drivers/usb/host/ehci-omap.c	modified	+4	−3	View file
drivers/usb/host/isp1362-hcd.c	modified	+3	−13	View file
drivers/usb/host/ohci-mem.c	modified	+4	−8	View file
drivers/usb/host/r8a66597-hcd.c	modified	+4	−1	View file
drivers/usb/host/xhci-hub.c	modified	+196	−155	View file
drivers/usb/host/xhci-mem.c	modified	+9	−21	View file
drivers/usb/host/xhci-ring.c	modified	+1	−1	View file
drivers/usb/host/xhci.c	modified	+11	−11	View file
drivers/usb/host/xhci.h	modified	+2	−11	View file
drivers/usb/misc/appledisplay.c	modified	+1	−7	View file
drivers/usb/mtu3/mtu3_core.c	modified	+9	−11	View file
drivers/usb/mtu3/mtu3_gadget_ep0.c	modified	+9	−5	View file
drivers/usb/mtu3/mtu3_hw_regs.h	modified	+6	−0	View file
drivers/usb/mtu3/mtu3_plat.c	modified	+8	−0	View file
drivers/usb/mtu3/mtu3_qmu.c	modified	+1	−27	View file
drivers/usb/musb/musb_dsps.c	modified	+16	−5	View file
drivers/usb/renesas_usbhs/common.c	modified	+7	−20	View file
drivers/usb/roles/Kconfig	modified	+13	−0	View file
drivers/usb/roles/Makefile	modified	+3	−1	View file
drivers/usb/common/roles.c → drivers/usb/roles/class.c	renamed	+0	−0	View file
drivers/usb/serial/f81534.c	modified	+17	−3	View file
drivers/usb/serial/ftdi_sio.c	modified	+3	−3	View file
drivers/usb/serial/mos7840.c	modified	+25	−46	View file
drivers/usb/serial/option.c	modified	+4	−0	View file
drivers/usb/serial/pl2303.c	modified	+5	−0	View file
drivers/usb/serial/pl2303.h	modified	+5	−0	View file
drivers/usb/serial/quatech2.c	modified	+0	−3	View file
drivers/usb/storage/ene_ub6250.c	modified	+1	−1	View file
drivers/usb/typec/tcpm/fusb302.c	modified	+1	−1	View file
drivers/usb/typec/tcpm/tcpm.c	modified	+38	−18	View file
drivers/uwb/i1480/dfu/usb.c	modified	+1	−1	View file
include/linux/phy/phy-mipi-dphy.h	added	+285	−0	View file
include/linux/phy/phy.h	modified	+76	−7	View file
include/linux/usb/ccid.h	added	+51	−0	View file
include/linux/usb/chipidea.h	modified	+3	−0	View file
include/linux/usb/gadget.h	modified	+4	−0	View file
include/linux/usb/hcd.h	modified	+0	−5	View file
include/linux/usb/tcpm.h	modified	+1	−0	View file

Only the first 600 diff lines are shown. Download the complete patch.

Documentation/devicetree/bindings/connector/usb-connector.txt

View file

diff --git a/Documentation/devicetree/bindings/connector/usb-connector.txt b/Documentation/devicetree/bindings/connector/usb-connector.txt
index d90e17e..a9a2f2f 100644
--- a/Documentation/devicetree/bindings/connector/usb-connector.txt
+++ b/Documentation/devicetree/bindings/connector/usb-connector.txt
@@ -14,6 +14,8 @@ Optional properties:
 - label: symbolic name for the connector,
 - type: size of the connector, should be specified in case of USB-A, USB-B
   non-fullsize connectors: "mini", "micro".
+- self-powered: Set this property if the usb device that has its own power
+  source.
 
 Optional properties for usb-c-connector:
 - power-role: should be one of "source", "sink" or "dual"(DRP) if typec

Documentation/devicetree/bindings/net/cpsw.txt

View file

diff --git a/Documentation/devicetree/bindings/net/cpsw.txt b/Documentation/devicetree/bindings/net/cpsw.txt
index b3acebe..3264e19 100644
--- a/Documentation/devicetree/bindings/net/cpsw.txt
+++ b/Documentation/devicetree/bindings/net/cpsw.txt
@@ -22,7 +22,8 @@ Required properties:
 - cpsw-phy-sel		: Specifies the phandle to the CPSW phy mode selection
 			  device. See also cpsw-phy-sel.txt for it's binding.
 			  Note that in legacy cases cpsw-phy-sel may be
-			  a child device instead of a phandle.
+			  a child device instead of a phandle
+			  (DEPRECATED, use phys property instead).
 
 Optional properties:
 - ti,hwmods		: Must be "cpgmac0"
@@ -44,6 +45,7 @@ Optional properties:
 Slave Properties:
 Required properties:
 - phy-mode		: See ethernet.txt file in the same directory
+- phys			: phandle on phy-gmii-sel PHY (see phy/ti-phy-gmii-sel.txt)
 
 Optional properties:
 - dual_emac_res_vlan	: Specifies VID to be used to segregate the ports
@@ -85,12 +87,14 @@ Examples:
 			phy-mode = "rgmii-txid";
 			/* Filled in by U-Boot */
 			mac-address = [ 00 00 00 00 00 00 ];
+			phys = <&phy_gmii_sel 1 0>;
 		};
 		cpsw_emac1: slave@1 {
 			phy_id = <&davinci_mdio>, <1>;
 			phy-mode = "rgmii-txid";
 			/* Filled in by U-Boot */
 			mac-address = [ 00 00 00 00 00 00 ];
+			phys = <&phy_gmii_sel 2 0>;
 		};
 	};
 
@@ -114,11 +118,13 @@ Examples:
 			phy-mode = "rgmii-txid";
 			/* Filled in by U-Boot */
 			mac-address = [ 00 00 00 00 00 00 ];
+			phys = <&phy_gmii_sel 1 0>;
 		};
 		cpsw_emac1: slave@1 {
 			phy_id = <&davinci_mdio>, <1>;
 			phy-mode = "rgmii-txid";
 			/* Filled in by U-Boot */
 			mac-address = [ 00 00 00 00 00 00 ];
+			phys = <&phy_gmii_sel 2 0>;
 		};
 	};

Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.txt

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diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.txt b/Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.txt
new file mode 100644
index 0000000..a22e853
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.txt
@@ -0,0 +1,17 @@
+* Freescale i.MX8MQ USB3 PHY binding
+
+Required properties:
+- compatible:	Should be "fsl,imx8mq-usb-phy"
+- #phys-cells:	must be 0 (see phy-bindings.txt in this directory)
+- reg:		The base address and length of the registers
+- clocks:	phandles to the clocks for each clock listed in clock-names
+- clock-names:	must contain "phy"
+
+Example:
+	usb3_phy0: phy@381f0040 {
+		compatible = "fsl,imx8mq-usb-phy";
+		reg = <0x381f0040 0x40>;
+		clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>;
+		clock-names = "phy";
+		#phy-cells = <0>;
+	};

Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt

View file

diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
index fbc198d..41a1074 100644
--- a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
+++ b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
@@ -25,10 +25,6 @@ Required properties:
   - For all others:
     - The reg-names property shouldn't be defined.
 
- - #clock-cells: must be 1
-    - Phy pll outputs a bunch of clocks for Tx, Rx and Pipe
-      interface (for pipe based PHYs). These clock are then gate-controlled
-      by gcc.
  - #address-cells: must be 1
  - #size-cells: must be 1
  - ranges: must be present
@@ -82,27 +78,33 @@ Required nodes:
  - Each device node of QMP phy is required to have as many child nodes as
    the number of lanes the PHY has.
 
-Required properties for child node:
+Required properties for child nodes of PCIe PHYs (one child per lane):
  - reg: list of offset and length pairs of register sets for PHY blocks -
-	- index 0: tx
-	- index 1: rx
-	- index 2: pcs
-	- index 3: pcs_misc (optional)
+	tx, rx, pcs, and pcs_misc (optional).
+ - #phy-cells: must be 0
 
+Required properties for a single "lanes" child node of non-PCIe PHYs:
+ - reg: list of offset and length pairs of register sets for PHY blocks
+	For 1-lane devices:
+		tx, rx, pcs, and (optionally) pcs_misc
+	For 2-lane devices:
+		tx0, rx0, pcs, tx1, rx1, and (optionally) pcs_misc
  - #phy-cells: must be 0
 
-Required properties child node of pcie and usb3 qmp phys:
+Required properties for child node of PCIe and USB3 qmp phys:
  - clocks: a list of phandles and clock-specifier pairs,
 	   one for each entry in clock-names.
  - clock-names: Must contain following:
 		 "pipe<lane-number>" for pipe clock specific to each lane.
  - clock-output-names: Name of the PHY clock that will be the parent for
 		       the above pipe clock.
-
 	For "qcom,ipq8074-qmp-pcie-phy":
 		- "pcie20_phy0_pipe_clk"	Pipe Clock parent
 			(or)
 		  "pcie20_phy1_pipe_clk"
+ - #clock-cells: must be 0
+    - Phy pll outputs pipe clocks for pipe based PHYs. These clocks are then
+      gate-controlled by the gcc.
 
 Required properties for child node of PHYs with lane reset, AKA:
 	"qcom,msm8996-qmp-pcie-phy"
@@ -115,7 +117,6 @@ Example:
 	phy@34000 {
 		compatible = "qcom,msm8996-qmp-pcie-phy";
 		reg = <0x34000 0x488>;
-		#clock-cells = <1>;
 		#address-cells = <1>;
 		#size-cells = <1>;
 		ranges;
@@ -137,6 +138,7 @@ Example:
 			reg = <0x35000 0x130>,
 				<0x35200 0x200>,
 				<0x35400 0x1dc>;
+			#clock-cells = <0>;
 			#phy-cells = <0>;
 
 			clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
@@ -150,3 +152,54 @@ Example:
 		...
 		...
 	};
+
+	phy@88eb000 {
+		compatible = "qcom,sdm845-qmp-usb3-uni-phy";
+		reg = <0x88eb000 0x18c>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
+			 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+			 <&gcc GCC_USB3_SEC_CLKREF_CLK>,
+			 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
+		clock-names = "aux", "cfg_ahb", "ref", "com_aux";
+
+		resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
+			 <&gcc GCC_USB3_PHY_SEC_BCR>;
+		reset-names = "phy", "common";
+
+		lane@88eb200 {
+			reg = <0x88eb200 0x128>,
+			      <0x88eb400 0x1fc>,
+			      <0x88eb800 0x218>,
+			      <0x88eb600 0x70>;
+			#clock-cells = <0>;
+			#phy-cells = <0>;
+			clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
+			clock-names = "pipe0";
+			clock-output-names = "usb3_uni_phy_pipe_clk_src";
+		};
+	};
+
+	phy@1d87000 {
+		compatible = "qcom,sdm845-qmp-ufs-phy";
+		reg = <0x1d87000 0x18c>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		clock-names = "ref",
+			      "ref_aux";
+		clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
+			 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
+
+		lanes@1d87400 {
+			reg = <0x1d87400 0x108>,
+			      <0x1d87600 0x1e0>,
+			      <0x1d87c00 0x1dc>,
+			      <0x1d87800 0x108>,
+			      <0x1d87a00 0x1e0>;
+			#phy-cells = <0>;
+		};
+	};

Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt

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diff --git a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
index 07ca4ec..f2e120a 100644
--- a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
+++ b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
@@ -14,13 +14,14 @@ Required properties:
   * allwinner,sun8i-r40-usb-phy
   * allwinner,sun8i-v3s-usb-phy
   * allwinner,sun50i-a64-usb-phy
+  * allwinner,sun50i-h6-usb-phy
 - reg : a list of offset + length pairs
 - reg-names :
   * "phy_ctrl"
-  * "pmu0" for H3, V3s and A64
+  * "pmu0" for H3, V3s, A64 or H6
   * "pmu1"
   * "pmu2" for sun4i, sun6i, sun7i, sun8i-a83t or sun8i-h3
-  * "pmu3" for sun8i-h3
+  * "pmu3" for sun8i-h3 or sun50i-h6
 - #phy-cells : from the generic phy bindings, must be 1
 - clocks : phandle + clock specifier for the phy clocks
 - clock-names :
@@ -29,12 +30,13 @@ Required properties:
   * "usb0_phy", "usb1_phy" for sun8i
   * "usb0_phy", "usb1_phy", "usb2_phy" and "usb2_hsic_12M" for sun8i-a83t
   * "usb0_phy", "usb1_phy", "usb2_phy" and "usb3_phy" for sun8i-h3
+  * "usb0_phy" and "usb3_phy" for sun50i-h6
 - resets : a list of phandle + reset specifier pairs
 - reset-names :
   * "usb0_reset"
   * "usb1_reset"
   * "usb2_reset" for sun4i, sun6i, sun7i, sun8i-a83t or sun8i-h3
-  * "usb3_reset" for sun8i-h3
+  * "usb3_reset" for sun8i-h3 and sun50i-h6
 
 Optional properties:
 - usb0_id_det-gpios : gpio phandle for reading the otg id pin value

Documentation/devicetree/bindings/phy/ti-phy-gmii-sel.txt

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diff --git a/Documentation/devicetree/bindings/phy/ti-phy-gmii-sel.txt b/Documentation/devicetree/bindings/phy/ti-phy-gmii-sel.txt
new file mode 100644
index 0000000..50ce9ae
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/ti-phy-gmii-sel.txt
@@ -0,0 +1,68 @@
+CPSW Port's Interface Mode Selection PHY Tree Bindings
+-----------------------------------------------
+
+TI am335x/am437x/dra7(am5)/dm814x CPSW3G Ethernet Subsystem supports
+two 10/100/1000 Ethernet ports with selectable G/MII, RMII, and RGMII interfaces.
+The interface mode is selected by configuring the MII mode selection register(s)
+(GMII_SEL) in the System Control Module chapter (SCM). GMII_SEL register(s) and
+bit fields placement in SCM are different between SoCs while fields meaning
+is the same.
+                                               +--------------+
+        +-------------------------------+      |SCM           |
+        |                     CPSW      |      |  +---------+ |
+        |        +--------------------------------+gmii_sel | |
+        |        |                      |      |  +---------+ |
+        |   +----v---+     +--------+   |      +--------------+
+        |   |Port 1..<--+-->GMII/MII<------->
+        |   |        |  |  |        |   |
+        |   +--------+  |  +--------+   |
+        |               |               |
+        |               |  +--------+   |
+        |               |  | RMII   <------->
+        |               +-->        |   |
+        |               |  +--------+   |
+        |               |               |
+        |               |  +--------+   |
+        |               |  | RGMII  <------->
+        |               +-->        |   |
+        |                  +--------+   |
+        +-------------------------------+
+
+CPSW Port's Interface Mode Selection PHY describes MII interface mode between
+CPSW Port and Ethernet PHY which depends on Eth PHY and board configuration.
+
+CPSW Port's Interface Mode Selection PHY device should defined as child device
+of SCM node (scm_conf) and can be attached to each CPSW port node using standard
+PHY bindings (See phy/phy-bindings.txt).
+
+Required properties:
+- compatible		: Should be "ti,am3352-phy-gmii-sel" for am335x platform
+			  "ti,dra7xx-phy-gmii-sel" for dra7xx/am57xx platform
+			  "ti,am43xx-phy-gmii-sel" for am43xx platform
+			  "ti,dm814-phy-gmii-sel" for dm814x platform
+- reg			: Address and length of the register set for the device
+- #phy-cells		: must be 2.
+			  cell 1 - CPSW port number (starting from 1)
+			  cell 2 - RMII refclk mode
+
+Examples:
+	phy_gmii_sel: phy-gmii-sel {
+		compatible = "ti,am3352-phy-gmii-sel";
+		reg = <0x650 0x4>;
+		#phy-cells = <2>;
+	};
+
+	mac: ethernet@4a100000 {
+		compatible = "ti,am335x-cpsw","ti,cpsw";
+		...
+
+		cpsw_emac0: slave@4a100200 {
+			...
+			phys = <&phy_gmii_sel 1 1>;
+		};
+
+		cpsw_emac1: slave@4a100300 {
+			...
+			phys = <&phy_gmii_sel 2 1>;
+		};
+	};

Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt

View file

diff --git a/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt b/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt
index 529e518..adae823 100644
--- a/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt
+++ b/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt
@@ -80,15 +80,19 @@ Optional properties:
   controller. It's expected that a mux state of 0 indicates device mode and a
   mux state of 1 indicates host mode.
 - mux-control-names: Shall be "usb_switch" if mux-controls is specified.
-- pinctrl-names: Names for optional pin modes in "default", "host", "device"
+- pinctrl-names: Names for optional pin modes in "default", "host", "device".
+  In case of HSIC-mode, "idle" and "active" pin modes are mandatory. In this
+  case, the "idle" state needs to pull down the data and strobe pin
+  and the "active" state needs to pull up the strobe pin.
 - pinctrl-n: alternate pin modes
 
 i.mx specific properties
 - fsl,usbmisc: phandler of non-core register device, with one
   argument that indicate usb controller index
 - disable-over-current: disable over current detect
-- over-current-active-high: over current signal polarity is high active,
-  typically over current signal polarity is low active.
+- over-current-active-low: over current signal polarity is active low.
+- over-current-active-high: over current signal polarity is active high.
+  It's recommended to specify the over current polarity.
 - external-vbus-divider: enables off-chip resistor divider for Vbus
 
 Example:
@@ -111,3 +115,29 @@ Example:
 		mux-controls = <&usb_switch>;
 		mux-control-names = "usb_switch";
 	};
+
+Example for HSIC:
+
+	usb@2184400 {
+		compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
+		reg = <0x02184400 0x200>;
+		interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clks IMX6QDL_CLK_USBOH3>;
+		fsl,usbphy = <&usbphynop1>;
+		fsl,usbmisc = <&usbmisc 2>;
+		phy_type = "hsic";
+		dr_mode = "host";
+		ahb-burst-config = <0x0>;
+		tx-burst-size-dword = <0x10>;
+		rx-burst-size-dword = <0x10>;
+		pinctrl-names = "idle", "active";
+		pinctrl-0 = <&pinctrl_usbh2_idle>;
+		pinctrl-1 = <&pinctrl_usbh2_active>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		usbnet: smsc@1 {
+			compatible = "usb424,9730";
+			reg = <1>;
+		};
+	};

Documentation/devicetree/bindings/usb/dwc3.txt

View file

diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt
index 636630f..8e5265e 100644
--- a/Documentation/devicetree/bindings/usb/dwc3.txt
+++ b/Documentation/devicetree/bindings/usb/dwc3.txt
@@ -37,7 +37,11 @@ Optional properties:
  - phy-names: from the *Generic PHY* bindings; supported names are "usb2-phy"
 	or "usb3-phy".
  - resets: a single pair of phandle and reset specifier
+ - snps,usb2-lpm-disable: indicate if we don't want to enable USB2 HW LPM
  - snps,usb3_lpm_capable: determines if platform is USB3 LPM capable
+ - snps,dis-start-transfer-quirk: when set, disable isoc START TRANSFER command
+			failure SW work-around for DWC_usb31 version 1.70a-ea06
+			and prior.
  - snps,disable_scramble_quirk: true when SW should disable data scrambling.
 	Only really useful for FPGA builds.
  - snps,has-lpm-erratum: true when DWC3 was configured with LPM Erratum enabled

Documentation/driver-api/usb/index.rst

View file

diff --git a/Documentation/driver-api/usb/index.rst b/Documentation/driver-api/usb/index.rst
index 8fe995a..cfa8797 100644
--- a/Documentation/driver-api/usb/index.rst
+++ b/Documentation/driver-api/usb/index.rst
@@ -19,6 +19,7 @@ Linux USB API
    dwc3
    writing_musb_glue_layer
    typec
+   typec_bus
    usb3-debug-port
 
 .. only::  subproject and html

Documentation/driver-api/usb/typec.rst

View file

diff --git a/Documentation/driver-api/usb/typec.rst b/Documentation/driver-api/usb/typec.rst
index 48ff580..201163d 100644
--- a/Documentation/driver-api/usb/typec.rst
+++ b/Documentation/driver-api/usb/typec.rst
@@ -1,3 +1,4 @@
+.. _typec:
 
 USB Type-C connector class
 ==========================

Documentation/driver-api/usb/typec_bus.rst

View file

diff --git a/Documentation/driver-api/usb/typec_bus.rst b/Documentation/driver-api/usb/typec_bus.rst
index d5eec17..f47a69b 100644
--- a/Documentation/driver-api/usb/typec_bus.rst
+++ b/Documentation/driver-api/usb/typec_bus.rst
@@ -13,10 +13,10 @@ every alternate mode, so every alternate mode will need a custom driver.
 USB Type-C bus allows binding a driver to the discovered partner alternate
 modes by using the SVID and the mode number.
 
-USB Type-C Connector Class provides a device for every alternate mode a port
-supports, and separate device for every alternate mode the partner supports.
-The drivers for the alternate modes are bound to the partner alternate mode
-devices, and the port alternate mode devices must be handled by the port
+:ref:`USB Type-C Connector Class <typec>` provides a device for every alternate
+mode a port supports, and separate device for every alternate mode the partner
+supports. The drivers for the alternate modes are bound to the partner alternate
+mode devices, and the port alternate mode devices must be handled by the port
 drivers.
 
 When a new partner alternate mode device is registered, it is linked to the
@@ -46,7 +46,7 @@ enter any modes on their own.
 ``->vdm`` is the most important callback in the operation callbacks vector. It
 will be used to deliver all the SVID specific commands from the partner to the
 alternate mode driver, and vice versa in case of port drivers. The drivers send
-the SVID specific commands to each other using :c:func:`typec_altmode_vmd()`.
+the SVID specific commands to each other using :c:func:`typec_altmode_vdm()`.
 
 If the communication with the partner using the SVID specific commands results
 in need to reconfigure the pins on the connector, the alternate mode driver
@@ -67,15 +67,15 @@ Type-C Specification, and also put the connector back to ``TYPEC_STATE_USB``
 after the mode has been exited.
 
 An example of working definitions for SVID specific pin configurations would
-look like this:
+look like this::
 
-enum {
-	ALTMODEX_CONF_A = TYPEC_STATE_MODAL,
-	ALTMODEX_CONF_B,
-	...
-};
+    enum {
+        ALTMODEX_CONF_A = TYPEC_STATE_MODAL,
+        ALTMODEX_CONF_B,
+        ...
+    };
 
-Helper macro ``TYPEC_MODAL_STATE()`` can also be used:
+Helper macro ``TYPEC_MODAL_STATE()`` can also be used::
 
 #define ALTMODEX_CONF_A = TYPEC_MODAL_STATE(0);
 #define ALTMODEX_CONF_B = TYPEC_MODAL_STATE(1);

Documentation/usb/authorization.txt

View file

diff --git a/Documentation/usb/authorization.txt b/Documentation/usb/authorization.txt
index c7e985f..f901ec7 100644
--- a/Documentation/usb/authorization.txt
+++ b/Documentation/usb/authorization.txt
@@ -119,5 +119,5 @@ If a deauthorized interface will be authorized so the driver probing must
 be triggered manually by writing INTERFACE to /sys/bus/usb/drivers_probe
 
 For drivers that need multiple interfaces all needed interfaces should be
-authroized first. After that the drivers should be probed.
+authorized first. After that the drivers should be probed.
 This avoids side effects.

MAINTAINERS

View file

diff --git a/MAINTAINERS b/MAINTAINERS
index 67e448e..8ea5ae3 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6310,6 +6310,7 @@ T:	git git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy.git
 S:	Supported
 F:	drivers/phy/
 F:	include/linux/phy/
+F:	Documentation/devicetree/bindings/phy/
 
 GENERIC PINCTRL I2C DEMULTIPLEXER DRIVER
 M:	Wolfram Sang <[email protected]>

drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c

View file

diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
index f1dab0b..6a059d6 100644
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
@@ -1165,28 +1165,13 @@ static void mvpp22_gop_setup_irq(struct mvpp2_port *port)
  */
 static int mvpp22_comphy_init(struct mvpp2_port *port)
 {
-	enum phy_mode mode;
 	int ret;
 
 	if (!port->comphy)
 		return 0;
 
-	switch (port->phy_interface) {
-	case PHY_INTERFACE_MODE_SGMII:
-	case PHY_INTERFACE_MODE_1000BASEX:
-		mode = PHY_MODE_SGMII;
-		break;
-	case PHY_INTERFACE_MODE_2500BASEX:
-		mode = PHY_MODE_2500SGMII;
-		break;
-	case PHY_INTERFACE_MODE_10GKR:
-		mode = PHY_MODE_10GKR;
-		break;
-	default:
-		return -EINVAL;
-	}
-
-	ret = phy_set_mode(port->comphy, mode);
+	ret = phy_set_mode_ext(port->comphy, PHY_MODE_ETHERNET,
+			       port->phy_interface);
 	if (ret)
 		return ret;
 

drivers/net/ethernet/mscc/ocelot.c

View file

diff --git a/drivers/net/ethernet/mscc/ocelot.c b/drivers/net/ethernet/mscc/ocelot.c
index 0dca2fa..215a453 100644
--- a/drivers/net/ethernet/mscc/ocelot.c
+++ b/drivers/net/ethernet/mscc/ocelot.c
@@ -471,7 +471,6 @@ static int ocelot_port_open(struct net_device *dev)
 {
 	struct ocelot_port *port = netdev_priv(dev);
 	struct ocelot *ocelot = port->ocelot;
-	enum phy_mode phy_mode;
 	int err;
 
 	/* Enable receiving frames on the port, and activate auto-learning of
@@ -483,12 +482,8 @@ static int ocelot_port_open(struct net_device *dev)
 			 ANA_PORT_PORT_CFG, port->chip_port);
 
 	if (port->serdes) {
-		if (port->phy_mode == PHY_INTERFACE_MODE_SGMII)
-			phy_mode = PHY_MODE_SGMII;
-		else
-			phy_mode = PHY_MODE_QSGMII;
-
-		err = phy_set_mode(port->serdes, phy_mode);
+		err = phy_set_mode_ext(port->serdes, PHY_MODE_ETHERNET,
+				       port->phy_mode);
 		if (err) {
 			netdev_err(dev, "Could not set mode of SerDes\n");
 			return err;

drivers/net/ethernet/ti/cpsw.c

View file

diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index 0e8f61a..a591583 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -26,6 +26,7 @@
 #include <linux/netdevice.h>
 #include <linux/net_tstamp.h>
 #include <linux/phy.h>
+#include <linux/phy/phy.h>
 #include <linux/workqueue.h>
 #include <linux/delay.h>
 #include <linux/pm_runtime.h>
@@ -387,6 +388,7 @@ struct cpsw_slave_data {
 	int		phy_if;
 	u8		mac_addr[ETH_ALEN];
 	u16		dual_emac_res_vlan;	/* Reserved VLAN for DualEMAC */
+	struct phy	*ifphy;
 };
 
 struct cpsw_platform_data {
@@ -1624,7 +1626,12 @@ static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
 	phy_start(slave->phy);
 
 	/* Configure GMII_SEL register */
-	cpsw_phy_sel(cpsw->dev, slave->phy->interface, slave->slave_num);
+	if (!IS_ERR(slave->data->ifphy))
+		phy_set_mode_ext(slave->data->ifphy, PHY_MODE_ETHERNET,
+				 slave->data->phy_if);
+	else
+		cpsw_phy_sel(cpsw->dev, slave->phy->interface,
+			     slave->slave_num);
 }
 
 static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
@@ -3274,6 +3281,16 @@ static int cpsw_probe_dt(struct cpsw_platform_data *data,
 		if (!of_node_name_eq(slave_node, "slave"))
 			continue;
 
+		slave_data->ifphy = devm_of_phy_get(&pdev->dev, slave_node,
+						    NULL);
+		if (!IS_ENABLED(CONFIG_TI_CPSW_PHY_SEL) &&
+		    IS_ERR(slave_data->ifphy)) {
+			ret = PTR_ERR(slave_data->ifphy);
+			dev_err(&pdev->dev,
+				"%d: Error retrieving port phy: %d\n", i, ret);
+			return ret;