Merge tag 'mips_5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux

d71e0644 · Linus Torvalds <[email protected]> · 2020-03-31 08:51:45 -07:00

Pull MIPS updates from Thomas Bogendoerfer:

 - loongson64 irq rework

 - dmi support loongson

 - replace setup_irq() by request_irq()

 - jazz cleanups

 - minor cleanups and fixes

* tag 'mips_5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (44 commits)
  MIPS: ralink: mt7621: Fix soc_device introduction
  MIPS: Exclude more dsemul code when CONFIG_MIPS_FP_SUPPORT=n
  MIPS/tlbex: Fix LDDIR usage in setup_pw() for Loongson-3
  MIPS: do not compile generic functions for CONFIG_CAVIUM_OCTEON_SOC
  MAINTAINERS: Update Loongson64 entry
  MIPS: Loongson64: Load built-in dtbs
  MIPS: Loongson64: Add generic dts
  dt-bindings: mips: Add loongson boards
  MIPS: Loongson64: Drop legacy IRQ code
  dt-bindings: interrupt-controller: Add Loongson-3 HTPIC
  irqchip: Add driver for Loongson-3 HyperTransport PIC controller
  dt-bindings: interrupt-controller: Add Loongson LIOINTC
  irqchip: loongson-liointc: Workaround LPC IRQ Errata
  irqchip: Add driver for Loongson I/O Local Interrupt Controller
  docs: mips: remove no longer needed au1xxx_ide.rst documentation
  MIPS: Alchemy: remove no longer used au1xxx_ide.h header
  ide: remove no longer used au1xxx-ide driver
  MIPS: Add support for Desktop Management Interface (DMI)
  firmware: dmi: Add macro SMBIOS_ENTRY_POINT_SCAN_START
  MIPS: ralink: mt7621: introduce 'soc_device' initialization
  ...

Commit: d71e064449a704a026fa032ec852d532f08aefa1
Parents: 58233ccf · ba155332

Merge commit. Changes below are compared with the first parent: 58233ccf.

Changes

136 files changed · +1369 −1924

File	Status	Add	Del	Content
Documentation/devicetree/bindings/interrupt-controller/loongson,htpic.yaml	added	+59	−0	View file
Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml	added	+93	−0	View file
Documentation/devicetree/bindings/mips/loongson/devices.yaml	added	+27	−0	View file
Documentation/mips/au1xxx_ide.rst	deleted	+0	−130	View before deletion
Documentation/mips/index.rst	modified	+0	−2	View file
MAINTAINERS	modified	+1	−0	View file
arch/mips/Kconfig	modified	+28	−3	View file
arch/mips/alchemy/common/time.c	modified	+3	−8	View file
arch/mips/ar7/irq.c	modified	+8	−8	View file
arch/mips/ath25/ar2315.c	modified	+3	−6	View file
arch/mips/ath25/ar5312.c	modified	+3	−6	View file
arch/mips/ath79/setup.c	modified	+1	−1	View file
arch/mips/bcm63xx/irq.c	modified	+16	−25	View file
arch/mips/bmips/setup.c	modified	+1	−1	View file
arch/mips/boot/dts/Makefile	modified	+1	−0	View file
arch/mips/boot/dts/ingenic/ci20.dts	modified	+19	−0	View file
arch/mips/boot/dts/loongson/Makefile	added	+4	−0	View file
arch/mips/boot/dts/loongson/loongson3-package.dtsi	added	+64	−0	View file
arch/mips/boot/dts/loongson/loongson3_4core_rs780e.dts	added	+25	−0	View file
arch/mips/boot/dts/loongson/loongson3_8core_rs780e.dts	added	+25	−0	View file
arch/mips/boot/dts/loongson/rs780e-pch.dtsi	added	+26	−0	View file
arch/mips/cavium-octeon/octeon-irq.c	modified	+3	−0	View file
arch/mips/cobalt/irq.c	modified	+10	−8	View file
arch/mips/configs/ar7_defconfig	modified	+0	−1	View file
arch/mips/configs/ath25_defconfig	modified	+0	−1	View file
arch/mips/configs/ath79_defconfig	modified	+0	−1	View file
arch/mips/configs/bcm63xx_defconfig	modified	+0	−2	View file
arch/mips/configs/bmips_be_defconfig	modified	+0	−2	View file
arch/mips/configs/bmips_stb_defconfig	modified	+0	−2	View file
arch/mips/configs/ci20_defconfig	modified	+21	−0	View file
arch/mips/configs/db1xxx_defconfig	modified	+0	−1	View file
arch/mips/configs/generic/board-ni169445.config	modified	+0	−1	View file
arch/mips/configs/jazz_defconfig	modified	+12	−255	View file
arch/mips/configs/lasat_defconfig	modified	+0	−2	View file
arch/mips/configs/lemote2f_defconfig	modified	+1	−1	View file
arch/mips/configs/loongson3_defconfig	modified	+3	−2	View file
arch/mips/configs/msp71xx_defconfig	modified	+0	−2	View file
arch/mips/configs/pnx8335_stb225_defconfig	modified	+0	−2	View file
arch/mips/configs/rb532_defconfig	modified	+0	−1	View file
arch/mips/configs/rt305x_defconfig	modified	+0	−1	View file
arch/mips/configs/xway_defconfig	modified	+0	−1	View file
arch/mips/dec/setup.c	modified	+24	−35	View file
arch/mips/emma/markeins/irq.c	modified	+10	−11	View file
arch/mips/fw/lib/cmdline.c	modified	+2	−0	View file
arch/mips/generic/init.c	modified	+1	−1	View file
arch/mips/include/asm/dmi.h	added	+20	−0	View file
arch/mips/include/asm/elf.h	modified	+3	−0	View file
arch/mips/include/asm/i8259.h	modified	+1	−0	View file
arch/mips/include/asm/mach-ar7/irq.h	modified	+1	−1	View file
arch/mips/include/asm/mach-ath79/irq.h	modified	+1	−1	View file
arch/mips/include/asm/mach-au1x00/au1xxx_ide.h	deleted	+0	−178	View before deletion
arch/mips/include/asm/mach-emma2rh/irq.h	modified	+1	−1	View file
arch/mips/include/asm/mach-ip27/irq.h	modified	+1	−1	View file
arch/mips/include/asm/mach-ip30/irq.h	modified	+1	−1	View file
arch/mips/include/asm/mach-lantiq/falcon/irq.h	modified	+1	−1	View file
arch/mips/include/asm/mach-lantiq/xway/irq.h	modified	+1	−1	View file
arch/mips/include/asm/mach-lasat/irq.h	modified	+1	−1	View file
arch/mips/include/asm/mach-loongson64/boot_param.h	modified	+2	−0	View file
arch/mips/include/asm/mach-loongson64/builtin_dtbs.h	added	+13	−0	View file
arch/mips/include/asm/mach-loongson64/irq.h	modified	+1	−29	View file
arch/mips/include/asm/mach-loongson64/loongson.h	modified	+1	−0	View file
arch/mips/include/asm/mach-malta/irq.h	modified	+1	−1	View file
arch/mips/include/asm/mach-pic32/irq.h	modified	+1	−1	View file
arch/mips/include/asm/mach-pistachio/irq.h	modified	+1	−1	View file
arch/mips/include/asm/mach-ralink/irq.h	modified	+1	−1	View file
arch/mips/include/asm/mach-rm/mc146818rtc.h	modified	+1	−1	View file
arch/mips/include/asm/mach-vr41xx/irq.h	modified	+1	−1	View file
arch/mips/include/asm/mach-xilfpga/irq.h	modified	+1	−1	View file
arch/mips/include/asm/processor.h	modified	+6	−6	View file
arch/mips/include/asm/sni.h	modified	+3	−1	View file
arch/mips/jazz/irq.c	modified	+3	−9	View file
arch/mips/jz4740/time.c	modified	+1	−1	View file
arch/mips/kernel/cevt-bcm1480.c	modified	+3	−8	View file
arch/mips/kernel/cevt-ds1287.c	modified	+2	−7	View file
arch/mips/kernel/cevt-gt641xx.c	modified	+2	−7	View file
arch/mips/kernel/cevt-r4k.c	modified	+4	−1	View file
arch/mips/kernel/cevt-sb1250.c	modified	+3	−8	View file
arch/mips/kernel/cevt-txx9.c	modified	+3	−8	View file
arch/mips/kernel/cpu-probe.c	modified	+18	−0	View file
arch/mips/kernel/i8253.c	modified	+4	−7	View file
arch/mips/kernel/process.c	modified	+8	−2	View file
arch/mips/kernel/rtlx-mt.c	modified	+1	−7	View file
arch/mips/kernel/setup.c	modified	+2	−0	View file
arch/mips/kernel/smp.c	modified	+12	−21	View file
arch/mips/kernel/vdso.c	modified	+15	−11	View file
arch/mips/lasat/interrupt.c	modified	+3	−7	View file
arch/mips/lib/delay.c	modified	+4	−0	View file
arch/mips/lib/memcpy.S	modified	+3	−0	View file
arch/mips/loongson2ef/common/bonito-irq.c	modified	+3	−6	View file
arch/mips/loongson2ef/common/cs5536/cs5536_mfgpt.c	modified	+3	−7	View file
arch/mips/loongson2ef/fuloong-2e/irq.c	modified	+8	−8	View file
arch/mips/loongson2ef/lemote-2f/irq.c	modified	+6	−14	View file
arch/mips/loongson32/common/irq.c	modified	+10	−11	View file
arch/mips/loongson32/common/time.c	modified	+4	−8	View file
arch/mips/loongson64/Makefile	modified	+1	−1	View file
arch/mips/loongson64/env.c	modified	+23	−0	View file
arch/mips/loongson64/hpet.c	modified	+3	−7	View file
arch/mips/loongson64/init.c	modified	+6	−0	View file
arch/mips/loongson64/irq.c	deleted	+0	−162	View before deletion
arch/mips/loongson64/numa.c	modified	+1	−1	View file
arch/mips/loongson64/setup.c	modified	+16	−0	View file
arch/mips/loongson64/smp.c	modified	+11	−17	View file
arch/mips/mm/c-octeon.c	modified	+9	−9	View file
arch/mips/mm/c-r3k.c	modified	+2	−2	View file
arch/mips/mm/c-r4k.c	modified	+38	−9	View file
arch/mips/mm/c-tx39.c	modified	+2	−2	View file
arch/mips/mm/tlbex.c	modified	+4	−1	View file
arch/mips/mti-malta/malta-int.c	modified	+3	−7	View file
arch/mips/netlogic/xlr/fmn.c	modified	+3	−8	View file
arch/mips/pic32/pic32mzda/time.c	modified	+2	−2	View file
arch/mips/pistachio/time.c	modified	+1	−1	View file
arch/mips/pmcs-msp71xx/msp_irq.c	modified	+12	−16	View file
arch/mips/pmcs-msp71xx/msp_smp.c	modified	+6	−16	View file
arch/mips/pmcs-msp71xx/msp_time.c	modified	+5	−3	View file
arch/mips/ralink/Kconfig	modified	+1	−0	View file
arch/mips/ralink/cevt-rt3352.c	modified	+8	−10	View file
arch/mips/ralink/mt7621.c	modified	+30	−0	View file
arch/mips/ralink/timer-gic.c	modified	+1	−1	View file
arch/mips/sgi-ip22/ip22-eisa.c	modified	+2	−8	View file
arch/mips/sgi-ip22/ip22-int.c	modified	+15	−34	View file
arch/mips/sgi-ip32/ip32-irq.c	modified	+6	−12	View file
arch/mips/sni/a20r.c	modified	+3	−1	View file
arch/mips/sni/irq.c	modified	+1	−7	View file
arch/mips/sni/pcit.c	modified	+6	−2	View file
arch/mips/sni/rm200.c	modified	+9	−14	View file
arch/mips/sni/time.c	modified	+3	−9	View file
arch/mips/vr41xx/common/irq.c	modified	+2	−7	View file
drivers/firmware/dmi_scan.c	modified	+5	−1	View file
drivers/ide/Kconfig	modified	+1	−19	View file
drivers/ide/Makefile	modified	+0	−2	View file
drivers/ide/au1xxx-ide.c	deleted	+0	−597	View before deletion
drivers/irqchip/Kconfig	modified	+19	−0	View file
drivers/irqchip/Makefile	modified	+2	−0	View file
drivers/irqchip/irq-loongson-htpic.c	added	+149	−0	View file
drivers/irqchip/irq-loongson-liointc.c	added	+271	−0	View file
drivers/video/fbdev/g364fb.c	modified	+3	−26	View file

Only the first 600 diff lines are shown. Download the complete patch.

Documentation/devicetree/bindings/interrupt-controller/loongson,htpic.yaml

View file

diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongson,htpic.yaml b/Documentation/devicetree/bindings/interrupt-controller/loongson,htpic.yaml
new file mode 100644
index 0000000..c8861cb
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/loongson,htpic.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/interrupt-controller/loongson,htpic.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Loongson-3 HyperTransport Interrupt Controller
+
+maintainers:
+  - Jiaxun Yang <[email protected]>
+
+allOf:
+  - $ref: /schemas/interrupt-controller.yaml#
+
+description: |
+  This interrupt controller is found in the Loongson-3 family of chips to transmit
+  interrupts from PCH PIC connected on HyperTransport bus.
+
+properties:
+  compatible:
+    const: loongson,htpic-1.0
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    minItems: 1
+    maxItems: 4
+    description: |
+      Four parent interrupts that receive chained interrupts.
+
+  interrupt-controller: true
+
+  '#interrupt-cells':
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - interrupt-controller
+  - '#interrupt-cells'
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/irq.h>
+    htintc: interrupt-controller@1fb000080 {
+      compatible = "loongson,htintc-1.0";
+      reg = <0xfb000080 0x40>;
+      interrupt-controller;
+      #interrupt-cells = <1>;
+
+      interrupt-parent = <&liointc>;
+      interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
+                    <25 IRQ_TYPE_LEVEL_HIGH>,
+                    <26 IRQ_TYPE_LEVEL_HIGH>,
+                    <27 IRQ_TYPE_LEVEL_HIGH>;
+    };
+...

Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml

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diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml b/Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml
new file mode 100644
index 0000000..9c6b91f
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml
@@ -0,0 +1,93 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/interrupt-controller/loongson,liointc.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Loongson Local I/O Interrupt Controller
+
+maintainers:
+  - Jiaxun Yang <[email protected]>
+
+description: |
+  This interrupt controller is found in the Loongson-3 family of chips as the primary
+  package interrupt controller which can route local I/O interrupt to interrupt lines
+  of cores.
+
+allOf:
+  - $ref: /schemas/interrupt-controller.yaml#
+
+properties:
+  compatible:
+    oneOf:
+      - const: loongson,liointc-1.0
+      - const: loongson,liointc-1.0a
+
+  reg:
+    maxItems: 1
+
+  interrupt-controller: true
+
+  interrupts:
+    description:
+      Interrupt source of the CPU interrupts.
+    minItems: 1
+    maxItems: 4
+
+  interrupt-names:
+    description: List of names for the parent interrupts.
+    items:
+      - const: int0
+      - const: int1
+      - const: int2
+      - const: int3
+    minItems: 1
+    maxItems: 4
+
+  '#interrupt-cells':
+    const: 2
+
+  'loongson,parent_int_map':
+    description: |
+      This property points how the children interrupts will be mapped into CPU
+      interrupt lines. Each cell refers to a parent interrupt line from 0 to 3
+      and each bit in the cell refers to a children interrupt fron 0 to 31.
+      If a CPU interrupt line didn't connected with liointc, then keep it's
+      cell with zero.
+    allOf:
+      - $ref: /schemas/types.yaml#/definitions/uint32-array
+      - items:
+          minItems: 4
+          maxItems: 4
+
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - interrupt-controller
+  - '#interrupt-cells'
+  - 'loongson,parent_int_map'
+
+
+examples:
+  - |
+    iointc: interrupt-controller@3ff01400 {
+      compatible = "loongson,liointc-1.0";
+      reg = <0x3ff01400 0x64>;
+
+      interrupt-controller;
+      #interrupt-cells = <2>;
+
+      interrupt-parent = <&cpuintc>;
+      interrupts = <2>, <3>;
+      interrupt-names = "int0", "int1";
+
+      loongson,parent_int_map = <0xf0ffffff>, /* int0 */
+                                <0x0f000000>, /* int1 */
+                                <0x00000000>, /* int2 */
+                                <0x00000000>; /* int3 */
+
+    };
+
+...

Documentation/devicetree/bindings/mips/loongson/devices.yaml

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diff --git a/Documentation/devicetree/bindings/mips/loongson/devices.yaml b/Documentation/devicetree/bindings/mips/loongson/devices.yaml
new file mode 100644
index 0000000..74ed4e3
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/loongson/devices.yaml
@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mips/loongson/devices.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Loongson based Platforms Device Tree Bindings
+
+maintainers:
+  - Jiaxun Yang <[email protected]>
+description: |
+  Devices with a Loongson CPU shall have the following properties.
+
+properties:
+  $nodename:
+    const: '/'
+  compatible:
+    oneOf:
+
+      - description: Generic Loongson3 Quad Core + RS780E
+        items:
+          - const: loongson,loongson3-4core-rs780e
+
+      - description: Generic Loongson3 Octa Core + RS780E
+        items:
+          - const: loongson,loongson3-8core-rs780e
+...

Documentation/mips/au1xxx_ide.rst

View before deletion

diff --git a/Documentation/mips/au1xxx_ide.rst b/Documentation/mips/au1xxx_ide.rst
deleted file mode 100644
index 2f9c2cf..0000000
--- a/Documentation/mips/au1xxx_ide.rst
+++ /dev/null
@@ -1,130 +0,0 @@
-.. include:: <isonum.txt>
-
-======================
-MIPS AU1XXX IDE driver
-======================
-
-Released 2005-07-15
-
-About
-=====
-
-This file describes the 'drivers/ide/au1xxx-ide.c', related files and the
-services they provide.
-
-If you are short in patience and just want to know how to add your hard disc to
-the white or black list, go to the 'ADD NEW HARD DISC TO WHITE OR BLACK LIST'
-section.
-
-
-License
-=======
-
-:Copyright: |copy| 2003-2005 AMD, Personal Connectivity Solutions
-
-This program is free software; you can redistribute it and/or modify it under
-the terms of the GNU General Public License as published by the Free Software
-Foundation; either version 2 of the License, or (at your option) any later
-version.
-
-THIS SOFTWARE IS PROVIDED ``AS IS`` AND ANY EXPRESS OR IMPLIED WARRANTIES,
-INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
-FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR
-BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-POSSIBILITY OF SUCH DAMAGE.
-
-You should have received a copy of the GNU General Public License along with
-this program; if not, write to the Free Software Foundation, Inc.,
-675 Mass Ave, Cambridge, MA 02139, USA.
-
-Note:
-      for more information, please refer "AMD Alchemy Au1200/Au1550 IDE
-      Interface and Linux Device Driver" Application Note.
-
-
-Files, Configs and Compatibility
-================================
-
-Two files are introduced:
-
-  a) 'arch/mips/include/asm/mach-au1x00/au1xxx_ide.h'
-     contains : struct _auide_hwif
-
-                - timing parameters for PIO mode 0/1/2/3/4
-                - timing parameters for MWDMA 0/1/2
-
-  b) 'drivers/ide/mips/au1xxx-ide.c'
-     contains the functionality of the AU1XXX IDE driver
-
-Following extra configs variables are introduced:
-
-  CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA
-	- enable the PIO+DBDMA mode
-  CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
-	- enable the MWDMA mode
-
-
-Supported IDE Modes
-===================
-
-The AU1XXX IDE driver supported all PIO modes - PIO mode 0/1/2/3/4 - and all
-MWDMA modes - MWDMA 0/1/2 -. There is no support for SWDMA and UDMA mode.
-
-To change the PIO mode use the program hdparm with option -p, e.g.
-'hdparm -p0 [device]' for PIO mode 0. To enable the MWDMA mode use the option
--X, e.g. 'hdparm -X32 [device]' for MWDMA mode 0.
-
-
-Performance Configurations
-==========================
-
-If the used system doesn't need USB support enable the following kernel
-configs::
-
-    CONFIG_IDE=y
-    CONFIG_BLK_DEV_IDE=y
-    CONFIG_IDE_GENERIC=y
-    CONFIG_BLK_DEV_IDEPCI=y
-    CONFIG_BLK_DEV_GENERIC=y
-    CONFIG_BLK_DEV_IDEDMA_PCI=y
-    CONFIG_BLK_DEV_IDE_AU1XXX=y
-    CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA=y
-    CONFIG_BLK_DEV_IDEDMA=y
-
-Also define 'IDE_AU1XXX_BURSTMODE' in 'drivers/ide/mips/au1xxx-ide.c' to enable
-the burst support on DBDMA controller.
-
-If the used system need the USB support enable the following kernel configs for
-high IDE to USB throughput.
-
-::
-
-    CONFIG_IDE_GENERIC=y
-    CONFIG_BLK_DEV_IDEPCI=y
-    CONFIG_BLK_DEV_GENERIC=y
-    CONFIG_BLK_DEV_IDEDMA_PCI=y
-    CONFIG_BLK_DEV_IDE_AU1XXX=y
-    CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA=y
-    CONFIG_BLK_DEV_IDEDMA=y
-
-Also undefine 'IDE_AU1XXX_BURSTMODE' in 'drivers/ide/mips/au1xxx-ide.c' to
-disable the burst support on DBDMA controller.
-
-
-Acknowledgments
-===============
-
-These drivers wouldn't have been done without the base of kernel 2.4.x AU1XXX
-IDE driver from AMD.
-
-Additional input also from:
-Matthias Lenk <[email protected]>
-
-Happy hacking!
-
-Enrico Walther <[email protected]>

Documentation/mips/index.rst

View file

diff --git a/Documentation/mips/index.rst b/Documentation/mips/index.rst
index a93c2f6..d5ad8c0 100644
--- a/Documentation/mips/index.rst
+++ b/Documentation/mips/index.rst
@@ -10,8 +10,6 @@ MIPS-specific Documentation
 
    ingenic-tcu
 
-   au1xxx_ide
-
 .. only::  subproject and html
 
    Indices

MAINTAINERS

View file

diff --git a/MAINTAINERS b/MAINTAINERS
index f114a90..c5ae60a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11202,6 +11202,7 @@ S:	Maintained
 F:	arch/mips/loongson64/
 F:	arch/mips/include/asm/mach-loongson64/
 F:	drivers/platform/mips/cpu_hwmon.c
+F:	drivers/irqchip/irq-loongson*
 F:	drivers/*/*loongson3*
 F:	drivers/*/*/*loongson3*
 

arch/mips/Kconfig

View file

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 66e9427..f8f3dbd 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -486,9 +486,11 @@ config MACH_LOONGSON64
 	select SYS_SUPPORTS_HIGHMEM
 	select SYS_SUPPORTS_LITTLE_ENDIAN
 	select SYS_SUPPORTS_ZBOOT
-	select LOONGSON_MC146818
 	select ZONE_DMA32
 	select NUMA
+	select COMMON_CLK
+	select USE_OF
+	select BUILTIN_DTB
 	help
 	  This enables the support of Loongson-2/3 family of machines.
 
@@ -973,6 +975,9 @@ config CAVIUM_OCTEON_SOC
 	select SYS_HAS_EARLY_PRINTK
 	select SYS_HAS_CPU_CAVIUM_OCTEON
 	select HAVE_PCI
+	select HAVE_PLAT_DELAY
+	select HAVE_PLAT_FW_INIT_CMDLINE
+	select HAVE_PLAT_MEMCPY
 	select ZONE_DMA32
 	select HOLES_IN_ZONE
 	select GPIOLIB
@@ -1229,6 +1234,15 @@ config GENERIC_ISA_DMA_SUPPORT_BROKEN
 	bool
 	select GENERIC_ISA_DMA
 
+config HAVE_PLAT_DELAY
+	bool
+
+config HAVE_PLAT_FW_INIT_CMDLINE
+	bool
+
+config HAVE_PLAT_MEMCPY
+	bool
+
 config ISA_DMA_API
 	bool
 
@@ -2676,7 +2690,7 @@ config NUMA
 	  Say Y to compile the kernel to support NUMA (Non-Uniform Memory
 	  Access).  This option improves performance on systems with more
 	  than two nodes; on two node systems it is generally better to
-	  leave it disabled; on single node systems disable this option
+	  leave it disabled; on single node systems leave this option
 	  disabled.
 
 config SYS_SUPPORTS_NUMA
@@ -2758,6 +2772,17 @@ config HW_PERF_EVENTS
 	  Enable hardware performance counter support for perf events. If
 	  disabled, perf events will use software events only.
 
+config DMI
+	bool "Enable DMI scanning"
+	depends on MACH_LOONGSON64
+	select DMI_SCAN_MACHINE_NON_EFI_FALLBACK
+	default y
+	help
+	  Enabled scanning of DMI to identify machine quirks. Say Y
+	  here unless you have verified that your setup is not
+	  affected by entries in the DMI blacklist. Required by PNP
+	  BIOS code.
+
 config SMP
 	bool "Multi-Processing support"
 	depends on SYS_SUPPORTS_SMP
@@ -3070,7 +3095,7 @@ endchoice
 choice
 	prompt "Kernel command line type" if !CMDLINE_OVERRIDE
 	default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
-					 !MIPS_MALTA && \
+					 !MACH_LOONGSON64 && !MIPS_MALTA && \
 					 !CAVIUM_OCTEON_SOC
 	default MIPS_CMDLINE_FROM_BOOTLOADER
 

arch/mips/alchemy/common/time.c

View file

diff --git a/arch/mips/alchemy/common/time.c b/arch/mips/alchemy/common/time.c
index 3a21a6a..d794ffb 100644
--- a/arch/mips/alchemy/common/time.c
+++ b/arch/mips/alchemy/common/time.c
@@ -72,13 +72,6 @@ static struct clock_event_device au1x_rtcmatch2_clockdev = {
 	.cpumask	= cpu_possible_mask,
 };
 
-static struct irqaction au1x_rtcmatch2_irqaction = {
-	.handler	= au1x_rtcmatch2_irq,
-	.flags		= IRQF_TIMER,
-	.name		= "timer",
-	.dev_id		= &au1x_rtcmatch2_clockdev,
-};
-
 static int __init alchemy_time_init(unsigned int m2int)
 {
 	struct clock_event_device *cd = &au1x_rtcmatch2_clockdev;
@@ -130,7 +123,9 @@ static int __init alchemy_time_init(unsigned int m2int)
 	cd->min_delta_ns = clockevent_delta2ns(9, cd);
 	cd->min_delta_ticks = 9;	/* ~0.28ms */
 	clockevents_register_device(cd);
-	setup_irq(m2int, &au1x_rtcmatch2_irqaction);
+	if (request_irq(m2int, au1x_rtcmatch2_irq, IRQF_TIMER, "timer",
+			&au1x_rtcmatch2_clockdev))
+		pr_err("Failed to register timer interrupt\n");
 
 	printk(KERN_INFO "Alchemy clocksource installed\n");
 

arch/mips/ar7/irq.c

View file

diff --git a/arch/mips/ar7/irq.c b/arch/mips/ar7/irq.c
index 93a331f..f0a7942 100644
--- a/arch/mips/ar7/irq.c
+++ b/arch/mips/ar7/irq.c
@@ -83,12 +83,6 @@ static struct irq_chip ar7_sec_irq_type = {
 	.irq_ack = ar7_ack_sec_irq,
 };
 
-static struct irqaction ar7_cascade_action = {
-	.handler = no_action,
-	.name = "AR7 cascade interrupt",
-	.flags = IRQF_NO_THREAD,
-};
-
 static void __init ar7_irq_init(int base)
 {
 	int i;
@@ -116,8 +110,14 @@ static void __init ar7_irq_init(int base)
 						 handle_level_irq);
 	}
 
-	setup_irq(2, &ar7_cascade_action);
-	setup_irq(ar7_irq_base, &ar7_cascade_action);
+	if (request_irq(2, no_action, IRQF_NO_THREAD, "AR7 cascade interrupt",
+			NULL))
+		pr_err("Failed to request irq 2 (AR7 cascade interrupt)\n");
+	if (request_irq(ar7_irq_base, no_action, IRQF_NO_THREAD,
+			"AR7 cascade interrupt", NULL)) {
+		pr_err("Failed to request irq %d (AR7 cascade interrupt)\n",
+		       ar7_irq_base);
+	}
 	set_c0_status(IE_IRQ0);
 }
 

arch/mips/ath25/ar2315.c

View file

diff --git a/arch/mips/ath25/ar2315.c b/arch/mips/ath25/ar2315.c
index 24f6191..e7b53e3 100644
--- a/arch/mips/ath25/ar2315.c
+++ b/arch/mips/ath25/ar2315.c
@@ -64,11 +64,6 @@ static irqreturn_t ar2315_ahb_err_handler(int cpl, void *dev_id)
 	return IRQ_HANDLED;
 }
 
-static struct irqaction ar2315_ahb_err_interrupt  = {
-	.handler	= ar2315_ahb_err_handler,
-	.name		= "ar2315-ahb-error",
-};
-
 static void ar2315_misc_irq_handler(struct irq_desc *desc)
 {
 	u32 pending = ar2315_rst_reg_read(AR2315_ISR) &
@@ -159,7 +154,9 @@ void __init ar2315_arch_init_irq(void)
 		panic("Failed to add IRQ domain");
 
 	irq = irq_create_mapping(domain, AR2315_MISC_IRQ_AHB);
-	setup_irq(irq, &ar2315_ahb_err_interrupt);
+	if (request_irq(irq, ar2315_ahb_err_handler, 0, "ar2315-ahb-error",
+			NULL))
+		pr_err("Failed to register ar2315-ahb-error interrupt\n");
 
 	irq_set_chained_handler_and_data(AR2315_IRQ_MISC,
 					 ar2315_misc_irq_handler, domain);

arch/mips/ath25/ar5312.c

View file

diff --git a/arch/mips/ath25/ar5312.c b/arch/mips/ath25/ar5312.c
index 47f3e98..42bf2af 100644
--- a/arch/mips/ath25/ar5312.c
+++ b/arch/mips/ath25/ar5312.c
@@ -68,11 +68,6 @@ static irqreturn_t ar5312_ahb_err_handler(int cpl, void *dev_id)
 	return IRQ_HANDLED;
 }
 
-static struct irqaction ar5312_ahb_err_interrupt  = {
-	.handler = ar5312_ahb_err_handler,
-	.name    = "ar5312-ahb-error",
-};
-
 static void ar5312_misc_irq_handler(struct irq_desc *desc)
 {
 	u32 pending = ar5312_rst_reg_read(AR5312_ISR) &
@@ -154,7 +149,9 @@ void __init ar5312_arch_init_irq(void)
 		panic("Failed to add IRQ domain");
 
 	irq = irq_create_mapping(domain, AR5312_MISC_IRQ_AHB_PROC);
-	setup_irq(irq, &ar5312_ahb_err_interrupt);
+	if (request_irq(irq, ar5312_ahb_err_handler, 0, "ar5312-ahb-error",
+			NULL))
+		pr_err("Failed to register ar5312-ahb-error interrupt\n");
 
 	irq_set_chained_handler_and_data(AR5312_IRQ_MISC,
 					 ar5312_misc_irq_handler, domain);

arch/mips/ath79/setup.c

View file

diff --git a/arch/mips/ath79/setup.c b/arch/mips/ath79/setup.c
index 484ee28..acb4fd6 100644
--- a/arch/mips/ath79/setup.c
+++ b/arch/mips/ath79/setup.c
@@ -15,7 +15,7 @@
 #include <linux/memblock.h>
 #include <linux/err.h>
 #include <linux/clk.h>
-#include <linux/clk-provider.h>
+#include <linux/of_clk.h>
 #include <linux/of_fdt.h>
 #include <linux/irqchip.h>
 

arch/mips/bcm63xx/irq.c

View file

diff --git a/arch/mips/bcm63xx/irq.c b/arch/mips/bcm63xx/irq.c
index ec694b9..2548013 100644
--- a/arch/mips/bcm63xx/irq.c
+++ b/arch/mips/bcm63xx/irq.c
@@ -399,26 +399,6 @@ static struct irq_chip bcm63xx_external_irq_chip = {
 	.irq_set_type	= bcm63xx_external_irq_set_type,
 };
 
-static struct irqaction cpu_ip2_cascade_action = {
-	.handler	= no_action,
-	.name		= "cascade_ip2",
-	.flags		= IRQF_NO_THREAD,
-};
-
-#ifdef CONFIG_SMP
-static struct irqaction cpu_ip3_cascade_action = {
-	.handler	= no_action,
-	.name		= "cascade_ip3",
-	.flags		= IRQF_NO_THREAD,
-};
-#endif
-
-static struct irqaction cpu_ext_cascade_action = {
-	.handler	= no_action,
-	.name		= "cascade_extirq",
-	.flags		= IRQF_NO_THREAD,
-};
-
 static void bcm63xx_init_irq(void)
 {
 	int irq_bits;
@@ -531,7 +511,7 @@ static void bcm63xx_init_irq(void)
 