Merge tag 'renesas-dt-fixes-for-v4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt

d95eabc7 · Arnd Bergmann <[email protected]> · 2016-07-21 14:40:28 +02:00

Merge "Renesas ARM Based SoC DT Fixes for v4.8" from Simon Horman:

* Corrections to r8a7792

* tag 'renesas-dt-fixes-for-v4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  ARM: dts: r8a7792: remove ADSP clock
  ARM: dts: r8a7792: add PLL1 divided by 2 clock

Commit: d95eabc7b8ee4c8ef471e8a97aa62d353b110880
Parents: 1b2d8b94 · e0c3f92a

Merge commit. Changes below are compared with the first parent: 1b2d8b94.

Changes

2 files changed · +8 −2

File	Status	Add	Del	Content
arch/arm/boot/dts/r8a7792.dtsi	modified	+8	−1	View file
include/dt-bindings/clock/r8a7792-clock.h	modified	+0	−1	View file

arch/arm/boot/dts/r8a7792.dtsi

View file

diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi
index 75256ef..3fd61d7 100644
--- a/arch/arm/boot/dts/r8a7792.dtsi
+++ b/arch/arm/boot/dts/r8a7792.dtsi
@@ -279,11 +279,18 @@
 			clocks = <&extal_clk>;
 			#clock-cells = <1>;
 			clock-output-names = "main", "pll0", "pll1", "pll3",
-					     "lb", "qspi", "z", "adsp";
+					     "lb", "qspi", "z";
 			#power-domain-cells = <0>;
 		};
 
 		/* Fixed factor clocks */
+		pll1_div2_clk: pll1_div2 {
+			compatible = "fixed-factor-clock";
+			clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
+			#clock-cells = <0>;
+			clock-div = <2>;
+			clock-mult = <1>;
+		};
 		zs_clk: zs {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R8A7792_CLK_PLL1>;

include/dt-bindings/clock/r8a7792-clock.h

View file

diff --git a/include/dt-bindings/clock/r8a7792-clock.h b/include/dt-bindings/clock/r8a7792-clock.h
index 89a5155..9a8b392 100644
--- a/include/dt-bindings/clock/r8a7792-clock.h
+++ b/include/dt-bindings/clock/r8a7792-clock.h
@@ -18,7 +18,6 @@
 #define R8A7792_CLK_LB			4
 #define R8A7792_CLK_QSPI		5
 #define R8A7792_CLK_Z			6
-#define R8A7792_CLK_ADSP		7
 
 /* MSTP0 */
 #define R8A7792_CLK_MSIOF0		0