Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus

e2464688 · Linus Torvalds <[email protected]> · 2016-01-24 12:50:56 -08:00

Pull MIPS updates from Ralf Baechle:
 "This is the main pull request for MIPS for 4.5 plus some 4.4 fixes.

  The executive summary:

   - ATH79 platform improvments, use DT bindings for the ATH79 USB PHY.
   - Avoid useless rebuilds for zboot.
   - jz4780: Add NEMC, BCH and NAND device tree nodes
   - Initial support for the MicroChip's DT platform.  As all the device
     drivers are missing this is still of limited use.
   - Some Loongson3 cleanups.
   - The unavoidable whitespace polishing.
   - Reduce clock skew when synchronizing the CPU cycle counters on CPU
     startup.
   - Add MIPS R6 fixes.
   - Lots of cleanups across arch/mips as fallout from KVM.
   - Lots of minor fixes and changes for IEEE 754-2008 support to the
     FPU emulator / fp-assist software.
   - Minor Ralink, BCM47xx and bcm963xx platform support improvments.
   - Support SMP on BCM63168"

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (84 commits)
  MIPS: zboot: Add support for serial debug using the PROM
  MIPS: zboot: Avoid useless rebuilds
  MIPS: BMIPS: Enable ARCH_WANT_OPTIONAL_GPIOLIB
  MIPS: bcm63xx: nvram: Remove unused bcm63xx_nvram_get_psi_size() function
  MIPS: bcm963xx: Update bcm_tag field image_sequence
  MIPS: bcm963xx: Move extended flash address to bcm_tag header file
  MIPS: bcm963xx: Move Broadcom BCM963xx image tag data structure
  MIPS: bcm63xx: nvram: Use nvram structure definition from header file
  MIPS: bcm963xx: Add Broadcom BCM963xx board nvram data structure
  MAINTAINERS: Add KVM for MIPS entry
  MIPS: KVM: Add missing newline to kvm_err()
  MIPS: Move KVM specific opcodes into asm/inst.h
  MIPS: KVM: Use cacheops.h definitions
  MIPS: Break down cacheops.h definitions
  MIPS: Use EXCCODE_ constants with set_except_vector()
  MIPS: Update trap codes
  MIPS: Move Cause.ExcCode trap codes to mipsregs.h
  MIPS: KVM: Make kvm_mips_{init,exit}() static
  MIPS: KVM: Refactor added offsetof()s
  MIPS: KVM: Convert EXPORT_SYMBOL to _GPL
  ...

Commit: e2464688b59c6ae9928f385dabf5355e30cff298
Parents: e1c10879 · 07d17f09

Merge commit. Changes below are compared with the first parent: e1c10879.

Changes

130 files changed · +4923 −676

File	Status	Add	Del	Content
Documentation/devicetree/bindings/interrupt-controller/microchip,pic32-evic.txt	added	+67	−0	View file
Documentation/devicetree/bindings/mips/pic32/microchip,pic32mzda.txt	added	+31	−0	View file
Documentation/devicetree/bindings/net/mediatek,mt7620-gsw.txt	added	+26	−0	View file
Documentation/devicetree/bindings/net/ralink,rt2880-net.txt	added	+61	−0	View file
Documentation/devicetree/bindings/net/ralink,rt3050-esw.txt	added	+32	−0	View file
Documentation/devicetree/bindings/phy/phy-ath79-usb.txt	added	+18	−0	View file
Documentation/kernel-parameters.txt	modified	+35	−0	View file
MAINTAINERS	modified	+22	−0	View file
arch/mips/Kbuild.platforms	modified	+1	−0	View file
arch/mips/Kconfig	modified	+16	−1	View file
arch/mips/Makefile	modified	+0	−10	View file
arch/mips/alchemy/common/gpiolib.c	modified	+3	−3	View file
arch/mips/ar7/gpio.c	modified	+1	−1	View file
arch/mips/ath79/common.h	modified	+0	−1	View file
arch/mips/ath79/irq.c	modified	+28	−33	View file
arch/mips/ath79/setup.c	modified	+1	−10	View file
arch/mips/bcm47xx/sprom.c	modified	+9	−3	View file
arch/mips/bcm63xx/nvram.c	modified	+3	−43	View file
arch/mips/bmips/setup.c	modified	+1	−0	View file
arch/mips/boot/compressed/Makefile	modified	+9	−6	View file
arch/mips/boot/compressed/uart-prom.c	added	+7	−0	View file
arch/mips/boot/dts/Makefile	modified	+1	−0	View file
arch/mips/boot/dts/brcm/bcm6328.dtsi	modified	+9	−0	View file
arch/mips/boot/dts/brcm/bcm6368.dtsi	modified	+22	−0	View file
arch/mips/boot/dts/ingenic/ci20.dts	modified	+64	−0	View file
arch/mips/boot/dts/ingenic/jz4780.dtsi	modified	+26	−0	View file
arch/mips/boot/dts/pic32/Makefile	added	+12	−0	View file
arch/mips/boot/dts/pic32/pic32mzda-clk.dtsi	added	+236	−0	View file
arch/mips/boot/dts/pic32/pic32mzda.dtsi	added	+281	−0	View file
arch/mips/boot/dts/pic32/pic32mzda_sk.dts	added	+151	−0	View file
arch/mips/boot/dts/qca/ar9132.dtsi	modified	+26	−0	View file
arch/mips/boot/dts/qca/ar9132_tl_wr1043nd_v1.dts	modified	+8	−0	View file
arch/mips/configs/pic32mzda_defconfig	added	+89	−0	View file
arch/mips/include/asm/cacheops.h	modified	+64	−42	View file
arch/mips/include/asm/cpu-features.h	modified	+7	−0	View file
arch/mips/include/asm/cpu.h	modified	+2	−0	View file
arch/mips/include/asm/elf.h	modified	+11	−4	View file
arch/mips/include/asm/fpu_emulator.h	modified	+1	−1	View file
arch/mips/include/asm/io.h	modified	+1	−0	View file
arch/mips/include/asm/irqflags.h	modified	+0	−30	View file
arch/mips/include/asm/kvm_host.h	modified	+1	−38	View file
arch/mips/include/asm/mach-ath79/ath79.h	modified	+1	−0	View file
arch/mips/include/asm/mach-bcm63xx/bcm63xx_nvram.h	modified	+0	−2	View file
arch/mips/include/asm/mach-pic32/cpu-feature-overrides.h	added	+32	−0	View file
arch/mips/include/asm/mach-pic32/irq.h	added	+22	−0	View file
arch/mips/include/asm/mach-pic32/pic32.h	added	+44	−0	View file
arch/mips/include/asm/mach-pic32/spaces.h	added	+24	−0	View file
arch/mips/include/asm/mach-ralink/irq.h	added	+9	−0	View file
arch/mips/include/asm/mach-ralink/mt7621.h	added	+38	−0	View file
arch/mips/include/asm/mach-ralink/mt7621/cpu-feature-overrides.h	added	+65	−0	View file
arch/mips/include/asm/mips-cm.h	modified	+4	−0	View file
arch/mips/include/asm/mips-r2-to-r6-emul.h	modified	+1	−1	View file
arch/mips/include/asm/mipsregs.h	modified	+34	−0	View file
arch/mips/include/asm/page.h	modified	+1	−1	View file
arch/mips/include/asm/pgtable.h	modified	+2	−2	View file
arch/mips/include/uapi/asm/inst.h	modified	+12	−3	View file
arch/mips/kernel/cpu-bugs64.c	modified	+4	−4	View file
arch/mips/kernel/cpu-probe.c	modified	+161	−0	View file
arch/mips/kernel/elf.c	modified	+87	−15	View file
arch/mips/kernel/gpio_txx9.c	modified	+1	−1	View file
arch/mips/kernel/ptrace.c	modified	+0	−3	View file
arch/mips/kernel/setup.c	modified	+1	−1	View file
arch/mips/kernel/smp-cps.c	modified	+3	−0	View file
arch/mips/kernel/sync-r4k.c	modified	+8	−24	View file
arch/mips/kernel/traps.c	modified	+26	−26	View file
arch/mips/kvm/callback.c	modified	+1	−1	View file
arch/mips/kvm/dyntrans.c	modified	+3	−7	View file
arch/mips/kvm/emulate.c	modified	+50	−66	View file
arch/mips/kvm/interrupt.c	modified	+4	−4	View file
arch/mips/kvm/locore.S	modified	+6	−6	View file
arch/mips/kvm/mips.c	modified	+19	−19	View file
arch/mips/kvm/opcode.h	deleted	+0	−22	View before deletion
arch/mips/kvm/tlb.c	modified	+20	−57	View file
arch/mips/kvm/trap_emul.c	modified	+0	−1	View file
arch/mips/lib/mips-atomic.c	modified	+1	−29	View file
arch/mips/loongson64/Platform	modified	+21	−0	View file
arch/mips/loongson64/loongson-3/hpet.c	modified	+7	−3	View file
arch/mips/loongson64/loongson-3/smp.c	modified	+13	−7	View file
arch/mips/math-emu/cp1emu.c	modified	+4	−0	View file
arch/mips/math-emu/dp_simple.c	modified	+25	−13	View file
arch/mips/math-emu/dp_tint.c	modified	+6	−3	View file
arch/mips/math-emu/dp_tlong.c	modified	+6	−3	View file
arch/mips/math-emu/dsemul.c	modified	+52	−25	View file
arch/mips/math-emu/ieee754.c	modified	+4	−2	View file
arch/mips/math-emu/ieee754.h	modified	+29	−13	View file
arch/mips/math-emu/ieee754dp.c	modified	+10	−2	View file
arch/mips/math-emu/ieee754int.h	modified	+6	−6	View file
arch/mips/math-emu/ieee754sp.c	modified	+10	−2	View file
arch/mips/math-emu/sp_fdp.c	modified	+8	−5	View file
arch/mips/math-emu/sp_simple.c	modified	+25	−13	View file
arch/mips/math-emu/sp_tint.c	modified	+6	−3	View file
arch/mips/math-emu/sp_tlong.c	modified	+6	−3	View file
arch/mips/mm/tlbex.c	modified	+1	−1	View file
arch/mips/pci/Makefile	modified	+1	−0	View file
arch/mips/pci/pci-mt7620.c	added	+426	−0	View file
arch/mips/pic32/Kconfig	added	+51	−0	View file
arch/mips/pic32/Makefile	added	+6	−0	View file
arch/mips/pic32/Platform	added	+7	−0	View file
arch/mips/pic32/common/Makefile	added	+5	−0	View file
arch/mips/pic32/common/irq.c	added	+21	−0	View file
arch/mips/pic32/common/reset.c	added	+62	−0	View file
arch/mips/pic32/pic32mzda/Makefile	added	+9	−0	View file
arch/mips/pic32/pic32mzda/config.c	added	+126	−0	View file
arch/mips/pic32/pic32mzda/early_clk.c	added	+106	−0	View file
arch/mips/pic32/pic32mzda/early_console.c	added	+171	−0	View file
arch/mips/pic32/pic32mzda/early_pin.c	added	+275	−0	View file
arch/mips/pic32/pic32mzda/early_pin.h	added	+241	−0	View file
arch/mips/pic32/pic32mzda/init.c	added	+156	−0	View file
arch/mips/pic32/pic32mzda/pic32mzda.h	added	+29	−0	View file
arch/mips/pic32/pic32mzda/time.c	added	+73	−0	View file
arch/mips/ralink/Kconfig	modified	+16	−0	View file
arch/mips/ralink/Makefile	modified	+9	−1	View file
arch/mips/ralink/Platform	modified	+5	−0	View file
arch/mips/ralink/irq-gic.c	added	+25	−0	View file
arch/mips/ralink/mt7620.c	modified	+55	−32	View file
arch/mips/ralink/mt7621.c	added	+226	−0	View file
arch/mips/ralink/rt288x.c	modified	+1	−1	View file
arch/mips/ralink/rt305x.c	modified	+1	−0	View file
arch/mips/ralink/rt3883.c	modified	+1	−0	View file
arch/mips/ralink/timer-gic.c	added	+24	−0	View file
arch/mips/rb532/gpio.c	modified	+1	−1	View file
arch/mips/txx9/generic/setup.c	modified	+1	−1	View file
drivers/irqchip/Kconfig	modified	+5	−0	View file
drivers/irqchip/Makefile	modified	+1	−0	View file
drivers/irqchip/irq-pic32-evic.c	added	+324	−0	View file
drivers/mtd/bcm63xxpart.c	modified	+3	−5	View file
fs/binfmt_elf.c	modified	+5	−1	View file
include/linux/bcm963xx_nvram.h	added	+112	−0	View file
arch/mips/include/asm/mach-bcm63xx/bcm963xx_tag.h → include/linux/bcm963xx_tag.h	renamed	+15	−9	View file
include/linux/platform_data/sdhci-pic32.h	added	+22	−0	View file

Only the first 600 diff lines are shown. Download the complete patch.

Documentation/devicetree/bindings/interrupt-controller/microchip,pic32-evic.txt

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diff --git a/Documentation/devicetree/bindings/interrupt-controller/microchip,pic32-evic.txt b/Documentation/devicetree/bindings/interrupt-controller/microchip,pic32-evic.txt
new file mode 100644
index 0000000..c3a1b37
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/microchip,pic32-evic.txt
@@ -0,0 +1,67 @@
+Microchip PIC32 Interrupt Controller
+====================================
+
+The Microchip PIC32 contains an Enhanced Vectored Interrupt Controller (EVIC).
+It handles all internal and external interrupts. This controller exists outside
+of the CPU and is the arbitrator of all interrupts (including interrupts from
+the CPU itself) before they are presented to the CPU.
+
+External interrupts have a software configurable edge polarity. Non external
+interrupts have a type and polarity that is determined by the source of the
+interrupt.
+
+Required properties
+-------------------
+
+- compatible: Should be "microchip,pic32mzda-evic"
+- reg: Specifies physical base address and size of register range.
+- interrupt-controller: Identifies the node as an interrupt controller.
+- #interrupt cells: Specifies the number of cells used to encode an interrupt
+  source connected to this controller. The value shall be 2 and interrupt
+  descriptor shall have the following format:
+
+	<hw_irq irq_type>
+
+  hw_irq - represents the hardware interrupt number as in the data sheet.
+  irq_type - is used to describe the type and polarity of an interrupt. For
+  internal interrupts use IRQ_TYPE_EDGE_RISING for non persistent interrupts and
+  IRQ_TYPE_LEVEL_HIGH for persistent interrupts. For external interrupts use
+  IRQ_TYPE_EDGE_RISING or IRQ_TYPE_EDGE_FALLING to select the desired polarity.
+
+Optional properties
+-------------------
+- microchip,external-irqs: u32 array of external interrupts with software
+  polarity configuration. This array corresponds to the bits in the INTCON
+  SFR.
+
+Example
+-------
+
+evic: interrupt-controller@1f810000 {
+	compatible = "microchip,pic32mzda-evic";
+	interrupt-controller;
+	#interrupt-cells = <2>;
+	reg = <0x1f810000 0x1000>;
+	microchip,external-irqs = <3 8 13 18 23>;
+};
+
+Each device/peripheral must request its interrupt line with the associated type
+and polarity.
+
+Internal interrupt DTS snippet
+------------------------------
+
+device@1f800000 {
+	...
+	interrupts = <113 IRQ_TYPE_LEVEL_HIGH>;
+	...
+};
+
+External interrupt DTS snippet
+------------------------------
+
+device@1f800000 {
+	...
+	interrupts = <3 IRQ_TYPE_EDGE_RISING>;
+	...
+};

Documentation/devicetree/bindings/mips/pic32/microchip,pic32mzda.txt

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diff --git a/Documentation/devicetree/bindings/mips/pic32/microchip,pic32mzda.txt b/Documentation/devicetree/bindings/mips/pic32/microchip,pic32mzda.txt
new file mode 100644
index 0000000..1c8dbc4
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/pic32/microchip,pic32mzda.txt
@@ -0,0 +1,31 @@
+* Microchip PIC32MZDA Platforms
+
+PIC32MZDA Starter Kit
+Required root node properties:
+    - compatible = "microchip,pic32mzda-sk", "microchip,pic32mzda"
+
+CPU nodes:
+----------
+A "cpus" node is required.  Required properties:
+ - #address-cells: Must be 1.
+ - #size-cells: Must be 0.
+A CPU sub-node is also required.  Required properties:
+ - device_type: Must be "cpu".
+ - compatible: Must be "mti,mips14KEc".
+Example:
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "mti,mips14KEc";
+		};
+	};
+
+Boot protocol
+--------------
+In accordance with Unified Hosting Interface Reference Manual (MD01069), the
+bootloader must pass the following arguments to the kernel:
+ - $a0: -2.
+ - $a1: KSEG0 address of the flattened device-tree blob.

Documentation/devicetree/bindings/net/mediatek,mt7620-gsw.txt

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diff --git a/Documentation/devicetree/bindings/net/mediatek,mt7620-gsw.txt b/Documentation/devicetree/bindings/net/mediatek,mt7620-gsw.txt
new file mode 100644
index 0000000..aa63130
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/mediatek,mt7620-gsw.txt
@@ -0,0 +1,26 @@
+Mediatek Gigabit Switch
+=======================
+
+The mediatek gigabit switch can be found on Mediatek SoCs (mt7620, mt7621).
+
+Required properties:
+- compatible: Should be "mediatek,mt7620-gsw" or "mediatek,mt7621-gsw"
+- reg: Address and length of the register set for the device
+- interrupt-parent: Should be the phandle for the interrupt controller
+  that services interrupts for this device
+- interrupts: Should contain the gigabit switches interrupt
+- resets: Should contain the gigabit switches resets
+- reset-names: Should contain the reset names "gsw"
+
+Example:
+
+gsw@10110000 {
+	compatible = "ralink,mt7620-gsw";
+	reg = <0x10110000 8000>;
+
+	resets = <&rstctrl 23>;
+	reset-names = "gsw";
+
+	interrupt-parent = <&intc>;
+	interrupts = <17>;
+};

Documentation/devicetree/bindings/net/ralink,rt2880-net.txt

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diff --git a/Documentation/devicetree/bindings/net/ralink,rt2880-net.txt b/Documentation/devicetree/bindings/net/ralink,rt2880-net.txt
new file mode 100644
index 0000000..88b095d
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/ralink,rt2880-net.txt
@@ -0,0 +1,61 @@
+Ralink Frame Engine Ethernet controller
+=======================================
+
+The Ralink frame engine ethernet controller can be found on Ralink and
+Mediatek SoCs (RT288x, RT3x5x, RT366x, RT388x, rt5350, mt7620, mt7621, mt76x8).
+
+Depending on the SoC, there is a number of ports connected to the CPU port
+directly and/or via a (gigabit-)switch.
+
+* Ethernet controller node
+
+Required properties:
+- compatible: Should be one of "ralink,rt2880-eth", "ralink,rt3050-eth",
+  "ralink,rt3050-eth", "ralink,rt3883-eth", "ralink,rt5350-eth",
+  "mediatek,mt7620-eth", "mediatek,mt7621-eth"
+- reg: Address and length of the register set for the device
+- interrupt-parent: Should be the phandle for the interrupt controller
+  that services interrupts for this device
+- interrupts: Should contain the frame engines interrupt
+- resets: Should contain the frame engines resets
+- reset-names: Should contain the reset names "fe". If a switch is present
+  "esw" is also required.
+
+
+* Ethernet port node
+
+Required properties:
+- compatible: Should be "ralink,eth-port"
+- reg: The number of the physical port
+- phy-handle: reference to the node describing the phy
+
+Example:
+
+mdio-bus {
+	...
+	phy0: ethernet-phy@0 {
+		phy-mode = "mii";
+		reg = <0>;
+	};
+};
+
+ethernet@400000 {
+	compatible = "ralink,rt2880-eth";
+	reg = <0x00400000 10000>;
+
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	resets = <&rstctrl 18>;
+	reset-names = "fe";
+
+	interrupt-parent = <&cpuintc>;
+	interrupts = <5>;
+
+	port@0 {
+		compatible = "ralink,eth-port";
+		reg = <0>;
+		phy-handle = <&phy0>;
+	};
+
+};

Documentation/devicetree/bindings/net/ralink,rt3050-esw.txt

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diff --git a/Documentation/devicetree/bindings/net/ralink,rt3050-esw.txt b/Documentation/devicetree/bindings/net/ralink,rt3050-esw.txt
new file mode 100644
index 0000000..2e79bd3
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/ralink,rt3050-esw.txt
@@ -0,0 +1,32 @@
+Ralink Fast Ethernet Embedded Switch
+====================================
+
+The ralink fast ethernet embedded switch can be found on Ralink and Mediatek
+SoCs (RT3x5x, RT5350, MT76x8).
+
+Required properties:
+- compatible: Should be "ralink,rt3050-esw"
+- reg: Address and length of the register set for the device
+- interrupt-parent: Should be the phandle for the interrupt controller
+  that services interrupts for this device
+- interrupts: Should contain the embedded switches interrupt
+- resets: Should contain the embedded switches resets
+- reset-names: Should contain the reset names "esw"
+
+Optional properties:
+- ralink,portmap: can be used to choose if the default switch setup is
+  llllw or wllll
+- ralink,led_polarity: override the active high/low settings of the leds
+
+Example:
+
+esw@10110000 {
+	compatible = "ralink,rt3050-esw";
+	reg = <0x10110000 8000>;
+
+	resets = <&rstctrl 23>;
+	reset-names = "esw";
+
+	interrupt-parent = <&intc>;
+	interrupts = <17>;
+};

Documentation/devicetree/bindings/phy/phy-ath79-usb.txt

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diff --git a/Documentation/devicetree/bindings/phy/phy-ath79-usb.txt b/Documentation/devicetree/bindings/phy/phy-ath79-usb.txt
new file mode 100644
index 0000000..cafe219
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-ath79-usb.txt
@@ -0,0 +1,18 @@
+* Atheros AR71XX/9XXX USB PHY
+
+Required properties:
+- compatible: "qca,ar7100-usb-phy"
+- #phys-cells: should be 0
+- reset-names: "usb-phy"[, "usb-suspend-override"]
+- resets: references to the reset controllers
+
+Example:
+
+	usb-phy {
+		compatible = "qca,ar7100-usb-phy";
+
+		reset-names = "usb-phy", "usb-suspend-override";
+		resets = <&rst 4>, <&rst 3>;
+
+		#phy-cells = <0>;
+	};

Documentation/kernel-parameters.txt

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diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt
index cfb2c0f..87d40a7 100644
--- a/Documentation/kernel-parameters.txt
+++ b/Documentation/kernel-parameters.txt
@@ -1454,6 +1454,41 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
 			In such case C2/C3 won't be used again.
 			idle=nomwait: Disable mwait for CPU C-states
 
+	ieee754=	[MIPS] Select IEEE Std 754 conformance mode
+			Format: { strict | legacy | 2008 | relaxed }
+			Default: strict
+
+			Choose which programs will be accepted for execution
+			based on the IEEE 754 NaN encoding(s) supported by
+			the FPU and the NaN encoding requested with the value
+			of an ELF file header flag individually set by each
+			binary.  Hardware implementations are permitted to
+			support either or both of the legacy and the 2008 NaN
+			encoding mode.
+
+			Available settings are as follows:
+			strict	accept binaries that request a NaN encoding
+				supported by the FPU
+			legacy	only accept legacy-NaN binaries, if supported
+				by the FPU
+			2008	only accept 2008-NaN binaries, if supported
+				by the FPU
+			relaxed	accept any binaries regardless of whether
+				supported by the FPU
+
+			The FPU emulator is always able to support both NaN
+			encodings, so if no FPU hardware is present or it has
+			been disabled with 'nofpu', then the settings of
+			'legacy' and '2008' strap the emulator accordingly,
+			'relaxed' straps the emulator for both legacy-NaN and
+			2008-NaN, whereas 'strict' enables legacy-NaN only on
+			legacy processors and both NaN encodings on MIPS32 or
+			MIPS64 CPUs.
+
+			The setting for ABS.fmt/NEG.fmt instruction execution
+			mode generally follows that for the NaN encoding,
+			except where unsupported by hardware.
+
 	ignore_loglevel	[KNL]
 			Ignore loglevel setting - this will print /all/
 			kernel messages to the console. Useful for debugging.

MAINTAINERS

View file

diff --git a/MAINTAINERS b/MAINTAINERS
index 78f71f4..30aca4a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2420,6 +2420,8 @@ F:	arch/mips/kernel/*bmips*
 F:	arch/mips/boot/dts/brcm/bcm*.dts*
 F:	drivers/irqchip/irq-bcm7*
 F:	drivers/irqchip/irq-brcmstb*
+F:	include/linux/bcm963xx_nvram.h
+F:	include/linux/bcm963xx_tag.h
 
 BROADCOM TG3 GIGABIT ETHERNET DRIVER
 M:	Prashant Sreedharan <[email protected]>
@@ -6216,6 +6218,14 @@ F:	arch/arm64/include/uapi/asm/kvm*
 F:	arch/arm64/include/asm/kvm*
 F:	arch/arm64/kvm/
 
+KERNEL VIRTUAL MACHINE FOR MIPS (KVM/mips)
+M:	James Hogan <[email protected]>
+L:	[email protected]
+S:	Supported
+F:	arch/mips/include/uapi/asm/kvm*
+F:	arch/mips/include/asm/kvm*
+F:	arch/mips/kvm/
+
 KEXEC
 M:	Eric Biederman <[email protected]>
 W:	http://kernel.org/pub/linux/utils/kernel/kexec/
@@ -6313,6 +6323,12 @@ S:	Maintained
 F:	net/l3mdev
 F:	include/net/l3mdev.h
 
+LANTIQ MIPS ARCHITECTURE
+M:	John Crispin <[email protected]>
+L:	[email protected]
+S:	Maintained
+F:	arch/mips/lantiq
+
 LAPB module
 L:	[email protected]
 S:	Orphan
@@ -8997,6 +9013,12 @@ L:	[email protected]
 S:	Maintained
 F:	drivers/video/fbdev/aty/aty128fb.c
 
+RALINK MIPS ARCHITECTURE
+M:	John Crispin <[email protected]>
+L:	[email protected]
+S:	Maintained
+F:	arch/mips/ralink
+
 RALINK RT2X00 WIRELESS LAN DRIVER
 P:	rt2x00 project
 M:	Stanislaw Gruszka <[email protected]>

arch/mips/Kbuild.platforms

View file

diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms
index a96c81d..c5cd63a 100644
--- a/arch/mips/Kbuild.platforms
+++ b/arch/mips/Kbuild.platforms
@@ -21,6 +21,7 @@ platforms += mti-malta
 platforms += mti-sead3
 platforms += netlogic
 platforms += paravirt
+platforms += pic32
 platforms += pistachio
 platforms += pmcs-msp71xx
 platforms += pnx833x

arch/mips/Kconfig

View file

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index fbf3f66..57a945e 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -169,6 +169,7 @@ config BMIPS_GENERIC
 	select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
 	select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
 	select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
+	select ARCH_WANT_OPTIONAL_GPIOLIB
 	help
 	  Build a generic DT-based kernel image that boots on select
 	  BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
@@ -480,6 +481,14 @@ config MIPS_MALTA
 	  This enables support for the MIPS Technologies Malta evaluation
 	  board.
 
+config MACH_PIC32
+	bool "Microchip PIC32 Family"
+	help
+	  This enables support for the Microchip PIC32 family of platforms.
+
+	  Microchip PIC32 is a family of general-purpose 32 bit MIPS core
+	  microcontrollers.
+
 config MIPS_SEAD3
 	bool "MIPS SEAD3 board"
 	select BOOT_ELF32
@@ -979,6 +988,7 @@ source "arch/mips/jazz/Kconfig"
 source "arch/mips/jz4740/Kconfig"
 source "arch/mips/lantiq/Kconfig"
 source "arch/mips/lasat/Kconfig"
+source "arch/mips/pic32/Kconfig"
 source "arch/mips/pistachio/Kconfig"
 source "arch/mips/pmcs-msp71xx/Kconfig"
 source "arch/mips/ralink/Kconfig"
@@ -1755,6 +1765,10 @@ config SYS_SUPPORTS_ZBOOT_UART16550
 	bool
 	select SYS_SUPPORTS_ZBOOT
 
+config SYS_SUPPORTS_ZBOOT_UART_PROM
+	bool
+	select SYS_SUPPORTS_ZBOOT
+
 config CPU_LOONGSON2
 	bool
 	select CPU_SUPPORTS_32BIT_KERNEL
@@ -2017,7 +2031,8 @@ config KVM_GUEST
 	bool "KVM Guest Kernel"
 	depends on BROKEN_ON_SMP
 	help
-	  Select this option if building a guest kernel for KVM (Trap & Emulate) mode
+	  Select this option if building a guest kernel for KVM (Trap & Emulate)
+	  mode.
 
 config KVM_GUEST_TIMER_FREQ
 	int "Count/Compare Timer Frequency (MHz)"

arch/mips/Makefile

View file

diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 3f70ba5..e78d60d 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -166,16 +166,6 @@ cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += -Wa,-march=octeon
 endif
 cflags-$(CONFIG_CAVIUM_CN63XXP1) += -Wa,-mfix-cn63xxp1
 cflags-$(CONFIG_CPU_BMIPS)	+= -march=mips32 -Wa,-mips32 -Wa,--trap
-#
-# binutils from v2.25 on and gcc starting from v4.9.0 treat -march=loongson3a
-# as MIPS64 R1; older versions as just R1.  This leaves the possibility open
-# that GCC might generate R2 code for -march=loongson3a which then is rejected
-# by GAS.  The cc-option can't probe for this behaviour so -march=loongson3a
-# can't easily be used safely within the kbuild framework.
-#
-cflags-$(CONFIG_CPU_LOONGSON3)  +=					\
-	$(call cc-option,-march=mips64r2,-mips64r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS64) \
-	-Wa,-mips64r2 -Wa,--trap
 
 cflags-$(CONFIG_CPU_R4000_WORKAROUNDS)	+= $(call cc-option,-mfix-r4000,)
 cflags-$(CONFIG_CPU_R4400_WORKAROUNDS)	+= $(call cc-option,-mfix-r4400,)

arch/mips/alchemy/common/gpiolib.c

View file

diff --git a/arch/mips/alchemy/common/gpiolib.c b/arch/mips/alchemy/common/gpiolib.c
index f9bc4f5..84548f7 100644
--- a/arch/mips/alchemy/common/gpiolib.c
+++ b/arch/mips/alchemy/common/gpiolib.c
@@ -40,7 +40,7 @@
 
 static int gpio2_get(struct gpio_chip *chip, unsigned offset)
 {
-	return alchemy_gpio2_get_value(offset + ALCHEMY_GPIO2_BASE);
+	return !!alchemy_gpio2_get_value(offset + ALCHEMY_GPIO2_BASE);
 }
 
 static void gpio2_set(struct gpio_chip *chip, unsigned offset, int value)
@@ -68,7 +68,7 @@ static int gpio2_to_irq(struct gpio_chip *chip, unsigned offset)
 
 static int gpio1_get(struct gpio_chip *chip, unsigned offset)
 {
-	return alchemy_gpio1_get_value(offset + ALCHEMY_GPIO1_BASE);
+	return !!alchemy_gpio1_get_value(offset + ALCHEMY_GPIO1_BASE);
 }
 
 static void gpio1_set(struct gpio_chip *chip,
@@ -119,7 +119,7 @@ struct gpio_chip alchemy_gpio_chip[] = {
 
 static int alchemy_gpic_get(struct gpio_chip *chip, unsigned int off)
 {
-	return au1300_gpio_get_value(off + AU1300_GPIO_BASE);
+	return !!au1300_gpio_get_value(off + AU1300_GPIO_BASE);
 }
 
 static void alchemy_gpic_set(struct gpio_chip *chip, unsigned int off, int v)

arch/mips/ar7/gpio.c

View file

diff --git a/arch/mips/ar7/gpio.c b/arch/mips/ar7/gpio.c
index f493045..f969f58 100644
--- a/arch/mips/ar7/gpio.c
+++ b/arch/mips/ar7/gpio.c
@@ -37,7 +37,7 @@ static int ar7_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
 				container_of(chip, struct ar7_gpio_chip, chip);
 	void __iomem *gpio_in = gpch->regs + AR7_GPIO_INPUT;
 
-	return readl(gpio_in) & (1 << gpio);
+	return !!(readl(gpio_in) & (1 << gpio));
 }
 
 static int titan_gpio_get_value(struct gpio_chip *chip, unsigned gpio)

arch/mips/ath79/common.h

View file

diff --git a/arch/mips/ath79/common.h b/arch/mips/ath79/common.h
index ca7cc19..870c6b2 100644
--- a/arch/mips/ath79/common.h
+++ b/arch/mips/ath79/common.h
@@ -23,7 +23,6 @@ void ath79_clocks_init(void);
 unsigned long ath79_get_sys_clk_rate(const char *id);
 
 void ath79_ddr_ctrl_init(void);
-void ath79_ddr_wb_flush(unsigned int reg);
 
 void ath79_gpio_init(void);
 

arch/mips/ath79/irq.c

View file

diff --git a/arch/mips/ath79/irq.c b/arch/mips/ath79/irq.c
index eeb3953..511c065 100644
--- a/arch/mips/ath79/irq.c
+++ b/arch/mips/ath79/irq.c
@@ -26,9 +26,13 @@
 #include "common.h"
 #include "machtypes.h"
 
+static void __init ath79_misc_intc_domain_init(
+	struct device_node *node, int irq);
+
 static void ath79_misc_irq_handler(struct irq_desc *desc)
 {
-	void __iomem *base = ath79_reset_base;
+	struct irq_domain *domain = irq_desc_get_handler_data(desc);
+	void __iomem *base = domain->host_data;
 	u32 pending;
 
 	pending = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS) &
@@ -42,15 +46,15 @@ static void ath79_misc_irq_handler(struct irq_desc *desc)
 	while (pending) {
 		int bit = __ffs(pending);
 
-		generic_handle_irq(ATH79_MISC_IRQ(bit));
+		generic_handle_irq(irq_linear_revmap(domain, bit));
 		pending &= ~BIT(bit);
 	}
 }
 
 static void ar71xx_misc_irq_unmask(struct irq_data *d)
 {
-	unsigned int irq = d->irq - ATH79_MISC_IRQ_BASE;
-	void __iomem *base = ath79_reset_base;
+	void __iomem *base = irq_data_get_irq_chip_data(d);
+	unsigned int irq = d->hwirq;
 	u32 t;
 
 	t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
@@ -62,8 +66,8 @@ static void ar71xx_misc_irq_unmask(struct irq_data *d)
 
 static void ar71xx_misc_irq_mask(struct irq_data *d)
 {
-	unsigned int irq = d->irq - ATH79_MISC_IRQ_BASE;
-	void __iomem *base = ath79_reset_base;
+	void __iomem *base = irq_data_get_irq_chip_data(d);
+	unsigned int irq = d->hwirq;
 	u32 t;
 
 	t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
@@ -75,8 +79,8 @@ static void ar71xx_misc_irq_mask(struct irq_data *d)
 
 static void ar724x_misc_irq_ack(struct irq_data *d)
 {
-	unsigned int irq = d->irq - ATH79_MISC_IRQ_BASE;
-	void __iomem *base = ath79_reset_base;
+	void __iomem *base = irq_data_get_irq_chip_data(d);
+	unsigned int irq = d->hwirq;
 	u32 t;
 
 	t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS);
@@ -94,12 +98,6 @@ static struct irq_chip ath79_misc_irq_chip = {
 
 static void __init ath79_misc_irq_init(void)
 {
-	void __iomem *base = ath79_reset_base;
-	int i;
-
-	__raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_ENABLE);
-	__raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_STATUS);
-
 	if (soc_is_ar71xx() || soc_is_ar913x())
 		ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask;
 	else if (soc_is_ar724x() ||
@@ -110,13 +108,7 @@ static void __init ath79_misc_irq_init(void)
 	else
 		BUG();
 
-	for (i = ATH79_MISC_IRQ_BASE;
-	     i < ATH79_MISC_IRQ_BASE + ATH79_MISC_IRQ_COUNT; i++) {
-		irq_set_chip_and_handler(i, &ath79_misc_irq_chip,
-					 handle_level_irq);
-	}
-
-	irq_set_chained_handler(ATH79_CPU_IRQ(6), ath79_misc_irq_handler);