projects/linux·commit e5e0e6be

Merge tag 'v6.15-p1' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6

e5e0e6be · Linus Torvalds <[email protected]> · 2025-03-29 10:01:55 -07:00

Pull crypto updates from Herbert Xu:
 "API:
   - Remove legacy compression interface
   - Improve scatterwalk API
   - Add request chaining to ahash and acomp
   - Add virtual address support to ahash and acomp
   - Add folio support to acomp
   - Remove NULL dst support from acomp

  Algorithms:
   - Library options are fuly hidden (selected by kernel users only)
   - Add Kerberos5 algorithms
   - Add VAES-based ctr(aes) on x86
   - Ensure LZO respects output buffer length on compression
   - Remove obsolete SIMD fallback code path from arm/ghash-ce

  Drivers:
   - Add support for PCI device 0x1134 in ccp
   - Add support for rk3588's standalone TRNG in rockchip
   - Add Inside Secure SafeXcel EIP-93 crypto engine support in eip93
   - Fix bugs in tegra uncovered by multi-threaded self-test
   - Fix corner cases in hisilicon/sec2

  Others:
   - Add SG_MITER_LOCAL to sg miter
   - Convert ubifs, hibernate and xfrm_ipcomp from legacy API to acomp"

* tag 'v6.15-p1' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: (187 commits)
  crypto: testmgr - Add multibuffer acomp testing
  crypto: acomp - Fix synchronous acomp chaining fallback
  crypto: testmgr - Add multibuffer hash testing
  crypto: hash - Fix synchronous ahash chaining fallback
  crypto: arm/ghash-ce - Remove SIMD fallback code path
  crypto: essiv - Replace memcpy() + NUL-termination with strscpy()
  crypto: api - Call crypto_alg_put in crypto_unregister_alg
  crypto: scompress - Fix incorrect stream freeing
  crypto: lib/chacha - remove unused arch-specific init support
  crypto: remove obsolete 'comp' compression API
  crypto: compress_null - drop obsolete 'comp' implementation
  crypto: cavium/zip - drop obsolete 'comp' implementation
  crypto: zstd - drop obsolete 'comp' implementation
  crypto: lzo - drop obsolete 'comp' implementation
  crypto: lzo-rle - drop obsolete 'comp' implementation
  crypto: lz4hc - drop obsolete 'comp' implementation
  crypto: lz4 - drop obsolete 'comp' implementation
  crypto: deflate - drop obsolete 'comp' implementation
  crypto: 842 - drop obsolete 'comp' implementation
  crypto: nx - Migrate to scomp API
  ...
Commit
e5e0e6bebef3a21081fd1057c40468d4cff1a60d
Parents
7d06015d · 99585c21

Merge commit. Changes below are compared with the first parent: 7d06015d.

Changes

233 files changed · +14474 −4689

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Documentation/crypto/architecture.rstmodified+0−2View file
Documentation/crypto/index.rstmodified+1−0View file
Documentation/crypto/krb5.rstadded+262−0View file
Documentation/devicetree/bindings/crypto/fsl,sec2.0.yamladded+144−0View file
Documentation/devicetree/bindings/crypto/fsl-sec2.txtdeleted+0−65View before deletion
Documentation/devicetree/bindings/crypto/inside-secure,safexcel-eip93.yamladded+67−0View file
Documentation/devicetree/bindings/crypto/inside-secure,safexcel.yamlmodified+2−0View file
Documentation/devicetree/bindings/crypto/qcom,prng.yamlmodified+1−0View file
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Documentation/devicetree/bindings/rng/rockchip,rk3588-rng.yamladded+59−0View file
MAINTAINERSmodified+39−0View file
arch/arm/crypto/Kconfigmodified+7−3View file
arch/arm/crypto/aes-ce-glue.cmodified+1−1View file
arch/arm/crypto/chacha-glue.cmodified+2−8View file
arch/arm/crypto/ghash-ce-glue.cmodified+12−201View file
arch/arm64/crypto/Kconfigmodified+4−2View file
arch/arm64/crypto/aes-ce-ccm-glue.cmodified+5−15View file
arch/arm64/crypto/aes-neonbs-glue.cmodified+2−1View file
arch/arm64/crypto/chacha-neon-glue.cmodified+2−8View file
arch/arm64/crypto/ghash-ce-glue.cmodified+4−13View file
arch/arm64/crypto/sm4-ce-ccm-glue.cmodified+11−16View file
arch/arm64/crypto/sm4-ce-gcm-glue.cmodified+13−18View file
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arch/powerpc/crypto/aes-gcm-p10-glue.cmodified+3−3View file
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arch/powerpc/crypto/chacha-p10-glue.cmodified+2−8View file
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arch/sparc/crypto/aes_glue.cmodified+1−1View file
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drivers/char/hw_random/rockchip-rng.cmodified+222−28View file
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drivers/crypto/caam/caamalg_qi2.cmodified+2−1View file
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drivers/crypto/inside-secure/eip93/eip93-cipher.hadded+60−0View file
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drivers/crypto/inside-secure/eip93/eip93-des.hadded+16−0View file
drivers/crypto/inside-secure/eip93/eip93-hash.cadded+866−0View file
drivers/crypto/inside-secure/eip93/eip93-hash.hadded+82−0View file
drivers/crypto/inside-secure/eip93/eip93-main.cadded+501−0View file
drivers/crypto/inside-secure/eip93/eip93-main.hadded+151−0View file
drivers/crypto/inside-secure/eip93/eip93-regs.hadded+335−0View file
drivers/crypto/intel/iaa/iaa_crypto_main.cmodified+12−152View file
drivers/crypto/intel/qat/qat_420xx/Makefilemodified+1−1View file
drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.cmodified+6−13View file
drivers/crypto/intel/qat/qat_420xx/adf_drv.cmodified+1−1View file
drivers/crypto/intel/qat/qat_4xxx/Makefilemodified+1−1View file
drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.cmodified+4−9View file
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drivers/crypto/intel/qat/qat_c3xxx/Makefilemodified+1−1View file
drivers/crypto/intel/qat/qat_c3xxx/adf_c3xxx_hw_data.cmodified+2−2View file
drivers/crypto/intel/qat/qat_c3xxx/adf_drv.cmodified+1−1View file
drivers/crypto/intel/qat/qat_c3xxxvf/Makefilemodified+1−1View file
drivers/crypto/intel/qat/qat_c62x/Makefilemodified+1−1View file
drivers/crypto/intel/qat/qat_c62x/adf_c62x_hw_data.cmodified+2−2View file
drivers/crypto/intel/qat/qat_c62x/adf_drv.cmodified+2−2View file
drivers/crypto/intel/qat/qat_c62xvf/Makefilemodified+1−1View file
drivers/crypto/intel/qat/qat_common/Makefilemodified+33−33View file
drivers/crypto/intel/qat/qat_common/adf_accel_devices.hmodified+22−1View file
drivers/crypto/intel/qat/qat_common/adf_cfg_services.cmodified+147−20View file
drivers/crypto/intel/qat/qat_common/adf_cfg_services.hmodified+17−9View file
drivers/crypto/intel/qat/qat_common/adf_cfg_strings.hmodified+1−5View file
drivers/crypto/intel/qat/qat_common/adf_gen2_hw_data.cmodified+1−1View file
drivers/crypto/intel/qat/qat_common/adf_gen4_config.cmodified+2−13View file
drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.cmodified+25−31View file
drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.hmodified+1−0View file
drivers/crypto/intel/qat/qat_common/adf_gen4_ras.cmodified+6−53View file
drivers/crypto/intel/qat/qat_common/adf_sysfs.cmodified+10−12View file
drivers/crypto/intel/qat/qat_common/icp_qat_fw_comp.hmodified+2−2View file
drivers/crypto/intel/qat/qat_common/icp_qat_uclo.hmodified+0−10View file
drivers/crypto/intel/qat/qat_common/qat_bl.cmodified+0−159View file
drivers/crypto/intel/qat/qat_common/qat_bl.hmodified+0−6View file
drivers/crypto/intel/qat/qat_common/qat_comp_algs.cmodified+1−84View file
drivers/crypto/intel/qat/qat_common/qat_comp_req.hmodified+0−10View file
drivers/crypto/intel/qat/qat_common/qat_uclo.cmodified+21−17View file
drivers/crypto/intel/qat/qat_dh895xcc/Makefilemodified+1−1View file
drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.cmodified+3−3View file
drivers/crypto/intel/qat/qat_dh895xcc/adf_drv.cmodified+1−1View file
drivers/crypto/intel/qat/qat_dh895xccvf/Makefilemodified+1−1View file
drivers/crypto/marvell/Kconfigmodified+2−2View file
drivers/crypto/marvell/octeontx/otx_cptpf_ucode.cmodified+3−13View file
drivers/crypto/marvell/octeontx/otx_cptpf_ucode.hmodified+0−2View file
drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.cmodified+1−99View file
drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.hmodified+0−1View file
drivers/crypto/marvell/octeontx2/otx2_cptvf_reqmgr.cmodified+4−3View file
drivers/crypto/mxs-dcp.cmodified+4−4View file
drivers/crypto/nx/nx-842.cmodified+19−14View file
drivers/crypto/nx/nx-842.hmodified+8−7View file
drivers/crypto/nx/nx-aes-ccm.cmodified+6−10View file
drivers/crypto/nx/nx-aes-gcm.cmodified+6−11View file
drivers/crypto/nx/nx-common-powernv.cmodified+15−16View file
drivers/crypto/nx/nx-common-pseries.cmodified+33−37View file
drivers/crypto/nx/nx.cmodified+6−28View file
drivers/crypto/nx/nx.hmodified+0−3View file
drivers/crypto/padlock-sha.cmodified+2−2View file
drivers/crypto/s5p-sss.cmodified+11−27View file
drivers/crypto/stm32/stm32-cryp.cmodified+17−17View file
drivers/crypto/tegra/tegra-se-aes.cmodified+266−135View file
drivers/crypto/tegra/tegra-se-hash.cmodified+186−101View file
drivers/crypto/tegra/tegra-se-key.cmodified+26−3View file
drivers/crypto/tegra/tegra-se-main.cmodified+12−4View file
drivers/crypto/tegra/tegra-se.hmodified+34−5View file
drivers/crypto/virtio/virtio_crypto_akcipher_algs.cmodified+16−25View file
drivers/crypto/virtio/virtio_crypto_core.cmodified+2−4View file
drivers/crypto/virtio/virtio_crypto_mgr.cmodified+1−1View file
drivers/crypto/virtio/virtio_crypto_skcipher_algs.cmodified+4−13View file
fs/ubifs/compress.cmodified+166−42View file
fs/ubifs/file.cmodified+25−49View file
fs/ubifs/journal.cmodified+7−4View file
fs/ubifs/ubifs.hmodified+12−14View file
include/crypto/acompress.hmodified+359−23View file
include/crypto/algapi.hmodified+19−14View file
include/crypto/authenc.hmodified+2−0View file
include/crypto/chacha.hmodified+1−10View file
include/crypto/ctr.hmodified+1−1View file
include/crypto/hash.hmodified+57−15View file
include/crypto/internal/acompress.hmodified+67−18View file
include/crypto/internal/hash.hmodified+15−0View file
include/crypto/internal/scompress.hmodified+3−15View file
include/crypto/internal/skcipher.hmodified+29−11View file
include/crypto/krb5.hadded+160−0View file
include/crypto/scatterwalk.hmodified+182−40View file
include/crypto/sig.hmodified+3−2View file
include/crypto/skcipher.hmodified+13−6View file
include/dt-bindings/reset/rockchip,rk3588-cru.hmodified+40−1View file
include/linux/async_tx.hmodified+0−5View file
include/linux/crypto.hmodified+17−66View file
include/linux/lzo.hmodified+8−0View file
include/linux/math.hmodified+12−0View file
include/linux/scatterlist.hmodified+1−0View file
include/linux/spinlock.hmodified+13−0View file
include/net/ipcomp.hmodified+1−12View file
include/uapi/linux/psp-sev.hmodified+14−7View file
kernel/power/hibernate.cmodified+3−2View file
kernel/power/swap.cmodified+39−19View file
lib/842/842_compress.cmodified+2−0View file
lib/crypto/Kconfigmodified+27−18View file
lib/crypto/chacha20poly1305.cmodified+3−4View file
lib/lzo/Makefilemodified+1−1View file
lib/lzo/lzo1x_compress.cmodified+77−25View file
lib/lzo/lzo1x_compress_safe.cadded+18−0View file
lib/scatterlist.cmodified+8−4View file
net/tls/tls_device_fallback.cmodified+6−25View file
net/xfrm/xfrm_algo.cmodified+3−4View file
net/xfrm/xfrm_ipcomp.cmodified+212−221View file
security/keys/Kconfigmodified+1−1View file
tools/testing/crypto/chacha20-s390/test-cipher.cmodified+2−2View file

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Documentation/crypto/architecture.rst

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diff --git a/Documentation/crypto/architecture.rst b/Documentation/crypto/architecture.rst
index 15dcd62..249b54d 100644
--- a/Documentation/crypto/architecture.rst
+++ b/Documentation/crypto/architecture.rst
@@ -196,8 +196,6 @@ the aforementioned cipher types:
- CRYPTO_ALG_TYPE_CIPHER Single block cipher
-- CRYPTO_ALG_TYPE_COMPRESS Compression
-
- CRYPTO_ALG_TYPE_AEAD Authenticated Encryption with Associated Data
(MAC)

Documentation/crypto/index.rst

View file
diff --git a/Documentation/crypto/index.rst b/Documentation/crypto/index.rst
index 92eec78..100b47d 100644
--- a/Documentation/crypto/index.rst
+++ b/Documentation/crypto/index.rst
@@ -26,3 +26,4 @@ for cryptographic use cases, as well as programming examples.
api-samples
descore-readme
device_drivers/index
+ krb5

Documentation/crypto/krb5.rst

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diff --git a/Documentation/crypto/krb5.rst b/Documentation/crypto/krb5.rst
new file mode 100644
index 0000000..beffa01
--- /dev/null
+++ b/Documentation/crypto/krb5.rst
@@ -0,0 +1,262 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+===========================
+Kerberos V Cryptography API
+===========================
+
+.. Contents:
+
+ - Overview.
+ - Small Buffer.
+ - Encoding Type.
+ - Key Derivation.
+ - PRF+ Calculation.
+ - Kc, Ke And Ki Derivation.
+ - Crypto Functions.
+ - Preparation Functions.
+ - Encryption Mode.
+ - Checksum Mode.
+ - The krb5enc AEAD algorithm
+
+Overview
+========
+
+This API provides Kerberos 5-style cryptography for key derivation, encryption
+and checksumming for use in network filesystems and can be used to implement
+the low-level crypto that's needed for GSSAPI.
+
+The following crypto types are supported::
+
+ KRB5_ENCTYPE_AES128_CTS_HMAC_SHA1_96
+ KRB5_ENCTYPE_AES256_CTS_HMAC_SHA1_96
+ KRB5_ENCTYPE_AES128_CTS_HMAC_SHA256_128
+ KRB5_ENCTYPE_AES256_CTS_HMAC_SHA384_192
+ KRB5_ENCTYPE_CAMELLIA128_CTS_CMAC
+ KRB5_ENCTYPE_CAMELLIA256_CTS_CMAC
+
+ KRB5_CKSUMTYPE_HMAC_SHA1_96_AES128
+ KRB5_CKSUMTYPE_HMAC_SHA1_96_AES256
+ KRB5_CKSUMTYPE_CMAC_CAMELLIA128
+ KRB5_CKSUMTYPE_CMAC_CAMELLIA256
+ KRB5_CKSUMTYPE_HMAC_SHA256_128_AES128
+ KRB5_CKSUMTYPE_HMAC_SHA384_192_AES256
+
+The API can be included by::
+
+ #include <crypto/krb5.h>
+
+Small Buffer
+------------
+
+To pass small pieces of data about, such as keys, a buffer structure is
+defined, giving a pointer to the data and the size of that data::
+
+ struct krb5_buffer {
+ unsigned int len;
+ void *data;
+ };
+
+Encoding Type
+=============
+
+The encoding type is defined by the following structure::
+
+ struct krb5_enctype {
+ int etype;
+ int ctype;
+ const char *name;
+ u16 key_bytes;
+ u16 key_len;
+ u16 Kc_len;
+ u16 Ke_len;
+ u16 Ki_len;
+ u16 prf_len;
+ u16 block_len;
+ u16 conf_len;
+ u16 cksum_len;
+ ...
+ };
+
+The fields of interest to the user of the API are as follows:
+
+ * ``etype`` and ``ctype`` indicate the protocol number for this encoding
+ type for encryption and checksumming respectively. They hold
+ ``KRB5_ENCTYPE_*`` and ``KRB5_CKSUMTYPE_*`` constants.
+
+ * ``name`` is the formal name of the encoding.
+
+ * ``key_len`` and ``key_bytes`` are the input key length and the derived key
+ length. (I think they only differ for DES, which isn't supported here).
+
+ * ``Kc_len``, ``Ke_len`` and ``Ki_len`` are the sizes of the derived Kc, Ke
+ and Ki keys. Kc is used for in checksum mode; Ke and Ki are used in
+ encryption mode.
+
+ * ``prf_len`` is the size of the result from the PRF+ function calculation.
+
+ * ``block_len``, ``conf_len`` and ``cksum_len`` are the encryption block
+ length, confounder length and checksum length respectively. All three are
+ used in encryption mode, but only the checksum length is used in checksum
+ mode.
+
+The encoding type is looked up by number using the following function::
+
+ const struct krb5_enctype *crypto_krb5_find_enctype(u32 enctype);
+
+Key Derivation
+==============
+
+Once the application has selected an encryption type, the keys that will be
+used to do the actual crypto can be derived from the transport key.
+
+PRF+ Calculation
+----------------
+
+To aid in key derivation, a function to calculate the Kerberos GSSAPI
+mechanism's PRF+ is provided::
+
+ int crypto_krb5_calc_PRFplus(const struct krb5_enctype *krb5,
+ const struct krb5_buffer *K,
+ unsigned int L,
+ const struct krb5_buffer *S,
+ struct krb5_buffer *result,
+ gfp_t gfp);
+
+This can be used to derive the transport key from a source key plus additional
+data to limit its use.
+
+Crypto Functions
+================
+
+Once the keys have been derived, crypto can be performed on the data. The
+caller must leave gaps in the buffer for the storage of the confounder (if
+needed) and the checksum when preparing a message for transmission. An enum
+and a pair of functions are provided to aid in this::
+
+ enum krb5_crypto_mode {
+ KRB5_CHECKSUM_MODE,
+ KRB5_ENCRYPT_MODE,
+ };
+
+ size_t crypto_krb5_how_much_buffer(const struct krb5_enctype *krb5,
+ enum krb5_crypto_mode mode,
+ size_t data_size, size_t *_offset);
+
+ size_t crypto_krb5_how_much_data(const struct krb5_enctype *krb5,
+ enum krb5_crypto_mode mode,
+ size_t *_buffer_size, size_t *_offset);
+
+All these functions take the encoding type and an indication the mode of crypto
+(checksum-only or full encryption).
+
+The first function returns how big the buffer will need to be to house a given
+amount of data; the second function returns how much data will fit in a buffer
+of a particular size, and adjusts down the size of the required buffer
+accordingly. In both cases, the offset of the data within the buffer is also
+returned.
+
+When a message has been received, the location and size of the data with the
+message can be determined by calling::
+
+ void crypto_krb5_where_is_the_data(const struct krb5_enctype *krb5,
+ enum krb5_crypto_mode mode,
+ size_t *_offset, size_t *_len);
+
+The caller provides the offset and length of the message to the function, which
+then alters those values to indicate the region containing the data (plus any
+padding). It is up to the caller to determine how much padding there is.
+
+Preparation Functions
+---------------------
+
+Two functions are provided to allocated and prepare a crypto object for use by
+the action functions::
+
+ struct crypto_aead *
+ crypto_krb5_prepare_encryption(const struct krb5_enctype *krb5,
+ const struct krb5_buffer *TK,
+ u32 usage, gfp_t gfp);
+ struct crypto_shash *
+ crypto_krb5_prepare_checksum(const struct krb5_enctype *krb5,
+ const struct krb5_buffer *TK,
+ u32 usage, gfp_t gfp);
+
+Both of these functions take the encoding type, the transport key and the usage
+value used to derive the appropriate subkey(s). They create an appropriate
+crypto object, an AEAD template for encryption and a synchronous hash for
+checksumming, set the key(s) on it and configure it. The caller is expected to
+pass these handles to the action functions below.
+
+Encryption Mode
+---------------
+
+A pair of functions are provided to encrypt and decrypt a message::
+
+ ssize_t crypto_krb5_encrypt(const struct krb5_enctype *krb5,
+ struct crypto_aead *aead,
+ struct scatterlist *sg, unsigned int nr_sg,
+ size_t sg_len,
+ size_t data_offset, size_t data_len,
+ bool preconfounded);
+ int crypto_krb5_decrypt(const struct krb5_enctype *krb5,
+ struct crypto_aead *aead,
+ struct scatterlist *sg, unsigned int nr_sg,
+ size_t *_offset, size_t *_len);
+
+In both cases, the input and output buffers are indicated by the same
+scatterlist.
+
+For the encryption function, the output buffer may be larger than is needed
+(the amount of output generated is returned) and the location and size of the
+data are indicated (which must match the encoding). If no confounder is set,
+the function will insert one.
+
+For the decryption function, the offset and length of the message in buffer are
+supplied and these are shrunk to fit the data. The decryption function will
+verify any checksums within the message and give an error if they don't match.
+
+Checksum Mode
+-------------
+
+A pair of function are provided to generate the checksum on a message and to
+verify that checksum::
+
+ ssize_t crypto_krb5_get_mic(const struct krb5_enctype *krb5,
+ struct crypto_shash *shash,
+ const struct krb5_buffer *metadata,
+ struct scatterlist *sg, unsigned int nr_sg,
+ size_t sg_len,
+ size_t data_offset, size_t data_len);
+ int crypto_krb5_verify_mic(const struct krb5_enctype *krb5,
+ struct crypto_shash *shash,
+ const struct krb5_buffer *metadata,
+ struct scatterlist *sg, unsigned int nr_sg,
+ size_t *_offset, size_t *_len);
+
+In both cases, the input and output buffers are indicated by the same
+scatterlist. Additional metadata can be passed in which will get added to the
+hash before the data.
+
+For the get_mic function, the output buffer may be larger than is needed (the
+amount of output generated is returned) and the location and size of the data
+are indicated (which must match the encoding).
+
+For the verification function, the offset and length of the message in buffer
+are supplied and these are shrunk to fit the data. An error will be returned
+if the checksums don't match.
+
+The krb5enc AEAD algorithm
+==========================
+
+A template AEAD crypto algorithm, called "krb5enc", is provided that hashes the
+plaintext before encrypting it (the reverse of authenc). The handle returned
+by ``crypto_krb5_prepare_encryption()`` may be one of these, but there's no
+requirement for the user of this API to interact with it directly.
+
+For reference, its key format begins with a BE32 of the format number. Only
+format 1 is provided and that continues with a BE32 of the Ke key length
+followed by a BE32 of the Ki key length, followed by the bytes from the Ke key
+and then the Ki key.
+
+Using specifically ordered words means that the static test data doesn't
+require byteswapping.

Documentation/devicetree/bindings/crypto/fsl,sec2.0.yaml

View file
diff --git a/Documentation/devicetree/bindings/crypto/fsl,sec2.0.yaml b/Documentation/devicetree/bindings/crypto/fsl,sec2.0.yaml
new file mode 100644
index 0000000..2091b89
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/fsl,sec2.0.yaml
@@ -0,0 +1,144 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/crypto/fsl,sec2.0.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale SoC SEC Security Engines versions 1.x-2.x-3.x
+
+maintainers:
+ - J. Neuschäfer <[email protected]>
+
+properties:
+ compatible:
+ description:
+ Should contain entries for this and backward compatible SEC versions,
+ high to low. Warning - SEC1 and SEC2 are mutually exclusive.
+ oneOf:
+ - items:
+ - const: fsl,sec3.3
+ - const: fsl,sec3.1
+ - const: fsl,sec3.0
+ - const: fsl,sec2.4
+ - const: fsl,sec2.2
+ - const: fsl,sec2.1
+ - const: fsl,sec2.0
+ - items:
+ - const: fsl,sec3.1
+ - const: fsl,sec3.0
+ - const: fsl,sec2.4
+ - const: fsl,sec2.2
+ - const: fsl,sec2.1
+ - const: fsl,sec2.0
+ - items:
+ - const: fsl,sec3.0
+ - const: fsl,sec2.4
+ - const: fsl,sec2.2
+ - const: fsl,sec2.1
+ - const: fsl,sec2.0
+ - items:
+ - const: fsl,sec2.4
+ - const: fsl,sec2.2
+ - const: fsl,sec2.1
+ - const: fsl,sec2.0
+ - items:
+ - const: fsl,sec2.2
+ - const: fsl,sec2.1
+ - const: fsl,sec2.0
+ - items:
+ - const: fsl,sec2.1
+ - const: fsl,sec2.0
+ - items:
+ - const: fsl,sec2.0
+ - items:
+ - const: fsl,sec1.2
+ - const: fsl,sec1.0
+ - items:
+ - const: fsl,sec1.0
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ fsl,num-channels:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [ 1, 4 ]
+ description: An integer representing the number of channels available.
+
+ fsl,channel-fifo-len:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maximum: 100
+ description:
+ An integer representing the number of descriptor pointers each channel
+ fetch fifo can hold.
+
+ fsl,exec-units-mask:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maximum: 0xfff
+ description: |
+ The bitmask representing what execution units (EUs) are available.
+ EU information should be encoded following the SEC's Descriptor Header
+ Dword EU_SEL0 field documentation, i.e. as follows:
+
+ bit 0 = reserved - should be 0
+ bit 1 = set if SEC has the ARC4 EU (AFEU)
+ bit 2 = set if SEC has the DES/3DES EU (DEU)
+ bit 3 = set if SEC has the message digest EU (MDEU/MDEU-A)
+ bit 4 = set if SEC has the random number generator EU (RNG)
+ bit 5 = set if SEC has the public key EU (PKEU)
+ bit 6 = set if SEC has the AES EU (AESU)
+ bit 7 = set if SEC has the Kasumi EU (KEU)
+ bit 8 = set if SEC has the CRC EU (CRCU)
+ bit 11 = set if SEC has the message digest EU extended alg set (MDEU-B)
+
+ remaining bits are reserved for future SEC EUs.
+
+ fsl,descriptor-types-mask:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ The bitmask representing what descriptors are available. Descriptor type
+ information should be encoded following the SEC's Descriptor Header Dword
+ DESC_TYPE field documentation, i.e. as follows:
+
+ bit 0 = SEC supports descriptor type aesu_ctr_nonsnoop
+ bit 1 = SEC supports descriptor type ipsec_esp
+ bit 2 = SEC supports descriptor type common_nonsnoop
+ bit 3 = SEC supports descriptor type 802.11i AES ccmp
+ bit 4 = SEC supports descriptor type hmac_snoop_no_afeu
+ bit 5 = SEC supports descriptor type srtp
+ bit 6 = SEC supports descriptor type non_hmac_snoop_no_afeu
+ bit 7 = SEC supports descriptor type pkeu_assemble
+ bit 8 = SEC supports descriptor type aesu_key_expand_output
+ bit 9 = SEC supports descriptor type pkeu_ptmul
+ bit 10 = SEC supports descriptor type common_nonsnoop_afeu
+ bit 11 = SEC supports descriptor type pkeu_ptadd_dbl
+
+ ..and so on and so forth.
+
+required:
+ - compatible
+ - reg
+ - fsl,num-channels
+ - fsl,channel-fifo-len
+ - fsl,exec-units-mask
+ - fsl,descriptor-types-mask
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ /* MPC8548E */
+ crypto@30000 {
+ compatible = "fsl,sec2.1", "fsl,sec2.0";
+ reg = <0x30000 0x10000>;
+ interrupts = <29 2>;
+ interrupt-parent = <&mpic>;
+ fsl,num-channels = <4>;
+ fsl,channel-fifo-len = <24>;
+ fsl,exec-units-mask = <0xfe>;
+ fsl,descriptor-types-mask = <0x12b0ebf>;
+ };
+
+...

Documentation/devicetree/bindings/crypto/fsl-sec2.txt

View before deletion
diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec2.txt b/Documentation/devicetree/bindings/crypto/fsl-sec2.txt
deleted file mode 100644
index 125f155..0000000
--- a/Documentation/devicetree/bindings/crypto/fsl-sec2.txt
+++ /dev/null
@@ -1,65 +0,0 @@
-Freescale SoC SEC Security Engines versions 1.x-2.x-3.x
-
-Required properties:
-
-- compatible : Should contain entries for this and backward compatible
- SEC versions, high to low, e.g., "fsl,sec2.1", "fsl,sec2.0" (SEC2/3)
- e.g., "fsl,sec1.2", "fsl,sec1.0" (SEC1)
- warning: SEC1 and SEC2 are mutually exclusive
-- reg : Offset and length of the register set for the device
-- interrupts : the SEC's interrupt number
-- fsl,num-channels : An integer representing the number of channels
- available.
-- fsl,channel-fifo-len : An integer representing the number of
- descriptor pointers each channel fetch fifo can hold.
-- fsl,exec-units-mask : The bitmask representing what execution units
- (EUs) are available. It's a single 32-bit cell. EU information
- should be encoded following the SEC's Descriptor Header Dword
- EU_SEL0 field documentation, i.e. as follows:
-
- bit 0 = reserved - should be 0
- bit 1 = set if SEC has the ARC4 EU (AFEU)
- bit 2 = set if SEC has the DES/3DES EU (DEU)
- bit 3 = set if SEC has the message digest EU (MDEU/MDEU-A)
- bit 4 = set if SEC has the random number generator EU (RNG)
- bit 5 = set if SEC has the public key EU (PKEU)
- bit 6 = set if SEC has the AES EU (AESU)
- bit 7 = set if SEC has the Kasumi EU (KEU)
- bit 8 = set if SEC has the CRC EU (CRCU)
- bit 11 = set if SEC has the message digest EU extended alg set (MDEU-B)
-
-remaining bits are reserved for future SEC EUs.
-
-- fsl,descriptor-types-mask : The bitmask representing what descriptors
- are available. It's a single 32-bit cell. Descriptor type information
- should be encoded following the SEC's Descriptor Header Dword DESC_TYPE
- field documentation, i.e. as follows:
-
- bit 0 = set if SEC supports the aesu_ctr_nonsnoop desc. type
- bit 1 = set if SEC supports the ipsec_esp descriptor type
- bit 2 = set if SEC supports the common_nonsnoop desc. type
- bit 3 = set if SEC supports the 802.11i AES ccmp desc. type
- bit 4 = set if SEC supports the hmac_snoop_no_afeu desc. type
- bit 5 = set if SEC supports the srtp descriptor type
- bit 6 = set if SEC supports the non_hmac_snoop_no_afeu desc.type
- bit 7 = set if SEC supports the pkeu_assemble descriptor type
- bit 8 = set if SEC supports the aesu_key_expand_output desc.type
- bit 9 = set if SEC supports the pkeu_ptmul descriptor type
- bit 10 = set if SEC supports the common_nonsnoop_afeu desc. type
- bit 11 = set if SEC supports the pkeu_ptadd_dbl descriptor type
-
- ..and so on and so forth.
-
-Example:
-
- /* MPC8548E */
- crypto@30000 {
- compatible = "fsl,sec2.1", "fsl,sec2.0";
- reg = <0x30000 0x10000>;
- interrupts = <29 2>;
- interrupt-parent = <&mpic>;
- fsl,num-channels = <4>;
- fsl,channel-fifo-len = <24>;
- fsl,exec-units-mask = <0xfe>;
- fsl,descriptor-types-mask = <0x12b0ebf>;
- };

Documentation/devicetree/bindings/crypto/inside-secure,safexcel-eip93.yaml

View file
diff --git a/Documentation/devicetree/bindings/crypto/inside-secure,safexcel-eip93.yaml b/Documentation/devicetree/bindings/crypto/inside-secure,safexcel-eip93.yaml
new file mode 100644
index 0000000..997bf97
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/inside-secure,safexcel-eip93.yaml
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/crypto/inside-secure,safexcel-eip93.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Inside Secure SafeXcel EIP-93 cryptographic engine
+
+maintainers:
+ - Christian Marangi <[email protected]>
+
+description: |
+ The Inside Secure SafeXcel EIP-93 is a cryptographic engine IP block
+ integrated in varios devices with very different and generic name from
+ PKTE to simply vendor+EIP93. The real IP under the hood is actually
+ developed by Inside Secure and given to license to vendors.
+
+ The IP block is sold with different model based on what feature are
+ needed and are identified with the final letter. Each letter correspond
+ to a specific set of feature and multiple letter reflect the sum of the
+ feature set.
+
+ EIP-93 models:
+ - EIP-93i: (basic) DES/Triple DES, AES, PRNG, IPsec ESP, SRTP, SHA1
+ - EIP-93ie: i + SHA224/256, AES-192/256
+ - EIP-93is: i + SSL/DTLS/DTLS, MD5, ARC4
+ - EIP-93ies: i + e + s
+ - EIP-93iw: i + AES-XCB-MAC, AES-CCM
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: airoha,en7581-eip93
+ - const: inside-secure,safexcel-eip93ies
+ - items:
+ - not: {}
+ description: Need a SoC specific compatible
+ - enum:
+ - inside-secure,safexcel-eip93i
+ - inside-secure,safexcel-eip93ie
+ - inside-secure,safexcel-eip93is
+ - inside-secure,safexcel-eip93iw
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ crypto@1e004000 {
+ compatible = "airoha,en7581-eip93", "inside-secure,safexcel-eip93ies";
+ reg = <0x1fb70000 0x1000>;
+
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ };

Documentation/devicetree/bindings/crypto/inside-secure,safexcel.yaml

View file
diff --git a/Documentation/devicetree/bindings/crypto/inside-secure,safexcel.yaml b/Documentation/devicetree/bindings/crypto/inside-secure,safexcel.yaml
index ef07258..343e2d0 100644
--- a/Documentation/devicetree/bindings/crypto/inside-secure,safexcel.yaml
+++ b/Documentation/devicetree/bindings/crypto/inside-secure,safexcel.yaml
@@ -47,6 +47,8 @@ properties:
- const: core
- const: reg
+ dma-coherent: true
+
required:
- reg
- interrupts

Documentation/devicetree/bindings/crypto/qcom,prng.yaml

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index 5e6f8b6..ed7e16b 100644
--- a/Documentation/devicetree/bindings/crypto/qcom,prng.yaml

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crypto/testmgr.h

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crypto/xctr.c

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crypto/xts.c

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crypto/zstd.c

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drivers/char/hw_random/Kconfig

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drivers/char/hw_random/imx-rngc.c

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drivers/char/hw_random/rockchip-rng.c

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drivers/crypto/Kconfig

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drivers/crypto/Makefile

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drivers/crypto/axis/artpec6_crypto.c

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drivers/crypto/bcm/cipher.c

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drivers/crypto/bcm/spu2.c

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drivers/crypto/caam/caamalg_qi2.c

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drivers/crypto/cavium/zip/zip_crypto.c

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drivers/crypto/cavium/zip/zip_crypto.h

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drivers/crypto/cavium/zip/zip_main.c

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drivers/crypto/ccp/sp-pci.c

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drivers/crypto/hisilicon/hpre/hpre_crypto.c

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drivers/crypto/hisilicon/sec2/sec.h

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drivers/crypto/hisilicon/sec2/sec_crypto.c

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drivers/crypto/inside-secure/Makefile

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drivers/crypto/inside-secure/eip93/Kconfig

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drivers/crypto/inside-secure/eip93/Makefile

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drivers/crypto/inside-secure/eip93/eip93-aead.c

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drivers/crypto/inside-secure/eip93/eip93-aead.h

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drivers/crypto/inside-secure/eip93/eip93-aes.h

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drivers/crypto/inside-secure/eip93/eip93-cipher.c

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drivers/crypto/inside-secure/eip93/eip93-cipher.h

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drivers/crypto/inside-secure/eip93/eip93-common.c

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drivers/crypto/inside-secure/eip93/eip93-common.h

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drivers/crypto/inside-secure/eip93/eip93-des.h

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drivers/crypto/inside-secure/eip93/eip93-hash.c

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drivers/crypto/inside-secure/eip93/eip93-hash.h

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drivers/crypto/inside-secure/eip93/eip93-main.c

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drivers/crypto/inside-secure/eip93/eip93-main.h

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drivers/crypto/inside-secure/eip93/eip93-regs.h

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drivers/crypto/intel/iaa/iaa_crypto_main.c

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drivers/crypto/intel/qat/qat_420xx/Makefile

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drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

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drivers/crypto/intel/qat/qat_420xx/adf_drv.c

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drivers/crypto/intel/qat/qat_4xxx/Makefile

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drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

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drivers/crypto/intel/qat/qat_4xxx/adf_drv.c

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drivers/crypto/intel/qat/qat_c3xxx/Makefile

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drivers/crypto/intel/qat/qat_c3xxx/adf_c3xxx_hw_data.c

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drivers/crypto/intel/qat/qat_c3xxx/adf_drv.c

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drivers/crypto/intel/qat/qat_c3xxxvf/Makefile

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drivers/crypto/intel/qat/qat_c62x/Makefile

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drivers/crypto/intel/qat/qat_c62x/adf_c62x_hw_data.c

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drivers/crypto/intel/qat/qat_c62x/adf_drv.c

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drivers/crypto/intel/qat/qat_c62xvf/Makefile

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drivers/crypto/intel/qat/qat_common/Makefile

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drivers/crypto/intel/qat/qat_common/adf_accel_devices.h

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drivers/crypto/intel/qat/qat_common/adf_cfg_services.c

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drivers/crypto/intel/qat/qat_common/adf_cfg_services.h

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drivers/crypto/intel/qat/qat_common/adf_cfg_strings.h

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drivers/crypto/intel/qat/qat_common/adf_gen2_hw_data.c

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drivers/crypto/intel/qat/qat_common/adf_gen4_config.c

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drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c

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drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.h

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drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

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drivers/crypto/intel/qat/qat_common/adf_sysfs.c

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drivers/crypto/intel/qat/qat_common/icp_qat_fw_comp.h

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drivers/crypto/intel/qat/qat_common/icp_qat_uclo.h

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drivers/crypto/intel/qat/qat_common/qat_bl.c

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drivers/crypto/intel/qat/qat_common/qat_bl.h

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drivers/crypto/intel/qat/qat_common/qat_comp_algs.c

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drivers/crypto/intel/qat/qat_common/qat_comp_req.h

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drivers/crypto/intel/qat/qat_common/qat_uclo.c

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drivers/crypto/intel/qat/qat_dh895xcc/Makefile

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drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

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drivers/crypto/intel/qat/qat_dh895xcc/adf_drv.c

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drivers/crypto/intel/qat/qat_dh895xccvf/Makefile

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drivers/crypto/marvell/Kconfig

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drivers/crypto/marvell/octeontx/otx_cptpf_ucode.c

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drivers/crypto/marvell/octeontx/otx_cptpf_ucode.h

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drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c

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drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.h

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drivers/crypto/marvell/octeontx2/otx2_cptvf_reqmgr.c

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drivers/crypto/mxs-dcp.c

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drivers/crypto/nx/nx-842.c

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drivers/crypto/nx/nx-842.h

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drivers/crypto/nx/nx-aes-ccm.c

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drivers/crypto/nx/nx-aes-gcm.c

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drivers/crypto/nx/nx-common-powernv.c

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drivers/crypto/nx/nx-common-pseries.c

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drivers/crypto/nx/nx.c

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drivers/crypto/nx/nx.h

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drivers/crypto/padlock-sha.c

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drivers/crypto/s5p-sss.c

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drivers/crypto/stm32/stm32-cryp.c

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drivers/crypto/tegra/tegra-se-aes.c

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drivers/crypto/tegra/tegra-se-hash.c

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drivers/crypto/tegra/tegra-se-key.c

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drivers/crypto/tegra/tegra-se-main.c

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drivers/crypto/tegra/tegra-se.h

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drivers/crypto/virtio/virtio_crypto_akcipher_algs.c

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drivers/crypto/virtio/virtio_crypto_core.c

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drivers/crypto/virtio/virtio_crypto_mgr.c

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drivers/crypto/virtio/virtio_crypto_skcipher_algs.c

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fs/ubifs/compress.c

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fs/ubifs/file.c

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fs/ubifs/journal.c

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fs/ubifs/ubifs.h

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include/crypto/acompress.h

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include/crypto/algapi.h

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include/crypto/authenc.h

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include/crypto/chacha.h

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include/crypto/ctr.h

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include/crypto/hash.h

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include/crypto/internal/acompress.h

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include/crypto/internal/hash.h

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include/crypto/internal/scompress.h

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include/crypto/internal/skcipher.h

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include/crypto/krb5.h

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include/crypto/scatterwalk.h

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include/crypto/sig.h

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include/crypto/skcipher.h

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include/dt-bindings/reset/rockchip,rk3588-cru.h

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include/linux/async_tx.h

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include/linux/crypto.h

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include/linux/lzo.h

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include/linux/math.h

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include/linux/scatterlist.h

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include/linux/spinlock.h

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include/net/ipcomp.h

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include/uapi/linux/psp-sev.h

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kernel/power/hibernate.c

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kernel/power/swap.c

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lib/842/842_compress.c

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lib/crypto/Kconfig

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lib/crypto/chacha20poly1305.c

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lib/lzo/Makefile

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lib/lzo/lzo1x_compress.c

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lib/lzo/lzo1x_compress_safe.c

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lib/scatterlist.c

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net/tls/tls_device_fallback.c

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net/xfrm/xfrm_algo.c

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net/xfrm/xfrm_ipcomp.c

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security/keys/Kconfig

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tools/testing/crypto/chacha20-s390/test-cipher.c

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